coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: fdde2eb hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
by Alexandru Gagniuc 20 Apr '14

20 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5556 -gerrit commit fdde2eb470d8994ec4363915b3326d9c618d7bcb Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 16:22:53 2014 -0500 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18 The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly. Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 10 ++++------ src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 2 ++ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 7375a4b..a6d2d7b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -65,12 +65,10 @@ Scope(\_GPE) { /* Start Scope GPE */ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Store("PCI bridge wake event", Debug) + /* Notify PCI bridges of wake event */ + Notify(\_SB.PCI0.PBR4, 0x02) + Notify(\_SB.PCI0.PBR5, 0x02) } /* Azalia SCI event */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8b48476..df0f8fd 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -386,6 +386,7 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, + {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h index 8e51a77..95febb7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -12,6 +12,7 @@ #define EC_SCI_GEVENT 3 #define EC_LID_GEVENT 22 #define EC_SMI_GEVENT 23 +#define PCIE_GEVENT 8 /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but * we make the distinction between GEVENT pin and SCI. @@ -19,5 +20,6 @@ #define EC_SCI_GPE EC_SCI_GEVENT #define EC_LID_GPE EC_LID_GEVENT #define PME_GPE 0x0b +#define PCIE_GPE 0x18 #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H */

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Patch set updated for coreboot: cbf3322 southbridge/amd/agesa/hudson: Refactor SPI controller driver
by Alexandru Gagniuc 20 Apr '14

20 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5557 -gerrit commit cbf332249aedc7d9f9de45fb301083e5214940a9 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 22:21:27 2014 -0500 southbridge/amd/agesa/hudson: Refactor SPI controller driver The SPI controller driver used numerical offsets to access SPI registers, making it unreadable without the datasheet. Use less magic and more #defines to improve readability. Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/spi.c | 69 ++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 19 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index a46bf08..f0f75c8 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -31,23 +31,54 @@ static int bus_claimed = 0; #endif +#define SPI_REG_OPCODE 0x0 +#define SPI_REG_CNTRL01 0x1 +#define SPI_REG_CNTRL02 0x2 + #define CNTRL02_FIFO_RESET (1 << 4) + #define CNTRL02_EXEC_OPCODE (1 << 0) +#define SPI_REG_CNTRL03 0x3 + #define CNTRL03_SPIBUSY (1 << 7) +#define SPI_REG_FIFO 0xc +#define SPI_REG_CNTRL11 0xd + #define CNTRL11_FIFOPTR_MASK 0x07 + + static u32 spibar; +static inline uint8_t spi_read(uint8_t reg) +{ + return read8(spibar + reg); +} + +static inline void spi_write(uint8_t reg, uint8_t val) +{ + write8(spibar + reg, val); +} + static void reset_internal_fifo_pointer(void) { + uint8_t reg8; + do { - write8(spibar + 2, read8(spibar + 2) | 0x10); - } while (read8(spibar + 0xD) & 0x7); + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_FIFO_RESET; + spi_write(SPI_REG_CNTRL02, reg8); + } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); } static void execute_command(void) { - write8(spibar + 2, read8(spibar + 2) | 1); + uint8_t reg8; + + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_EXEC_OPCODE; + spi_write(SPI_REG_CNTRL02, reg8); - while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); + while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && + (spi_read(SPI_REG_CNTRL02) & CNTRL03_SPIBUSY)); } -void spi_init() +void spi_init(void) { device_t dev; @@ -59,13 +90,13 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { /* First byte is cmd which can not being sent through FIFO. */ - u8 cmd = *(u8 *)dout++; - u8 readoffby1; + uint8_t cmd = *(uint8_t *)dout++; + uint8_t readoffby1; #if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE - u8 readwrite; + uint8_t readwrite; #endif - u8 bytesout, bytesin; - u8 count; + uint8_t bytesout, bytesin; + uint8_t count; bitsout -= 8; bytesout = bitsout / 8; @@ -74,19 +105,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE - write8(spibar + 0x1E, 5); - write8(spibar + 0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ - write8(spibar + 0x1E, 6); - write8(spibar + 0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ + spi_write(0x1E, 5); + spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + spi_write(0x1E, 6); + spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ #else readwrite = (bytesin + readoffby1) << 4 | bytesout; - write8(spibar + 1, readwrite); + spi_write(SPI_REG_CNTRL01, readwrite); #endif - write8(spibar + 0, cmd); + spi_write(SPI_REG_OPCODE, cmd); reset_internal_fifo_pointer(); for (count = 0; count < bytesout; count++, dout++) { - write8(spibar + 0x0C, *(u8 *)dout); + spi_write(SPI_REG_FIFO, *(uint8_t *)dout); } reset_internal_fifo_pointer(); @@ -95,12 +126,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout, reset_internal_fifo_pointer(); /* Skip the bytes we sent. */ for (count = 0; count < bytesout; count++) { - cmd = read8(spibar + 0x0C); + cmd = spi_read(SPI_REG_FIFO); } reset_internal_fifo_pointer(); for (count = 0; count < bytesin; count++, din++) { - *(u8 *)din = read8(spibar + 0x0C); + *(uint8_t *)din = spi_read(SPI_REG_FIFO); } return 0;

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Patch merged into coreboot/master: 46b0951 Move MAX_PHYSICAL_CPUS to AMD k8 and fam10
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 46b0951182c07b7bcd86fd2b66ac162d99eee3f3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 17 15:07:47 2014 +0300 Move MAX_PHYSICAL_CPUS to AMD k8 and fam10 This was always AMD-only and it was never properly used with AGESA. Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5540 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5540 for details. -gerrit

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Patch merged into coreboot/master: a6c525a AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit a6c525a7d5ad0dedc31dcc9719be6bc5fbc743dd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 16 09:43:40 2014 +0300 AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS Following boards use cimx/sb700: amd/dinar supermicro/h8qgi supermicro/h8scm tyan/s8226 Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0. There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1). Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0. Together with documented 4-bit restriction for APIC ID field, this APIC ID programming matches with MP tables and ACPI tables. I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which we do not have in the tree. Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5539 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5539 for details. -gerrit

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Patch merged into coreboot/master: 35546de AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 35546deba642d3bb341d329fc1b9711727a5c50e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 17 15:07:32 2014 +0300 AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1. Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5538 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5538 for details. -gerrit

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Patch merged into coreboot/master: 9816392 amd/torpedo: Remove unused Kconfig options
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 981639233766a95b9642f7268519eafeccc57464 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 16 09:43:40 2014 +0300 amd/torpedo: Remove unused Kconfig options These are not used with cimx/sb900 vendorcode. Change-Id: I489ee80c739b31edac649491497162c65316996e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5537 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5537 for details. -gerrit

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Patch merged into coreboot/master: 29c3e36 AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 29c3e367da8f80becacb66193d044f90b49bf0c5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 16 16:30:00 2014 +0300 AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS Match the definition of NODE_PCI() with get_node_pci(), so romstage and ramstage agree of the PCI BDFs for nodes. Note that all board have CONFIG_CDB = 0x18 and the maximum for nodes = 8, so we always have (CONFIG_CDB + x) < 32. Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5536 for details. -gerrit

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Patch merged into coreboot/master: b1ccccc mainboard: New port Packard Bell LM85.
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit b1ccccc2073c40f622f5c0b2e861c3e8453a94f9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 19 22:20:14 2014 +0100 mainboard: New port Packard Bell LM85. Change-Id: I8c1548470c605d06825fe35579879e806bf33542 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/5271 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5271 for details. -gerrit

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Patch merged into coreboot/master: 5c97142 drivers/elog: Fix implicit function declaration issue
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 5c97142419a7b7204786fea5b785c23a3bb41836 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 15 14:32:53 2014 +1000 drivers/elog: Fix implicit function declaration issue Fix compilation. Relying on the pre-processor to condition an if statement will lead to warnings of implicitly defined functions. To solve this dilemma add symbols to resolve to at compile time. Change-Id: Id0117528c5579cc1dec750a8a17a76fab4314b3f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5504 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5504 for details. -gerrit

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Patch set updated for coreboot: 34f5a4b drivers/elog: Fix implicit function declaration issue
by Edward O'Callaghan 20 Apr '14

20 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5504 -gerrit commit 34f5a4b220605716824645d1cffa210dc0dab614 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 15 14:32:53 2014 +1000 drivers/elog: Fix implicit function declaration issue Fix compilation. Relying on the pre-processor to condition an if statement will lead to warnings of implicitly defined functions. To solve this dilemma add symbols to resolve to at compile time. Change-Id: Id0117528c5579cc1dec750a8a17a76fab4314b3f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/elog.h | 4 +++- src/include/pc80/mc146818rtc.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/include/elog.h b/src/include/elog.h index f9b5d53..eb8352d 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -162,7 +162,9 @@ extern u32 gsmi_exec(u8 command, u32 *param); #if CONFIG_ELOG_BOOT_COUNT u32 boot_count_read(void); u32 boot_count_increment(void); -#endif +#else +static inline u32 boot_count_read(void) { return 0; } +#endif /* CONFIG_ELOG_BOOT_COUNT */ #endif /* !CONFIG_ELOG */ diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index fd40308..cf4a951 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -220,6 +220,8 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)), #define CMOS_POST_EXTRA_DEV_PATH 0x01 void cmos_post_log(void); +#else +static inline void cmos_post_log(void) {} #endif /* CONFIG_CMOS_POST */ #endif /* PC80_MC146818RTC_H */

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coreboot-gerrit April 2014