coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

1 participants
779 discussions

New patch to review for coreboot: 46844ee hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file
by Alexandru Gagniuc 19 Apr '14

19 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5547 -gerrit commit 46844ee5956bb06221d8eae29a907704bf65b74a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 19:53:51 2014 -0500 hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file These definitions were scattered in a couple of files, and we risk scattering them all over the place. Provide a common file for these definitions. Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl | 6 ++---- src/mainboard/hp/pavilion_m6_1035dx/ec.h | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 22 ++++++++++++++++++++++ 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl index 188515c..0293a12 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/ec.asl @@ -3,10 +3,8 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -/* - * EC bits specific to the mainboard - */ -#define EC_SCI_GPE 3 +/* Defines EC bits specific to the mainboard, needed by EC ASL */ +#include "mainboard.h" /* ACPI code for EC functions */ #include <ec/compal/ene932/acpi/ec.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 7eb4d06..61ecc06 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -6,8 +6,7 @@ #ifndef _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H #define _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H -#define EC_SMI_GEVENT 23 -#define EC_LID_GEVENT 22 +#include "mainboard.h" #ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h new file mode 100644 index 0000000..1e69cc9 --- /dev/null +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -0,0 +1,22 @@ +/* + * "The way things are connected" and a few setup options + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H +#define _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H + +/* What is connected to GEVENT pins */ +#define EC_SCI_GEVENT 3 +#define EC_LID_GEVENT 22 +#define EC_SMI_GEVENT 23 + +/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but + * we make the distinction between GEVENT pin and SCI. + */ +#define EC_SCI_GPE EC_SCI_GEVENT + + +#endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H */

1 0

Patch set updated for coreboot: dcbbc02 AMD hudson and yangtze boards: Let mainboard declare power button
by Alexandru Gagniuc 19 Apr '14

19 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5546 -gerrit commit dcbbc02d2979e2454be104664e52fb0b46c2e0dc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 01:42:19 2014 -0500 AMD hudson and yangtze boards: Let mainboard declare power button The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/amd/olivehill/acpi/gpe.asl | 8 ++++---- src/mainboard/amd/olivehill/dsdt.asl | 7 +++++++ src/mainboard/amd/parmer/acpi/gpe.asl | 8 ++++---- src/mainboard/amd/parmer/dsdt.asl | 7 +++++++ src/mainboard/amd/thatcher/acpi/gpe.asl | 8 ++++---- src/mainboard/amd/thatcher/dsdt.asl | 7 +++++++ src/mainboard/asrock/imb-a180/acpi/gpe.asl | 8 ++++---- src/mainboard/asrock/imb-a180/dsdt.asl | 7 +++++++ src/mainboard/asus/f2a85-m/acpi/gpe.asl | 8 ++++---- src/mainboard/asus/f2a85-m/dsdt.asl | 7 +++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 +++--- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 6 ++++++ src/southbridge/amd/agesa/hudson/acpi/fch.asl | 7 ------- 13 files changed, 64 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl index f294502..8d4f8a2 100644 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ b/src/mainboard/amd/olivehill/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index e0c21cf..d2d8122 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -56,6 +56,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 40a19d4..22a3957 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index ef2ae6f..21b2090 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -55,6 +55,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 40a19d4..22a3957 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index ef2ae6f..21b2090 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -55,6 +55,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/asrock/imb-a180/acpi/gpe.asl b/src/mainboard/asrock/imb-a180/acpi/gpe.asl index f294502..8d4f8a2 100644 --- a/src/mainboard/asrock/imb-a180/acpi/gpe.asl +++ b/src/mainboard/asrock/imb-a180/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 78d9bca..cecaa59 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -56,6 +56,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl index 956d5d1..a5ec91a 100644 --- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl +++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -64,13 +64,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Method(_L18) { /* DBGO("\\_GPE\\_L18\n") */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index bb9c0fe..a1a95b2 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -55,6 +55,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index a240308..89c002a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -40,7 +40,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -61,13 +61,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 6a10038..5700e86 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -103,4 +103,10 @@ Scope (\_SB) { Return(GE22) } } + + Device(PWRB) { + Name(_HID, EisaId("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) + } } diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index f56b69c..b04bc59 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -204,10 +204,3 @@ Method(CkOT, 0){ } Return(OSTP) } - -Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ -}

1 0

Patch merged into coreboot/master: 7f09b75 hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method
by gerrit＠coreboot.org 19 Apr '14

19 Apr '14

the following patch was just integrated into master: commit 7f09b754f982bc232a112a5593da08b3e24db509 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Apr 9 20:52:46 2014 -0500 hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5517 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/5517 for details. -gerrit

1 0

Patch merged into coreboot/master: 5db38a3 hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey
by gerrit＠coreboot.org 19 Apr '14

19 Apr '14

the following patch was just integrated into master: commit 5db38a38c9e3dd50e2e513414a2a1b7ab80250a4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Apr 9 20:51:41 2014 -0500 hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5516 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/5516 for details. -gerrit

1 0

Patch merged into coreboot/master: fa84067 ec/compal/ene932: Update to use coreboot EC-mainboard API
by gerrit＠coreboot.org 19 Apr '14

19 Apr '14

the following patch was just integrated into master: commit fa840676f5f3bd92b63c352f0c8bf6f14bc2c314 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Apr 9 21:07:43 2014 -0500 ec/compal/ene932: Update to use coreboot EC-mainboard API This patch implements a simple interface between the EC and mainboard ASL code. This interface does not rely on the preprocessor, and prevents name conflicts by scoping the interface methods. As this interface is documented on the coreboot wiki, an in-tree documentation is not provided. Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5515 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5515 for details. -gerrit

1 0

Patch merged into coreboot/master: 91b6d3a hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"
by gerrit＠coreboot.org 19 Apr '14

19 Apr '14

the following patch was just integrated into master: commit 91b6d3a6b9430c94989d37982a56ead948419e78 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 01:01:10 2014 -0500 hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID" There is only one lid switch, so it does not make sense to number it. This naming is also consistent with the examples in the ACPI spec. Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5545 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/5545 for details. -gerrit

1 0

New patch to review for coreboot: 284d686 AMD hudson and yangtze boards: Let mainboard declare power button
by Alexandru Gagniuc 19 Apr '14

19 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5546 -gerrit commit 284d6860548abe86de7202417800308f70940c64 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 01:42:19 2014 -0500 AMD hudson and yangtze boards: Let mainboard declare power button The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/amd/olivehill/acpi/gpe.asl | 8 ++++---- src/mainboard/amd/olivehill/dsdt.asl | 7 +++++++ src/mainboard/amd/parmer/acpi/gpe.asl | 8 ++++---- src/mainboard/amd/parmer/dsdt.asl | 7 +++++++ src/mainboard/amd/thatcher/acpi/gpe.asl | 8 ++++---- src/mainboard/amd/thatcher/dsdt.asl | 7 +++++++ src/mainboard/asrock/imb-a180/acpi/gpe.asl | 8 ++++---- src/mainboard/asrock/imb-a180/dsdt.asl | 7 +++++++ src/mainboard/asus/f2a85-m/acpi/gpe.asl | 8 ++++---- src/mainboard/asus/f2a85-m/dsdt.asl | 7 +++++++ src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 6 +++--- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 6 ++++++ src/southbridge/amd/agesa/hudson/acpi/fch.asl | 7 ------- 13 files changed, 64 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl index f294502..8d4f8a2 100644 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ b/src/mainboard/amd/olivehill/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index e0c21cf..d2d8122 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -56,6 +56,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 40a19d4..22a3957 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index ef2ae6f..21b2090 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -55,6 +55,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 40a19d4..22a3957 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -67,13 +67,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index ef2ae6f..21b2090 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -55,6 +55,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/asrock/imb-a180/acpi/gpe.asl b/src/mainboard/asrock/imb-a180/acpi/gpe.asl index f294502..8d4f8a2 100644 --- a/src/mainboard/asrock/imb-a180/acpi/gpe.asl +++ b/src/mainboard/asrock/imb-a180/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -66,13 +66,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 78d9bca..cecaa59 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -56,6 +56,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl index 956d5d1..a5ec91a 100644 --- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl +++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl @@ -22,7 +22,7 @@ Scope(\_GPE) { /* Start Scope GPE */ /* General event 3 */ Method(_L03) { /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Legacy PM event */ @@ -46,7 +46,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -64,13 +64,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Method(_L18) { /* DBGO("\\_GPE\\_L18\n") */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index bb9c0fe..a1a95b2 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -55,6 +55,13 @@ DefinitionBlock ( /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ #include "acpi/routing.asl" + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + Device(PCI0) { /* Describe the AMD Northbridge */ #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index a240308..89c002a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -40,7 +40,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* ExtEvent0 SCI event */ @@ -61,13 +61,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index e30d083..f3f4209 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -82,4 +82,10 @@ Scope (\_SB) { Return (\LIDS) } } + + Device(PWRB) { + Name(_HID, EisaId("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) + } } diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index f56b69c..b04bc59 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -204,10 +204,3 @@ Method(CkOT, 0){ } Return(OSTP) } - -Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ -}

1 0

New patch to review for coreboot: ee0e186 hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"
by Alexandru Gagniuc 19 Apr '14

19 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5545 -gerrit commit ee0e186c71ad1f795e94b32ce4e4849d68c911b3 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 01:01:10 2014 -0500 hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID" There is only one lid switch, so it does not make sense to number it. This naming is also consistent with the examples in the ACPI spec. Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl index 47d7872..e30d083 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl @@ -73,7 +73,7 @@ } Scope (\_SB) { - Device (LID0) + Device (LID) { Name(_HID, EisaId("PNP0C0D")) Method(_LID, 0)

1 0

Patch set updated for coreboot: 0410a49 Move MAX_PHYSICAL_CPUS to AMD k8 and fam10
by Kyösti Mälkki 18 Apr '14

18 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5540 -gerrit commit 0410a491d7dd9a12e52f44856c0ea3dff18e3cfd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 17 15:07:47 2014 +0300 Move MAX_PHYSICAL_CPUS to AMD k8 and fam10 This was always AMD-only and it was never properly used with AGESA. Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/Kconfig | 7 ------- src/cpu/amd/model_10xxx/Kconfig | 4 ++++ src/cpu/amd/model_fxx/Kconfig | 4 ++++ 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f3883d3..bf5ce8e 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -29,13 +29,6 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex -# FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better -# yet be dropped completely. -config MAX_PHYSICAL_CPUS - int - depends on CPU_AMD_MODEL_10XXX || CPU_AMD_MODEL_FXX || CPU_AMD_AGESA - default 1 - config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 99358e0..bc20219 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -32,6 +32,10 @@ config SET_FIDVID bool default y +config MAX_PHYSICAL_CPUS + int + default 1 + config LIFT_BSP_APIC_ID bool default n diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index fb094b1..2ea381e 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -11,6 +11,10 @@ config UDELAY_IO bool default n +config MAX_PHYSICAL_CPUS + int + default 1 + config LIFT_BSP_APIC_ID bool default n

1 0

Patch set updated for coreboot: 8de78af AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
by Kyösti Mälkki 18 Apr '14

18 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5539 -gerrit commit 8de78af7b8ff0b8a5101ff7cd1be91d8ea305aad Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 16 09:43:40 2014 +0300 AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS Following boards use cimx/sb700: amd/dinar supermicro/h8qgi supermicro/h8scm tyan/s8226 Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0. There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1). Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0. Together with documented 4-bit restriction for APIC ID field, this APIC ID programming matches with MP tables and ACPI tables. I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which we do not have in the tree. Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/Kconfig | 8 -------- src/mainboard/amd/dinar/acpi_tables.c | 11 +++++------ src/mainboard/amd/dinar/mptable.c | 11 +++++------ src/mainboard/supermicro/h8qgi/Kconfig | 4 ---- src/mainboard/supermicro/h8qgi/acpi_tables.c | 11 +++++------ src/mainboard/supermicro/h8qgi/mptable.c | 9 ++++----- src/mainboard/supermicro/h8scm/Kconfig | 4 ---- src/mainboard/supermicro/h8scm/acpi_tables.c | 11 +++++------ src/mainboard/supermicro/h8scm/mptable.c | 9 ++++----- src/mainboard/tyan/s8226/Kconfig | 4 ---- src/mainboard/tyan/s8226/acpi_tables.c | 11 +++++------ src/mainboard/tyan/s8226/mptable.c | 9 ++++----- src/southbridge/amd/cimx/sb700/late.c | 15 ++++----------- 13 files changed, 41 insertions(+), 76 deletions(-) diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index b5434b4..6768a57 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -42,10 +42,6 @@ config MAINBOARD_DIR string default amd/dinar -config APIC_ID_OFFSET - hex - default 0x0 - config MAINBOARD_PART_NUMBER string default "Dinar" @@ -58,10 +54,6 @@ config MAX_CPUS int default 64 -config MAX_PHYSICAL_CPUS - int - default 16 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index c4a42dc..b010565 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -73,12 +73,11 @@ unsigned long acpi_fill_madt(unsigned long current) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sb700 = 0x0; -#else - apicid_sb700 = CONFIG_MAX_CPUS + 1 -#endif - apicid_rd890 = apicid_sb700 + 1; + if (CONFIG_MAX_CPUS >= 16) + apicid_sb700 = 0x0; + else + apicid_sb700 = CONFIG_MAX_CPUS + 1; + apicid_rd890 = apicid_sb700 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 60779f8..5f9e83b 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -58,12 +58,11 @@ static void *smp_write_config_table(void *v) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sb700 = 0x0; -#else - apicid_sb700 = CONFIG_MAX_CPUS + 1 -#endif - apicid_rd890 = apicid_sb700 + 1; + if (CONFIG_MAX_CPUS >= 16) + apicid_sb700 = 0x0; + else + apicid_sb700 = CONFIG_MAX_CPUS + 1; + apicid_rd890 = apicid_sb700 + 1; //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 6371d9e..2ff782a 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -54,10 +54,6 @@ config MAX_CPUS int default 64 -config MAX_PHYSICAL_CPUS - int - default 16 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index 0b62af7..90d39bc 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -72,12 +72,11 @@ unsigned long acpi_fill_madt(unsigned long current) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sp5100 = 0x0; -#else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 -#endif - apicid_sr5650 = apicid_sp5100 + 1; + if (CONFIG_MAX_CPUS >= 16) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index c10a219..0365ae6 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -58,11 +58,10 @@ static void *smp_write_config_table(void *v) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sp5100 = 0x0; -#else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 -#endif + if (CONFIG_MAX_CPUS >= 16) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 86395e4..7260f99 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -53,10 +53,6 @@ config MAX_CPUS int default 64 -config MAX_PHYSICAL_CPUS - int - default 16 - config CPU_ADDR_BITS int default 36 # TODO: Set it conservatively to match both fam10 & 15 diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c index 05c9995..ffcdf1c 100644 --- a/src/mainboard/supermicro/h8scm/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -72,12 +72,11 @@ unsigned long acpi_fill_madt(unsigned long current) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sp5100 = 0x0; -#else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 -#endif - apicid_sr5650 = apicid_sp5100 + 1; + if (CONFIG_MAX_CPUS >= 16) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index c10a219..0365ae6 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -58,11 +58,10 @@ static void *smp_write_config_table(void *v) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sp5100 = 0x0; -#else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 -#endif + if (CONFIG_MAX_CPUS >= 16) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 68ce152..e8d2f88 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -54,10 +54,6 @@ config MAX_CPUS int default 64 -config MAX_PHYSICAL_CPUS - int - default 2 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c index 0cac914..fde10f1 100644 --- a/src/mainboard/tyan/s8226/acpi_tables.c +++ b/src/mainboard/tyan/s8226/acpi_tables.c @@ -72,12 +72,11 @@ unsigned long acpi_fill_madt(unsigned long current) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sp5100 = 0x0; -#else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 -#endif - apicid_sr5650 = apicid_sp5100 + 1; + if (CONFIG_MAX_CPUS >= 16) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index c10a219..0365ae6 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -58,11 +58,10 @@ static void *smp_write_config_table(void *v) * For systems with < 16 APICs, put the Local-APICs at 0..n and * put the IO-APICs at (n + 1)..z */ -#if CONFIG_MAX_CPUS >= 16 - apicid_sp5100 = 0x0; -#else - apicid_sp5100 = CONFIG_MAX_CPUS + 1 -#endif + if (CONFIG_MAX_CPUS >= 16) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index b03f13a..9605083 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -218,22 +218,15 @@ static void sb700_enable(device_t dev) case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { -#if 1 u32 ioapic_base; printk(BIOS_DEBUG, "sm_init().\n"); ioapic_base = IO_APIC_ADDR; clear_ioapic(ioapic_base); /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ -#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS)); -#elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ - setup_ioapic(ioapic_base, 0); -#else -#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" -#endif -#endif + if (CONFIG_MAX_CPUS >= 16) + setup_ioapic(ioapic_base, 0); + else + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1); } break;

1 0

← Newer
1
...
28
29
30
31
32
33
34
...
78
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2014