coreboot-gerrit April 2014

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Patch merged into coreboot/master: dbe6336 hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
by gerrit＠coreboot.org 18 Apr '14

18 Apr '14

the following patch was just integrated into master: commit dbe6336f908800ec028dc1a1087d6782e5a38851 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 17 00:47:47 2014 -0500 hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS Intercept the low battery SMI from the EC, and shut down the system immediately. The EC only sends this SMI when the OS did not enable ACPI mode, so ACPI OSes are not affected by this. On the other hand, payloads such as GRUB or SeaBIOS will experience the shutdown. This behavior is helpful for protecting the battery, for example, when the OS fails to boot and we are stuck in the payload. The low battery SMI is triggered at 10% charge, at which point the risk of cell degradation exists. Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5527 for details. -gerrit

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Patch set updated for coreboot: 975689c hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS
by Alexandru Gagniuc 18 Apr '14

18 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/171 -gerrit commit 975689c1fe1d3bdee1a598f09b45444f96d00c1d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 17 23:41:19 2014 -0500 hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS This is handled by generating an SMI when GEVENT22 goes low. This pin is driven by the EC when the lid opens or closes. This SMI is disabled when switching to ACPI mode, so ACPI OSes are not affected. Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/ec.h | 1 + src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c | 12 ++++++++++++ 3 files changed, 14 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 579bf7e..7eb4d06 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -7,6 +7,7 @@ #define _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H #define EC_SMI_GEVENT 23 +#define EC_LID_GEVENT 22 #ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index ccabaf2..2e8436b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -42,6 +42,7 @@ static void mainboard_enable(device_t dev) pavilion_m6_1035dx_ec_init(); hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); + hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW); hudson_enable_smi_generation(); /* diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index f911443..386d390 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -12,6 +12,7 @@ #include <delay.h> #include <ec/compal/ene932/ec.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smi.h> #define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) @@ -71,16 +72,25 @@ static void handle_ec_smi(void) ec_process_smi(src); } +static void handle_lid_smi(void) +{ + /* Only triggered in non-ACPI mode on lid close. */ + outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK); +} + int mainboard_smi_apmc(uint8_t data) { switch (data) { case ACPI_SMI_CMD_ENABLE: printk(BIOS_DEBUG, "Enable ACPI mode\n"); ec_enter_acpi_mode(); + hudson_disable_gevent_smi(EC_LID_GEVENT); break; case ACPI_SMI_CMD_DISABLE: printk(BIOS_DEBUG, "Disable ACPI mode\n"); ec_enter_apm_mode(); + hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, + SMI_LVL_LOW); break; default: printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); @@ -92,4 +102,6 @@ void mainboard_smi_gpi(uint32_t gpi_sts) { if (gpi_sts & (1 << EC_SMI_GEVENT)) handle_ec_smi(); + if (gpi_sts & (1 << EC_LID_GEVENT)) + handle_lid_smi(); }

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Patch set updated for coreboot: b2cd5bc hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS
by Alexandru Gagniuc 18 Apr '14

18 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/171 -gerrit commit b2cd5bc42f4d22f13ee06c8dd58b439af6bcae3c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 17 23:41:19 2014 -0500 hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS This is handled by generating an SMI when GEVENT22 goes low. This pin is driven by the EC when the lid opens or closes. This SMI is disabled when switching to ACPI mode, so ACPI OSes are not affected. Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/ec.h | 1 + src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c | 12 ++++++++++++ 3 files changed, 14 insertions(+) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.h b/src/mainboard/hp/pavilion_m6_1035dx/ec.h index 579bf7e..7eb4d06 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/ec.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.h @@ -7,6 +7,7 @@ #define _MAINBOARD_HP_PAVILION_M6_1035DX_EC_H #define EC_SMI_GEVENT 23 +#define EC_LID_GEVENT 22 #ifndef __SMM__ void pavilion_m6_1035dx_ec_init(void); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index ccabaf2..2e8436b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -42,6 +42,7 @@ static void mainboard_enable(device_t dev) pavilion_m6_1035dx_ec_init(); hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); + hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW); hudson_enable_smi_generation(); /* diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index f911443..e309494 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -12,6 +12,7 @@ #include <delay.h> #include <ec/compal/ene932/ec.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/smi.h> #define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) @@ -71,16 +72,25 @@ static void handle_ec_smi(void) ec_process_smi(src); } +static void handle_lid_smi(void) +{ + /* Only triggered in non-ACPI mode on lid close. */ + outl(ACPI_PM1_CNT_SLEEP(4), ACPI_PM1_CNT_BLK); +} + int mainboard_smi_apmc(uint8_t data) { switch (data) { case ACPI_SMI_CMD_ENABLE: printk(BIOS_DEBUG, "Enable ACPI mode\n"); ec_enter_acpi_mode(); + hudson_disable_gevent_smi(EC_LID_GEVENT); break; case ACPI_SMI_CMD_DISABLE: printk(BIOS_DEBUG, "Disable ACPI mode\n"); ec_enter_apm_mode(); + hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, + SMI_LVL_LOW); break; default: printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); @@ -92,4 +102,6 @@ void mainboard_smi_gpi(uint32_t gpi_sts) { if (gpi_sts & (1 << EC_SMI_GEVENT)) handle_ec_smi(); + if (gpi_sts & (1 << EC_LID_GEVENT)) + handle_lid_smi(); }

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Patch set updated for coreboot: 98b1129 southbridge/hudson: Compile refactored SMI setup utilities in SMM
by Alexandru Gagniuc 18 Apr '14

18 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/170 -gerrit commit 98b11298a3b68c95a49b974cbeccac5d5becad00 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 17 23:33:50 2014 -0500 southbridge/hudson: Compile refactored SMI setup utilities in SMM Refactor hudson_enable_gevent_smi() to allow configuring the interrupt mode and trigger level. Move the utilities which are useful in SMM to a separate file that is included in both ramstage and SMM. This is useful for SMI handlers which need to enable or disable GEVENT SMIs on-the-fly. A follow-up patch makes use of this infrastructure. Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +- src/southbridge/amd/agesa/hudson/smi.c | 43 ------------- src/southbridge/amd/agesa/hudson/smi.h | 21 ++++--- src/southbridge/amd/agesa/hudson/smi_util.c | 80 +++++++++++++++++++++++++ 5 files changed, 97 insertions(+), 53 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 756b443..ccabaf2 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -41,7 +41,7 @@ static void mainboard_enable(device_t dev) pavilion_m6_1035dx_ec_init(); - hudson_enable_gevent_smi(EC_SMI_GEVENT); + hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); /* diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b92e850..398ca90 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -22,8 +22,8 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c romstage-y += imc.c ramstage-y += imc.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 168f2ac..1d58afe 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -10,8 +10,6 @@ #include <console/console.h> #include <cpu/cpu.h> -#define HUDSON_SMI_ACPI_COMMAND 75 - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); @@ -25,44 +23,3 @@ void hudson_enable_smi_generation(void) reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); } - -static void enable_smi(uint8_t smi_num) -{ - uint8_t reg32_offset, bit_offset; - uint32_t reg32; - - /* SMI sources range from [0:149] */ - if (smi_num > 149) { - printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); - return; - } - - /* 16 sources per register, 2 bits per source; registers are 4 bytes */ - reg32_offset = (smi_num / 16) * 4; - bit_offset = (smi_num % 16) * 2; - - reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); - reg32 &= ~(3 << (bit_offset)); - reg32 |= (SMI_SRC_MODE_SMI << (bit_offset)); - smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); - -} - -/** Enable generation of SMIs for given GPE */ -void hudson_enable_gevent_smi(uint8_t gevent) -{ - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - enable_smi(gevent); -} - -/** Enable SMIs on writes to ACPI SMI command port */ -void hudson_enable_acpi_cmd_smi(void) -{ - enable_smi(HUDSON_SMI_ACPI_COMMAND); -} diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 7932228..53da00a 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -22,11 +22,16 @@ #define SMI_REG_CONTROL0 0xa0 -enum smi_src_mode { - SMI_SRC_MODE_DISABLE = 0, - SMI_SRC_MODE_SMI = 1, - SMI_SRC_MODE_NMI = 2, - SMI_SRC_MODE_IRQ13 = 3, +enum smi_mode { + SMI_MODE_DISABLE = 0, + SMI_MODE_SMI = 1, + SMI_MODE_NMI = 2, + SMI_MODE_IRQ13 = 3, +}; + +enum smi_lvl { + SMI_LVL_LOW = 0, + SMI_LVL_HIGH = 1, }; static inline uint32_t smi_read32(uint8_t offset) @@ -49,10 +54,12 @@ static inline void smi_write16(uint8_t offset, uint16_t value) write16(SMI_BASE + offset, value); } +void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void hudson_disable_gevent_smi(uint8_t gevent); +void hudson_enable_acpi_cmd_smi(void); + #ifndef __SMM__ void hudson_enable_smi_generation(void); -void hudson_enable_gevent_smi(uint8_t gevent); -void hudson_enable_acpi_cmd_smi(void); #endif #endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c new file mode 100644 index 0000000..75137ec --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -0,0 +1,80 @@ +/* + * SMM utilities used in both SMM and normal mode + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "smi.h" + +#include <console/console.h> + +#define HUDSON_SMI_ACPI_COMMAND 75 + +static void configure_smi(uint8_t smi_num, uint8_t mode) +{ + uint8_t reg32_offset, bit_offset; + uint32_t reg32; + + /* SMI sources range from [0:149] */ + if (smi_num > 149) { + printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); + return; + } + + /* 16 sources per register, 2 bits per source; registers are 4 bytes */ + reg32_offset = (smi_num / 16) * 4; + bit_offset = (smi_num % 16) * 2; + + reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); + reg32 &= ~(3 << (bit_offset)); + reg32 |= (mode << (bit_offset)); + smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); + +} + +/** + * Configure generation of interrupts for given GEVENT pin + * + * @param gevent The GEVENT pin number. Valid values are 0 thru 23 + * @param mode The type of event this pin should generate. Note that only + * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. + * @param level SMI_LVL_LOW or SMI_LVL_HIGH + */ +void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +{ + uint32_t reg32; + /* GEVENT pins range from [0:23] */ + if (gevent > 23) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, mode); + + /* And set set the trigger level */ + reg32 = smi_read32(SMI_REG_SMITRIG0); + reg32 &= ~(1 << gevent); + reg32 |= (level & 0x1) << gevent; + smi_write32(SMI_REG_SMITRIG0, reg32); +} + +/** Disable events from given GEVENT pin */ +void hudson_disable_gevent_smi(uint8_t gevent) +{ + /* GEVENT pins range from [0:23] */ + if (gevent > 23) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, SMI_MODE_DISABLE); +} + +/** Enable SMIs on writes to ACPI SMI command port */ +void hudson_enable_acpi_cmd_smi(void) +{ + configure_smi(HUDSON_SMI_ACPI_COMMAND, SMI_MODE_SMI); +}

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Patch set updated for coreboot: dbe036e hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
by Alexandru Gagniuc 18 Apr '14

18 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5527 -gerrit commit dbe036e07d70408acd09f27c9bdcfbe77a39a2bc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 17 00:47:47 2014 -0500 hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS Intercept the low battery SMI from the EC, and shut down the system immediately. The EC only sends this SMI when the OS did not enable ACPI mode, so ACPI OSes are not affected by this. On the other hand, payloads such as GRUB or SeaBIOS will experience the shutdown. This behavior is helpful for protecting the battery, for example, when the OS fails to boot and we are stuck in the payload. The low battery SMI is triggered at 10% charge, at which point the risk of cell degradation exists. Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- .../hp/pavilion_m6_1035dx/mainboard_smi.c | 26 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index bb9cc2e..f911443 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -6,14 +6,26 @@ */ #include "ec.h" +#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <delay.h> #include <ec/compal/ene932/ec.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) + +enum sleep_states { + S0 = 0, + S1 = 1, + S3 = 3, + S4 = 4, + S5 = 5, +}; + enum ec_smi_event { EC_SMI_EVENT_IDLE = 0x80, + EC_SMI_BATTERY_LOW = 0xb3, }; /* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ @@ -37,12 +49,18 @@ static uint8_t ec_get_smi_event(void) static void ec_process_smi(uint8_t src) { - /* - * Stub: We aren't processing any events yet, but reading the SMI source - * satisfies the EC in terms of responding to the event. + /* Reading the SMI source satisfies the EC in terms of responding to + * the event, regardless of whether we take an action or not. */ - printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src); + switch (src) { + case EC_SMI_BATTERY_LOW: + printk(BIOS_DEBUG, "Battery low. Shutting down\n"); + outl(ACPI_PM1_CNT_SLEEP(S5), ACPI_PM1_CNT_BLK); + break; + default: + printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src); + } } static void handle_ec_smi(void)

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Patch set updated for coreboot: 1228cc3 southbridge/hudson: Compile refactored SMI setup utilities in SMM
by Alexandru Gagniuc 18 Apr '14

18 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/170 -gerrit commit 1228cc367b3e46ce945fdf2b1d01794701861366 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Apr 17 23:33:50 2014 -0500 southbridge/hudson: Compile refactored SMI setup utilities in SMM Refactor hudson_enable_gevent_smi() to allow configuring the interrupt mode and trigger level. Move the utilities which are useful in SMM to a separate file that is included in both ramstage and SMM. This is useful form SMI handlers which need to enable or disable GEVENT SMIs on-the-fly. A follow-up patch makes use of this infrastructure. Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +- src/southbridge/amd/agesa/hudson/smi.c | 43 ---------------- src/southbridge/amd/agesa/hudson/smi.h | 20 +++++--- src/southbridge/amd/agesa/hudson/smi_util.c | 67 +++++++++++++++++++++++++ 5 files changed, 83 insertions(+), 53 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index 756b443..ccabaf2 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -41,7 +41,7 @@ static void mainboard_enable(device_t dev) pavilion_m6_1035dx_ec_init(); - hudson_enable_gevent_smi(EC_SMI_GEVENT); + hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); hudson_enable_smi_generation(); /* diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b92e850..398ca90 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -22,8 +22,8 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c romstage-y += imc.c ramstage-y += imc.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 168f2ac..1d58afe 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -10,8 +10,6 @@ #include <console/console.h> #include <cpu/cpu.h> -#define HUDSON_SMI_ACPI_COMMAND 75 - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); @@ -25,44 +23,3 @@ void hudson_enable_smi_generation(void) reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); } - -static void enable_smi(uint8_t smi_num) -{ - uint8_t reg32_offset, bit_offset; - uint32_t reg32; - - /* SMI sources range from [0:149] */ - if (smi_num > 149) { - printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); - return; - } - - /* 16 sources per register, 2 bits per source; registers are 4 bytes */ - reg32_offset = (smi_num / 16) * 4; - bit_offset = (smi_num % 16) * 2; - - reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); - reg32 &= ~(3 << (bit_offset)); - reg32 |= (SMI_SRC_MODE_SMI << (bit_offset)); - smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); - -} - -/** Enable generation of SMIs for given GPE */ -void hudson_enable_gevent_smi(uint8_t gevent) -{ - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - enable_smi(gevent); -} - -/** Enable SMIs on writes to ACPI SMI command port */ -void hudson_enable_acpi_cmd_smi(void) -{ - enable_smi(HUDSON_SMI_ACPI_COMMAND); -} diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 7932228..f6468ce 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -22,11 +22,16 @@ #define SMI_REG_CONTROL0 0xa0 -enum smi_src_mode { - SMI_SRC_MODE_DISABLE = 0, - SMI_SRC_MODE_SMI = 1, - SMI_SRC_MODE_NMI = 2, - SMI_SRC_MODE_IRQ13 = 3, +enum smi_mode { + SMI_MODE_DISABLE = 0, + SMI_MODE_SMI = 1, + SMI_MODE_NMI = 2, + SMI_MODE_IRQ13 = 3, +}; + +enum smi_lvl { + SMI_LVL_LOW = 0, + SMI_LVL_HIGH = 1, }; static inline uint32_t smi_read32(uint8_t offset) @@ -49,10 +54,11 @@ static inline void smi_write16(uint8_t offset, uint16_t value) write16(SMI_BASE + offset, value); } +void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void hudson_enable_acpi_cmd_smi(void); + #ifndef __SMM__ void hudson_enable_smi_generation(void); -void hudson_enable_gevent_smi(uint8_t gevent); -void hudson_enable_acpi_cmd_smi(void); #endif #endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c new file mode 100644 index 0000000..01ce3f7 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -0,0 +1,67 @@ +/* + * SMM utilities used in both SMM and normal mode + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "smi.h" + +#include <console/console.h> + +#define HUDSON_SMI_ACPI_COMMAND 75 + +static void configure_smi(uint8_t smi_num, uint8_t mode) +{ + uint8_t reg32_offset, bit_offset; + uint32_t reg32; + + /* SMI sources range from [0:149] */ + if (smi_num > 149) { + printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); + return; + } + + /* 16 sources per register, 2 bits per source; registers are 4 bytes */ + reg32_offset = (smi_num / 16) * 4; + bit_offset = (smi_num % 16) * 2; + + reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); + reg32 &= ~(3 << (bit_offset)); + reg32 |= (mode << (bit_offset)); + smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); + +} + +/** + * Configure generation of interrupts for given GEVENT pin + * + * @param gevent The GEVENT pin number. Valid values are 0 thru 23 + * @param mode The type of event this pin should generate. Note that only + * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. + * @param level SMI_LVL_LOW or SMI_LVL_HIGH + */ +void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +{ + uint32_t reg32; + /* GEVENT pins range from [0:23] */ + if (gevent > 23) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, mode); + + /* And set set the trigger level */ + reg32 = smi_read32(SMI_REG_SMITRIG0); + reg32 &= ~(1 << gevent); + reg32 |= (level & 0x1) << gevent; + smi_write32(SMI_REG_SMITRIG0, reg32); +} + +/** Enable SMIs on writes to ACPI SMI command port */ +void hudson_enable_acpi_cmd_smi(void) +{ + configure_smi(HUDSON_SMI_ACPI_COMMAND, SMI_MODE_SMI); +}

1 0

New patch to review for coreboot: bc9814a cbfstool: fix an error in the use of makemagic.
by Ronald G. Minnich 18 Apr '14

18 Apr '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5544 -gerrit commit bc9814aae61351f8baa1de28cf29ce21f8854849 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Fri Apr 18 09:40:12 2014 -0700 cbfstool: fix an error in the use of makemagic. This fixes an error in the creation of the BSS payload constant. Change-Id: If55021a7bf3fc3399e2de0adaa457d0c08ff7352 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- util/cbfstool/cbfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index a561b2b..1ce615a 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -73,7 +73,7 @@ struct cbfs_stage { #define PAYLOAD_SEGMENT_CODE makemagic('C', 'O', 'D', 'E') #define PAYLOAD_SEGMENT_DATA makemagic('D', 'A', 'T', 'A') -#define PAYLOAD_SEGMENT_BSS makemagic(' ', 'B', 'S', 'S') +#define PAYLOAD_SEGMENT_BSS makemagic('B', 'S', 'S', ' ') #define PAYLOAD_SEGMENT_PARAMS makemagic('P', 'A', 'R', 'A') #define PAYLOAD_SEGMENT_ENTRY makemagic('E', 'N', 'T', 'R')

1 0

Patch set updated for coreboot: bd5f3d3 Drop drivers/generic/debug
by Kyösti Mälkki 18 Apr '14

18 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4554 -gerrit commit bd5f3d338604e8f93a0b947a3ec5c94af4bae25e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 13:13:17 2013 +0200 Drop drivers/generic/debug Not very popular nor useful nowadays. Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- documentation/Kconfig.tex | 16 -- src/drivers/generic/Kconfig | 1 - src/drivers/generic/Makefile.inc | 1 - src/drivers/generic/debug/Kconfig | 2 - src/drivers/generic/debug/Makefile.inc | 1 - src/drivers/generic/debug/debug_dev.c | 289 --------------------- src/mainboard/amd/bimini_fam10/devicetree.cb | 14 - src/mainboard/amd/mahogany_fam10/devicetree.cb | 14 - src/mainboard/amd/serengeti_cheetah/devicetree.cb | 11 - .../amd/serengeti_cheetah_fam10/devicetree.cb | 14 - src/mainboard/amd/tilapia_fam10/devicetree.cb | 13 - src/mainboard/broadcom/blast/devicetree.cb | 11 - src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb | 12 - src/mainboard/gigabyte/m57sli/devicetree.cb | 12 - src/mainboard/iwill/dk8_htx/devicetree.cb | 11 - src/mainboard/msi/ms7260/devicetree.cb | 13 - src/mainboard/msi/ms9185/devicetree.cb | 11 - src/mainboard/msi/ms9282/devicetree.cb | 8 - src/mainboard/msi/ms9652_fam10/devicetree.cb | 12 - src/mainboard/nvidia/l1_2pvv/devicetree.cb | 12 - src/mainboard/supermicro/h8dme/devicetree.cb | 12 - src/mainboard/supermicro/h8dmr/devicetree.cb | 12 - src/mainboard/supermicro/h8dmr_fam10/devicetree.cb | 12 - src/mainboard/supermicro/h8qme_fam10/devicetree.cb | 12 - src/mainboard/supermicro/h8scm_fam10/devicetree.cb | 14 - src/mainboard/supermicro/x6dhe_g/Kconfig | 1 - src/mainboard/supermicro/x6dhe_g/devicetree.cb | 6 - src/mainboard/supermicro/x6dhe_g2/Kconfig | 1 - src/mainboard/supermicro/x6dhe_g2/devicetree.cb | 6 - src/mainboard/tyan/s2885/devicetree.cb | 9 - src/mainboard/tyan/s2891/devicetree.cb | 11 - src/mainboard/tyan/s2892/devicetree.cb | 8 - src/mainboard/tyan/s2895/devicetree.cb | 10 - src/mainboard/tyan/s2912/devicetree.cb | 12 - src/mainboard/tyan/s2912_fam10/devicetree.cb | 12 - src/mainboard/tyan/s4882/devicetree.cb | 10 - src/mainboard/winent/mb6047/devicetree.cb | 11 - 37 files changed, 637 deletions(-) diff --git a/documentation/Kconfig.tex b/documentation/Kconfig.tex index 6e59a7c..2b2bf7f 100644 --- a/documentation/Kconfig.tex +++ b/documentation/Kconfig.tex @@ -337,22 +337,6 @@ That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much he \end{verbatim} -\begin{verbatim} - end # domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - -end -\end{verbatim} -This is a trick used to debug by creating entries in the device tree. \subsection{cpu socket} The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only diff --git a/src/drivers/generic/Kconfig b/src/drivers/generic/Kconfig index 597a186..3317fd1 100644 --- a/src/drivers/generic/Kconfig +++ b/src/drivers/generic/Kconfig @@ -1,3 +1,2 @@ -source src/drivers/generic/debug/Kconfig source src/drivers/generic/generic/Kconfig source src/drivers/generic/ioapic/Kconfig diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc index 802aac0..a099a31 100644 --- a/src/drivers/generic/Makefile.inc +++ b/src/drivers/generic/Makefile.inc @@ -1,3 +1,2 @@ -subdirs-y += debug subdirs-y += generic subdirs-y += ioapic diff --git a/src/drivers/generic/debug/Kconfig b/src/drivers/generic/debug/Kconfig deleted file mode 100644 index 608136a..0000000 --- a/src/drivers/generic/debug/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_GENERIC_DEBUG - bool diff --git a/src/drivers/generic/debug/Makefile.inc b/src/drivers/generic/debug/Makefile.inc deleted file mode 100644 index a6a3bd2..0000000 --- a/src/drivers/generic/debug/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_DEBUG) += debug_dev.c diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c deleted file mode 100644 index b523ca7..0000000 --- a/src/drivers/generic/debug/debug_dev.c +++ /dev/null @@ -1,289 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> -#include <reset.h> -#include <delay.h> - -static void print_pci_regs(struct device *dev) -{ - uint8_t byte; - int i; - - for(i=0;i<256;i++) { - byte = pci_read_config8(dev, i); - - if((i & 0xf)==0) printk(BIOS_DEBUG, "\n%02x:",i); - printk(BIOS_DEBUG, " %02x",byte); - } - printk(BIOS_DEBUG, "\n"); -} - -static void print_mem(void) -{ - unsigned int i; - unsigned int start = 0xfffff000; - for(i=start;i<0xffffffff;i++) { - if((i & 0xf)==0) printk(BIOS_DEBUG, "\n %08x:",i); - printk(BIOS_DEBUG, " %02x",(unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, " %02x\n",(unsigned char)*((unsigned char *)i)); - - } -static void print_pci_regs_all(void) -{ - struct device *dev; - unsigned bus, device, function; - - for(bus=0; bus<256; bus++) { - for(device=0; device<=0x1f; device++) { - for (function=0; function<=7; function++){ - unsigned devfn; - devfn = PCI_DEVFN(device, function); - dev = dev_find_slot(bus, devfn); - if(!dev) { - continue; - } - if(!dev->enabled) { - continue; - } - printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", - bus, device, function, dev_path(dev)); - print_pci_regs(dev); - } - } - } -} - -static void print_cpuid(void) -{ - msr_t msr; - unsigned index; - unsigned eax, ebx, ecx, edx; - index = 0x80000007; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n", - index, eax, ebx, ecx, edx); - if (edx & (3 << 1)) { - index = 0xC0010042; - printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index); - msr = rdmsr(index); - printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x\n", - index, msr.hi, msr.lo); - } - -} -static void print_smbus_regs(struct device *dev) -{ - int j; - printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link_num); - printk(BIOS_DEBUG, "%s", dev_path(dev)); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(dev, j); - if (status < 0) { - // printk(BIOS_DEBUG, "bad device status= %08x\n", status); - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); -} - -static void print_smbus_regs_all(struct device *dev) -{ - struct device *child; - struct bus *link; - if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) - { - // Here don't need to call smbus_set_link, because we scan it from top to down - if( dev->bus->dev->path.type == DEVICE_PATH_I2C) { // it's under i2c MUX so set mux at first - if(ops_smbus_bus(get_pbus_smbus(dev->bus->dev))) { - if(dev->bus->dev->ops && dev->bus->dev->ops->set_link) - dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link_num); - } - } - - if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev); - } - - for(link = dev->link_list; link; link = link->next) { - for (child = link->children; child; child = child->sibling) { - print_smbus_regs_all(child); - } - } -} -static void print_msr_dualcore(void) -{ - msr_t msr; - unsigned index; - unsigned eax, ebx, ecx, edx; - index = 0x80000008; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n", - index, eax, ebx, ecx, edx); - - printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); - - index = 0xc001001f; - printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index); - msr = rdmsr(index); - printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x bit 54 is %d\n", - index, msr.hi, msr.lo, (msr.hi>> (54-32)) & 1); -#if 0 - msr.hi |= (1<<(54-32)); - wrmsr(index, msr); - - msr = rdmsr(index); - printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x\n", - index, msr.hi, msr.lo); -#endif - -} - -static void print_cache_size(void) -{ - unsigned index; - unsigned int n, eax, ebx, ecx, edx; - - index = 0x80000000; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - n = eax; - - if (n >= 0x80000005) { - index = 0x80000005; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", - edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); - } - - if (n >= 0x80000006) { - index = 0x80000006; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "CPU: L2 Cache: %dK (%d bytes/line)\n", - ecx >> 16, ecx & 0xFF); - } - -} - -struct tsc_struct { - unsigned lo; - unsigned hi; -}; -typedef struct tsc_struct tsc_t; - -static tsc_t rdtsc(void) -{ - tsc_t res; - asm volatile( - "rdtsc" - : "=a" (res.lo), "=d"(res.hi) /* outputs */ - ); - return res; -} - -static void print_tsc(void) { - - tsc_t tsc; - tsc = rdtsc(); - printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n", - tsc.hi, tsc.lo); - udelay(1); - tsc = rdtsc(); - printk(BIOS_DEBUG, "tsc: 0x%08x%08x after udelay(1) \n", - tsc.hi, tsc.lo); - -} - -static void debug_init(device_t dev) -{ - device_t parent; - - if (!dev->enabled) - return; - switch(dev->path.pnp.device) { - case 0: - parent = dev->bus->dev; - printk(BIOS_DEBUG, "DEBUG: %s : %s\n", dev_path(parent), dev_name(parent)); - break; - - case 1: - print_pci_regs_all(); - break; - case 2: - print_mem(); - break; - case 3: - print_cpuid(); - break; - case 4: - print_smbus_regs_all(&dev_root); - break; - case 5: - print_msr_dualcore(); - break; - case 6: - print_cache_size(); - break; - case 7: - print_tsc(); - break; - case 8: - hard_reset(); - break; - } -} - -static void debug_noop(device_t dummy) -{ -} - -static struct device_operations debug_operations = { - .read_resources = debug_noop, - .set_resources = debug_noop, - .enable_resources = debug_noop, - .init = debug_init, -}; - -static void enable_dev(struct device *dev) -{ - dev->ops = &debug_operations; -} - -struct chip_operations drivers_generic_debug_ops = { - CHIP_NAME("Debug device") - .enable_dev = enable_dev, -}; diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index 25676f0..0bcc9c1 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -92,18 +92,4 @@ chip northbridge/amd/amdfam10/root_complex # end # end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end - end diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index 4fd77b7..5000b0c 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -126,18 +126,4 @@ chip northbridge/amd/amdfam10/root_complex # end # end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end - end diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index 1fea190..28b7e01 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -144,17 +144,6 @@ chip northbridge/amd/amdk8/root_complex end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - end diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index 972632b..8b5d817 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -134,20 +134,6 @@ chip northbridge/amd/amdfam10/root_complex # end # end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end - end diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 9315440..77fd875 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -127,17 +127,4 @@ chip northbridge/amd/amdfam10/root_complex # end # end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end end diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index b1486a6..326071b 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -119,16 +119,5 @@ chip northbridge/amd/amdk8/root_complex end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - end diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb index c2aecad..33b8505 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb +++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb @@ -89,16 +89,4 @@ chip northbridge/amd/amdk8/root_complex end # PCI domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end end #root_complex diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb index 5902932..efbf76e 100644 --- a/src/mainboard/gigabyte/m57sli/devicetree.cb +++ b/src/mainboard/gigabyte/m57sli/devicetree.cb @@ -151,16 +151,4 @@ device domain 0 on # PCI domain device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end end diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index 544390d..50d214b 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -114,17 +114,6 @@ chip northbridge/amd/amdk8/root_complex end end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - end diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb index b35bb58..717ad00 100644 --- a/src/mainboard/msi/ms7260/devicetree.cb +++ b/src/mainboard/msi/ms7260/devicetree.cb @@ -140,17 +140,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # TODO - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end end diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb index 75822ea..ee0d891 100644 --- a/src/mainboard/msi/ms9185/devicetree.cb +++ b/src/mainboard/msi/ms9185/devicetree.cb @@ -82,17 +82,6 @@ chip northbridge/amd/amdk8/root_complex device pci 18.3 on end end # amdk8 end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end - end diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb index f61d6a3..8210322 100644 --- a/src/mainboard/msi/ms9282/devicetree.cb +++ b/src/mainboard/msi/ms9282/devicetree.cb @@ -179,12 +179,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end - # device pnp 0.1 off end - # device pnp 0.2 off end - # device pnp 0.3 off end - # device pnp 0.4 off end - # device pnp 0.5 on end - # end end diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index 89b6a1e..a6d5206 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -166,16 +166,4 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end end diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb index 363d1a8..5709db7 100644 --- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb +++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb @@ -177,16 +177,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end end diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 9efbaf7..754e316 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -123,16 +123,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end end diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index 51ad94f..b363674 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -143,16 +143,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end end diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index c8a8bc5..9e52d07 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -149,16 +149,4 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 19.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end end diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 93a38d6..6956b45 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -112,16 +112,4 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 19.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 on end # io - # end end diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index ba7eb2a..9dda5d8 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -120,20 +120,6 @@ chip northbridge/amd/amdfam10/root_complex # end # end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end - end diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig index 03bb0a8..ab8d00b 100644 --- a/src/mainboard/supermicro/x6dhe_g/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 - select DRIVERS_GENERIC_DEBUG config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb index 01c2837..322860b 100644 --- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb @@ -1,10 +1,4 @@ chip northbridge/intel/e7520 # MCH - chip drivers/generic/debug # DEBUGGING - device pnp 00.0 on end - device pnp 00.1 off end - device pnp 00.2 off end - device pnp 00.3 off end - end device domain 0 on subsystemid 0x15d9 0x6080 inherit chip southbridge/intel/esb6300 # ESB6300 diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig index 397087c..b4630fe 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 select USE_WATCHDOG_ON_BOOT - select DRIVERS_GENERIC_DEBUG config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index c143ced..984814e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -1,10 +1,4 @@ chip northbridge/intel/e7520 # MCH - chip drivers/generic/debug # DEBUGGING - device pnp 00.0 off end - device pnp 00.1 off end - device pnp 00.2 off end - device pnp 00.3 off end - end device domain 0 on subsystemid 0x15d9 0x6080 inherit chip southbridge/intel/i82801ex # ICH5R diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb index acc5085..7191e52 100644 --- a/src/mainboard/tyan/s2885/devicetree.cb +++ b/src/mainboard/tyan/s2885/devicetree.cb @@ -119,14 +119,5 @@ chip northbridge/amd/amdk8/root_complex end end #domain - -# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end -# device pnp 0.4 off end -# device pnp 0.5 on end -# end end diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb index 3d8c65e..8442ec8 100644 --- a/src/mainboard/tyan/s2891/devicetree.cb +++ b/src/mainboard/tyan/s2891/devicetree.cb @@ -134,15 +134,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 off end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 off end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 on end # hard_reset - # end end diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb index af29be1..3edc156 100644 --- a/src/mainboard/tyan/s2892/devicetree.cb +++ b/src/mainboard/tyan/s2892/devicetree.cb @@ -137,12 +137,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end - # device pnp 0.1 off end - # device pnp 0.2 off end - # device pnp 0.3 off end - # device pnp 0.4 off end - # device pnp 0.5 on end - # end end diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb index f830505..4250160 100644 --- a/src/mainboard/tyan/s2895/devicetree.cb +++ b/src/mainboard/tyan/s2895/devicetree.cb @@ -150,14 +150,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 19.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 off end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # end end diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb index 57815de..42f764a 100644 --- a/src/mainboard/tyan/s2912/devicetree.cb +++ b/src/mainboard/tyan/s2912/devicetree.cb @@ -135,16 +135,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index 0a5475f..485c7e0 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -138,16 +138,4 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.4 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 on end # pci_regs_all - # device pnp 0.2 on end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 on end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 off end # io - # device pnp 0.9 off end # io - # end end diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index 151fbc4..44da2c2 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -192,15 +192,5 @@ chip northbridge/amd/amdk8/root_complex end end -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 on end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 on end # dual core msr -# device pnp 0.6 on end # cache size -# device pnp 0.7 on end # tsc -# end end diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 09a062e..81f5aae 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -117,15 +117,4 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.3 on end end end - # chip drivers/generic/debug - # device pnp 0.0 off end # chip name - # device pnp 0.1 off end # pci_regs_all - # device pnp 0.2 off end # mem - # device pnp 0.3 off end # cpuid - # device pnp 0.4 off end # smbus_regs_all - # device pnp 0.5 off end # dual core msr - # device pnp 0.6 off end # cache size - # device pnp 0.7 off end # tsc - # device pnp 0.8 on end # hard_reset - # end end

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New patch to review for coreboot: c14e1ec vendorcode/amd/agesa/*/AGESA.h: Correct typo in *b*e
by Paul Menzel 18 Apr '14

18 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5543 -gerrit commit c14e1ec6aa90e1dad67e41394a608ac1472f4b27 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Mar 15 10:47:50 2013 +0100 vendorcode/amd/agesa/*/AGESA.h: Correct typo in *b*e The typo is not present anymore in Family 16h (Kabini), so fix it for the older families (Family 10h, 12h, 14h, 15h, 15h Trinity) too using the command below. $ git grep -l ' ne ' src/vendorcode/amd/agesa | xargs sed -i 's/ ne / be /g' Change-Id: I9cb419251eeec79925f48a5832fac339d40f01d1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/AGESA.h | 2 +- src/vendorcode/amd/agesa/f12/AGESA.h | 2 +- src/vendorcode/amd/agesa/f14/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15/AGESA.h | 2 +- src/vendorcode/amd/agesa/f15tn/AGESA.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index e6f5cfb..d111ae4 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -764,7 +764,7 @@ typedef enum { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f12/AGESA.h b/src/vendorcode/amd/agesa/f12/AGESA.h index 9f61807..a240481 100644 --- a/src/vendorcode/amd/agesa/f12/AGESA.h +++ b/src/vendorcode/amd/agesa/f12/AGESA.h @@ -1022,7 +1022,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 2a9bed1..4237f86 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -877,7 +877,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h index 6b0171b..8b77fd8 100644 --- a/src/vendorcode/amd/agesa/f15/AGESA.h +++ b/src/vendorcode/amd/agesa/f15/AGESA.h @@ -1145,7 +1145,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index a709274..1392810 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1244,7 +1244,7 @@ typedef struct { /// GNB configuration info typedef struct { IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. - * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST + * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST * Example of topology definition for single socket system: * @code * PCIe_PORT_DESCRIPTOR PortList [] = {

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Patch set updated for coreboot: d76d5e5 util/xcompile/xcompile: Remove `-Wno-unused-but-set-variable` from `CFLAGS`
by Paul Menzel 18 Apr '14

18 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3981 -gerrit commit d76d5e543f4455d96e84605dd2648e6135260a1e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 20 00:11:34 2013 +0200 util/xcompile/xcompile: Remove `-Wno-unused-but-set-variable` from `CFLAGS` Do not disable warnings about unused but set variables to further improve the code quality. Change-Id: I25fa29ac42c9d09596d03f11fb01f31635a62a11 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/xcompile/xcompile | 5 ----- 1 file changed, 5 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index df7d558..bfb6da1 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -89,11 +89,6 @@ testas() { detect_special_flags() { local architecture="$1" - # GCC 4.6 is much more picky about unused variables. - # Turn off it's warnings for now: - testcc "$CC" "$CFLAGS -Wno-unused-but-set-variable " && - CFLAGS="$CFLAGS -Wno-unused-but-set-variable " - # Use bfd linker instead of gold if available: testcc "$CC" "$CFLAGS -fuse-ld=bfd" && CFLAGS="$CFLAGS -fuse-ld=bfd" && LINKER_SUFFIX='.bfd'

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