Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5539
-gerrit
commit d9b60fce2c9afeeaacefd4e9328c809a6763571b
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
Following boards use cimx/sb700:
amd/dinar
supermicro/h8qgi
supermicro/h8scm
tyan/s8226
Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).
Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.
I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.
Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/dinar/Kconfig | 8 --------
src/mainboard/supermicro/h8qgi/Kconfig | 4 ----
src/mainboard/supermicro/h8scm/Kconfig | 4 ----
src/mainboard/tyan/s8226/Kconfig | 4 ----
src/southbridge/amd/cimx/sb700/late.c | 11 +++--------
5 files changed, 3 insertions(+), 28 deletions(-)
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig
index b5434b4..6768a57 100644
--- a/src/mainboard/amd/dinar/Kconfig
+++ b/src/mainboard/amd/dinar/Kconfig
@@ -42,10 +42,6 @@ config MAINBOARD_DIR
string
default amd/dinar
-config APIC_ID_OFFSET
- hex
- default 0x0
-
config MAINBOARD_PART_NUMBER
string
default "Dinar"
@@ -58,10 +54,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 16
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index 6371d9e..2ff782a 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -54,10 +54,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 16
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig
index 86395e4..7260f99 100644
--- a/src/mainboard/supermicro/h8scm/Kconfig
+++ b/src/mainboard/supermicro/h8scm/Kconfig
@@ -53,10 +53,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 16
-
config CPU_ADDR_BITS
int
default 36 # TODO: Set it conservatively to match both fam10 & 15
diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig
index 68ce152..e8d2f88 100644
--- a/src/mainboard/tyan/s8226/Kconfig
+++ b/src/mainboard/tyan/s8226/Kconfig
@@ -54,10 +54,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index b03f13a..967eb34 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -218,21 +218,16 @@ static void sb700_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
{
-#if 1
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
clear_ioapic(ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
-#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
- /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS));
-#elif (CONFIG_APIC_ID_OFFSET > 0)
- /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+#if (CONFIG_MAX_CPUS >= 16)
setup_ioapic(ioapic_base, 0);
#else
-#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
-#endif
+ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+ setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
#endif
}
break;
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5539
-gerrit
commit cf2e03cf86a04cc1aa2e38175e4abdb995e70b70
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
Following boards use cimx/sb700:
amd/dinar
supermicro/h8qgi
supermicro/h8scm
tyan/s8226
Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).
Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.
I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.
Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/amd/dinar/Kconfig | 8 --------
src/mainboard/supermicro/h8qgi/Kconfig | 4 ----
src/mainboard/supermicro/h8scm/Kconfig | 4 ----
src/mainboard/tyan/s8226/Kconfig | 4 ----
src/southbridge/amd/cimx/sb700/late.c | 14 ++++----------
5 files changed, 4 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig
index b5434b4..6768a57 100644
--- a/src/mainboard/amd/dinar/Kconfig
+++ b/src/mainboard/amd/dinar/Kconfig
@@ -42,10 +42,6 @@ config MAINBOARD_DIR
string
default amd/dinar
-config APIC_ID_OFFSET
- hex
- default 0x0
-
config MAINBOARD_PART_NUMBER
string
default "Dinar"
@@ -58,10 +54,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 16
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index 6371d9e..2ff782a 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -54,10 +54,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 16
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig
index 86395e4..7260f99 100644
--- a/src/mainboard/supermicro/h8scm/Kconfig
+++ b/src/mainboard/supermicro/h8scm/Kconfig
@@ -53,10 +53,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 16
-
config CPU_ADDR_BITS
int
default 36 # TODO: Set it conservatively to match both fam10 & 15
diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig
index 68ce152..e8d2f88 100644
--- a/src/mainboard/tyan/s8226/Kconfig
+++ b/src/mainboard/tyan/s8226/Kconfig
@@ -54,10 +54,6 @@ config MAX_CPUS
int
default 64
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index b03f13a..9248ac3 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -218,23 +218,17 @@ static void sb700_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
{
-#if 1
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
clear_ioapic(ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
-#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
- /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS));
-#elif (CONFIG_APIC_ID_OFFSET > 0)
- /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+#if (CONFIG_MAX_CPUS >= 16)
setup_ioapic(ioapic_base, 0);
#else
-#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
-#endif
-#endif
- }
+ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+ setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
+#endif }
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5527
-gerrit
commit 9a536213888b7f296af020da7512092c8a783d5c
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Apr 17 00:47:47 2014 -0500
hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
Intercept the low battery SMI from the EC, and shut down the system
immediately. The EC only sends this SMI when the OS did not enable
ACPI mode, so ACPI OSes are not affected by this.
On the other hand, payloads such as GRUB or SeaBIOS will experience
the shutdown. This behavior is helpful for protecting the battery, for
example, when the OS fails to boot and we are stuck in the payload.
The low battery SMI is triggered at 10% charge, at which point the risk
of cell degradation exists.
Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c
index bb9cc2e..7c1a602 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c
@@ -6,14 +6,18 @@
*/
#include "ec.h"
+#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <delay.h>
#include <ec/compal/ene932/ec.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
+#define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10)
+
enum ec_smi_event {
EC_SMI_EVENT_IDLE = 0x80,
+ EC_SMI_BATTERY_LOW = 0xb3,
};
/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
@@ -37,12 +41,18 @@ static uint8_t ec_get_smi_event(void)
static void ec_process_smi(uint8_t src)
{
- /*
- * Stub: We aren't processing any events yet, but reading the SMI source
- * satisfies the EC in terms of responding to the event.
+ /* Reading the SMI source satisfies the EC in terms of responding to
+ * the event, regardless of whether we take an action or not.
*/
- printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src);
+ switch (src) {
+ case EC_SMI_BATTERY_LOW:
+ printk(BIOS_DEBUG, "Battery low. Shutting down\n");
+ outl(ACPI_PM1_CNT_SLEEP(5), ACPI_PM1_CNT_BLK);
+ break;
+ default:
+ printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src);
+ }
}
static void handle_ec_smi(void)
the following patch was just integrated into master:
commit 09fe3f83c545c162a4ac97e8c41198b8be915e2e
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Wed Apr 16 18:44:37 2014 -0500
hp/pavilion_m6_1035dx: Remove code which dumps ACPI tables
Dumping ACPI tables in canonical form has very little value, and is
of questionable use except when debugging acpigen. Remove the code
which dumps the tables.
Change-Id: Id13c88cee8674b13e5cf5b5ed32c26283e586fd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5526
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/5526 for details.
-gerrit