coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

1 participants
779 discussions

New patch to review for coreboot: c64008f uart8250io: Fix build with DEBUG_SMI
by Kyösti Mälkki 23 Apr '14

23 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5574 -gerrit commit c64008fca9c74fb3de7de854e01c88dfa8c5081d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 23 10:28:59 2014 +0300 uart8250io: Fix build with DEBUG_SMI Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/uart8250io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e1fb39b..4196350 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -134,7 +134,7 @@ void uart_tx_flush(void) uart8250_tx_flush(bases[0]); } -#ifndef __PRE_RAM__ +#if !defined(__PRE_RAM__) && !defined(__SMM__) void uart_fill_lb(void *data) { struct lb_serial serial;

1 0

New patch to review for coreboot: ab90d5e superio/fintek/*: Use correct headers for romstage
by Edward O'Callaghan 23 Apr '14

23 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5573 -gerrit commit ab90d5e9ce8445079862969995d5b70e00f01068 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 17:16:59 2014 +1000 superio/fintek/*: Use correct headers for romstage Many of these superio's were inheriting their headers from, presumably mainboard's includes. Change-Id: Ic06b47df9eb4d216a6d34ee16c3f0622284856bd Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71805f/early_serial.c | 1 + src/superio/fintek/f71805f/f71805f.h | 3 +++ src/superio/fintek/f71859/early_serial.c | 1 + src/superio/fintek/f71859/f71859.h | 3 +++ src/superio/fintek/f71863fg/early_serial.c | 1 + src/superio/fintek/f71863fg/f71863fg.h | 3 +++ src/superio/fintek/f71869ad/early_serial.c | 1 + src/superio/fintek/f71869ad/f71869ad.h | 3 +++ src/superio/fintek/f71872/early_serial.c | 1 + src/superio/fintek/f71872/f71872.h | 3 +++ src/superio/fintek/f71889/early_serial.c | 1 + src/superio/fintek/f71889/f71889.h | 3 +++ src/superio/fintek/f81865f/early_serial.c | 1 + src/superio/fintek/f81865f/f81865f.h | 3 +++ 14 files changed, 28 insertions(+) diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c index b823a43..6196eb7 100644 --- a/src/superio/fintek/f71805f/early_serial.c +++ b/src/superio/fintek/f71805f/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index a81319f..a23543a 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_FINTEK_F71805F_H #define SUPERIO_FINTEK_F71805F_H +#include <device/pnp.h> +#include <stdint.h> + /* * Datasheet: * - Name: F71805F/FG Super H/W Monitor + LPC IO diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c index cb0d3de..5f20095 100644 --- a/src/superio/fintek/f71859/early_serial.c +++ b/src/superio/fintek/f71859/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f71859.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index ab114a4..cd23a74 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_FINTEK_F71859_H #define SUPERIO_FINTEK_F71859_H +#include <device/pnp.h> +#include <stdint.h> + /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c index 251f298..b96b49a 100644 --- a/src/superio/fintek/f71863fg/early_serial.c +++ b/src/superio/fintek/f71863fg/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f71863fg.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index c29ddbe..c5db369 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_FINTEK_F71863FG_H #define SUPERIO_FINTEK_F71863FG_H +#include <device/pnp.h> +#include <stdint.h> + /* Logical Device Numbers (LDN). */ #define F71863FG_FDC 0x00 /* Floppy */ #define F71863FG_SP1 0x01 /* UART1 */ diff --git a/src/superio/fintek/f71869ad/early_serial.c b/src/superio/fintek/f71869ad/early_serial.c index 8518400..02fe9ef 100644 --- a/src/superio/fintek/f71869ad/early_serial.c +++ b/src/superio/fintek/f71869ad/early_serial.c @@ -33,6 +33,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f71869ad.h" /* diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index 43a4397..eea296f 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_FINTEK_F71869AD_H #define SUPERIO_FINTEK_F71869AD_H +#include <device/pnp.h> +#include <stdint.h> + /* Logical Device Numbers (LDN). */ #define F71869AD_FDC 0x00 /* Floppy */ #define F71869AD_SP1 0x01 /* UART1 */ diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c index bbfc264..9311b1a 100644 --- a/src/superio/fintek/f71872/early_serial.c +++ b/src/superio/fintek/f71872/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f71872.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index fb80762..78d7829 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_FINTEK_F71872_H #define SUPERIO_FINTEK_F71872_H +#include <device/pnp.h> +#include <stdint.h> + /* Logical Device Numbers (LDN). */ #define F71872_FDC 0x00 /* Floppy */ #define F71872_SP1 0x01 /* UART1 */ diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c index 5e11474..decbb1d 100644 --- a/src/superio/fintek/f71889/early_serial.c +++ b/src/superio/fintek/f71889/early_serial.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f71889.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 72148f4..0545f66 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -21,6 +21,9 @@ #ifndef SUPERIO_FINTEK_F71889_H #define SUPERIO_FINTEK_F71889_H +#include <device/pnp.h> +#include <stdint.h> + /* Logical Device Numbers (LDN). */ #define F71889_FDC 0x00 /* Floppy */ #define F71889_SP1 0x01 /* UART1 */ diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c index 29b5f9d..eec6b5f 100644 --- a/src/superio/fintek/f81865f/early_serial.c +++ b/src/superio/fintek/f81865f/early_serial.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/pnp.h> +#include <stdint.h> #include "f81865f.h" static void pnp_enter_conf_state(device_t dev) diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 99b7698..4a7f083 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -25,6 +25,9 @@ #ifndef SUPERIO_FINTEK_F81865_H #define SUPERIO_FINTEK_F81865_H +#include <device/pnp.h> +#include <stdint.h> + /* Logical Device Numbers (LDN). */ #define F81865F_FDC 0x00 /* Floppy */ #define F81865F_SP1 0x10 /* UART1 */

1 0

New patch to review for coreboot: 8a6403d superio/fintek/*: Fix header style
by Edward O'Callaghan 23 Apr '14

23 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5572 -gerrit commit 8a6403d4533e32804eb84270939da758eaa366c6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 17:01:45 2014 +1000 superio/fintek/*: Fix header style Remove some redundant includes. Fix repetitiveness in include guards and strip some misplaced tabs for whitespaces. Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71805f/f71805f.h | 18 +++++++++--------- src/superio/fintek/f71859/f71859.h | 6 +++--- src/superio/fintek/f71863fg/chip.h | 1 - src/superio/fintek/f71863fg/f71863fg.h | 20 ++++++++++---------- src/superio/fintek/f71869ad/chip.h | 1 - src/superio/fintek/f71869ad/f71869ad.h | 6 +++--- src/superio/fintek/f71872/f71872.h | 6 +++--- src/superio/fintek/f71889/chip.h | 1 - src/superio/fintek/f71889/f71889.h | 6 +++--- src/superio/fintek/f81865f/f81865f.h | 22 +++++++++++----------- 10 files changed, 42 insertions(+), 45 deletions(-) diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 6aae58f..a81319f 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71805F_F71805F_H -#define SUPERIO_FINTEK_F71805F_F71805F_H +#ifndef SUPERIO_FINTEK_F71805F_H +#define SUPERIO_FINTEK_F71805F_H /* * Datasheet: @@ -30,14 +30,14 @@ */ /* Logical Device Numbers (LDN). */ -#define F71805F_FDC 0x00 /* Floppy */ -#define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ +#define F71805F_FDC 0x00 /* Floppy */ +#define F71805F_SP1 0x01 /* UART1 */ +#define F71805F_SP2 0x02 /* UART2 */ #define F71805F_PP 0x03 /* Parallel port */ -#define F71805F_HWM 0x04 /* Hardware monitor */ -#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71805F_PME 0x0a /* Power Management Events (PME) */ +#define F71805F_HWM 0x04 /* Hardware monitor */ +#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71805F_PME 0x0a /* Power Management Events (PME) */ void f71805f_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71805F_F71805F_H */ +#endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index 580fa34..ab114a4 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -18,12 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71859_F71859_H -#define SUPERIO_FINTEK_F71859_F71859_H +#ifndef SUPERIO_FINTEK_F71859_H +#define SUPERIO_FINTEK_F71859_H /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ void f71859_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71859_F71859_H */ +#endif /* SUPERIO_FINTEK_F71859_H */ diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h index 4d2652e..a2c04d7 100644 --- a/src/superio/fintek/f71863fg/chip.h +++ b/src/superio/fintek/f71863fg/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71863FG_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71863fg_config { diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index 127a120..c29ddbe 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -18,21 +18,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71863FG_F71863FG_H -#define SUPERIO_FINTEK_F71863FG_F71863FG_H +#ifndef SUPERIO_FINTEK_F71863FG_H +#define SUPERIO_FINTEK_F71863FG_H /* Logical Device Numbers (LDN). */ #define F71863FG_FDC 0x00 /* Floppy */ #define F71863FG_SP1 0x01 /* UART1 */ -#define F71863FG_SP2 0x02 /* UART2 */ +#define F71863FG_SP2 0x02 /* UART2 */ #define F71863FG_PP 0x03 /* Parallel port */ -#define F71863FG_HWM 0x04 /* Hardware monitor */ -#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */ -#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71863FG_VID 0x07 /* VID */ -#define F71863FG_SPI 0x08 /* SPI */ -#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ +#define F71863FG_HWM 0x04 /* Hardware monitor */ +#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */ +#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71863FG_VID 0x07 /* VID */ +#define F71863FG_SPI 0x08 /* SPI */ +#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ void f71863fg_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71863FG_F71863FG_H */ +#endif /* SUPERIO_FINTEK_F71863FG_H */ diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..ea2ee6e 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index abc0260..43a4397 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71869AD_F71869AD_H -#define SUPERIO_FINTEK_F71869AD_F71869AD_H +#ifndef SUPERIO_FINTEK_F71869AD_H +#define SUPERIO_FINTEK_F71869AD_H /* Logical Device Numbers (LDN). */ #define F71869AD_FDC 0x00 /* Floppy */ @@ -34,4 +34,4 @@ void f71869ad_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71869AD_F71869AD_H */ +#endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index 577f8d1..fb80762 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71872_F71872_H -#define SUPERIO_FINTEK_F71872_F71872_H +#ifndef SUPERIO_FINTEK_F71872_H +#define SUPERIO_FINTEK_F71872_H /* Logical Device Numbers (LDN). */ #define F71872_FDC 0x00 /* Floppy */ @@ -34,4 +34,4 @@ void f71872_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71872_F71872_H */ +#endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h index 50312ad..e5a15d3 100644 --- a/src/superio/fintek/f71889/chip.h +++ b/src/superio/fintek/f71889/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71889_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71889_config { diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 6dc43b3..72148f4 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71889_F71889_H -#define SUPERIO_FINTEK_F71889_F71889_H +#ifndef SUPERIO_FINTEK_F71889_H +#define SUPERIO_FINTEK_F71889_H /* Logical Device Numbers (LDN). */ #define F71889_FDC 0x00 /* Floppy */ @@ -36,4 +36,4 @@ void f71889_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71889_F71889_H */ +#endif /* SUPERIO_FINTEK_F71889_H */ diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index ccf41af..99b7698 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -22,19 +22,19 @@ * Datasheet: * - Name: F81865F/F-I */ -#ifndef SUPERIO_FINTEK_F81865_F81865_H -#define SUPERIO_FINTEK_F81865_F81865_H +#ifndef SUPERIO_FINTEK_F81865_H +#define SUPERIO_FINTEK_F81865_H /* Logical Device Numbers (LDN). */ -#define F81865F_FDC 0x00 /* Floppy */ -#define F81865F_SP1 0x10 /* UART1 */ -#define F81865F_SP2 0x11 /* UART2 */ -#define F81865F_PP 0x03 /* Parallel Port */ -#define F81865F_HWM 0x04 /* Hardware Monitor */ -#define F81865F_KBC 0x05 /* Keyboard/Mouse */ -#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F81865F_PME 0x0a /* Power Management Events (PME) */ +#define F81865F_FDC 0x00 /* Floppy */ +#define F81865F_SP1 0x10 /* UART1 */ +#define F81865F_SP2 0x11 /* UART2 */ +#define F81865F_PP 0x03 /* Parallel Port */ +#define F81865F_HWM 0x04 /* Hardware Monitor */ +#define F81865F_KBC 0x05 /* Keyboard/Mouse */ +#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81865F_PME 0x0a /* Power Management Events (PME) */ void f81865f_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F81865_F81865_H */ +#endif /* SUPERIO_FINTEK_F81865_H */

1 0

New patch to review for coreboot: a196260 coreboot: Move redundant Makefile rules from arch to top level
by Furquan Shaikh 23 Apr '14

23 Apr '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5571 -gerrit commit a1962602551270d2d29afb40b4319f1158c2cf35 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 22 16:33:22 2014 -0700 coreboot: Move redundant Makefile rules from arch to top level Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others from arch level Makefile.inc to top level Makefile.inc Also, organize Makefile.inc at arch level into per-stage rules and variables Change-Id: I7dc5b2d31c959b55bb92d9c7811427c4dada1db5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 157 +++++++++++++++++ src/arch/armv7/Makefile.inc | 264 +++++++++++----------------- src/arch/x86/Makefile.inc | 407 +++++++++++++++----------------------------- 3 files changed, 389 insertions(+), 439 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 72f3951..3ad39c1 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -408,3 +408,160 @@ crossgcc-clean: clean-for-update tools: $(objutil)/kconfig/conf $(objutil)/cbfstool/cbfstool $(objutil)/cbfstool/rmodtool $(objutil)/nvramtool/nvramtool $(objutil)/romcc/romcc $(objutil)/sconfig/sconfig +######################################################################################################################################################################## +# Common recipes for all stages +######################################################################################################################################################################## + +$(objcbfs)/%.bin: $(objcbfs)/%.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -O binary $< $@ + +$(objcbfs)/%.elf: $(objcbfs)/%.debug + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cp $< $@.tmp + $(NM) -n $@.tmp | sort > $(basename $(a)).map + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp + mv $@.tmp $@ + +######################################################################################################################################################################## +# Build the final rom image +######################################################################################################################################################################## + +COREBOOT_ROM_DEPENDENCIES:= +ifeq ($(CONFIG_PAYLOAD_ELF),y) +COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) +endif +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) +COREBOOT_ROM_DEPENDENCIES+=seabios +endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) +COREBOOT_ROM_DEPENDENCIES+=filo +endif +ifeq ($(CONFIG_PAYLOAD_GRUB2),y) +COREBOOT_ROM_DEPENDENCIES+=grub2 +endif + +extract_nth=$(word $(1), $(subst |, ,$(2))) + +ifneq ($(CONFIG_UPDATE_IMAGE),y) +prebuild-files = \ + $(foreach file,$(cbfs-files), \ + $(CBFSTOOL) $@.tmp \ + add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \ + -f $(call extract_nth,1,$(file)) \ + -n $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file))) \ + $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) +prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) + +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) + $(CBFSTOOL) $@.tmp create -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ + -B $(objcbfs)/bootblock.bin -a 64 \ + $(COREBOOT_PRE1_OPTS) + $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) + mv $@.tmp $@ +else +.PHONY: $(obj)/coreboot.pre1 +$(obj)/coreboot.pre1: $(CBFSTOOL) + mv $(obj)/coreboot.rom $@ +endif + +ifeq ($(CONFIG_PAYLOAD_LINUX),y) +LINUX_ADDITIONAL_CONFIG:= +ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),) + LINUX_ADDITIONAL_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE) +endif +ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),) + LINUX_ADDITIONAL_CONFIG+=-I $(CONFIG_LINUX_INITRD) +endif +endif + +ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) +REFCODE_BLOB=$(obj)/refcode.rmod +$(REFCODE_BLOB): $(RMODTOOL) + $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ +endif + +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB) + @printf " CBFS $(subst $(obj)/,,$(@))\n" + cp $(obj)/coreboot.pre $@.tmp + $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG) +ifeq ($(CONFIG_PAYLOAD_NONE),y) + @printf " PAYLOAD none (as specified by user)\n" +endif +ifeq ($(CONFIG_PAYLOAD_ELF),y) + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) +endif +ifeq ($(CONFIG_PAYLOAD_LINUX),y) + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) +endif +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) + @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) + @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup +endif +endif +endif +ifeq ($(CONFIG_PAYLOAD_FILO),y) + @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) +endif +ifeq ($(CONFIG_PAYLOAD_GRUB2),y) + @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) +endif +ifeq ($(CONFIG_PAYLOAD_TIANOCORE),y) + @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) +endif +ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) + @printf " CONFIG $(DOTCONFIG)\n" + if [ -f $(DOTCONFIG) ]; then \ + echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ + sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ + $(CBFSTOOL) $@.tmp add -f $(obj)/config.tmp -n config -t raw; rm -f $(obj)/config.tmp ; fi +endif +ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) + $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) +endif +ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) + $(CBFSTOOL) $@.tmp add-stage -f $(REFCODE_BLOB) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG) +endif +ifeq ($(CONFIG_PXE_ROM),y) + $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw +endif +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) + @printf " UPDATE-FIT \n" + $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) +endif +endif + mv $@.tmp $@ + @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" + $(CBFSTOOL) $@ print + +cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg +bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) +bootsplash.jpg-type := bootsplash + +ifeq ($(CONFIG_ARCH_ARMV7),y) +ROMSTAGE_ELF := romstage.elf +endif +ifeq ($(CONFIG_ARCH_X86),y) +ROMSTAGE_ELF := romstage_xip.elf +endif + +$(obj)/coreboot.pre: $(objcbfs)/$(ROMSTAGE_ELF) $(obj)/coreboot.pre1 $(CBFSTOOL) + @printf " CBFS $(subst $(obj)/,,$(@))\n" + cp $(obj)/coreboot.pre1 $@.tmp + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/$(ROMSTAGE_ELF) \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ + $(COREBOOT_PRE_OPTS) + mv $@.tmp $@ diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 6395b0c..aa85cc6 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -22,91 +22,18 @@ ## ################################################################################ +################################################################################ # Take care of subdirectories +################################################################################ subdirs-y += boot/ subdirs-y += lib/ ################################################################################ -# Build the final rom image -COREBOOT_ROM_DEPENDENCIES:= -ifeq ($(CONFIG_PAYLOAD_ELF),y) -COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) -endif - -extract_nth=$(word $(1), $(subst |, ,$(2))) - -ifneq ($(CONFIG_UPDATE_IMAGE),y) -prebuild-files = \ - $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@.tmp \ - add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \ - -f $(call extract_nth,1,$(file)) \ - -n $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file))) \ - $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) -prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) - -# TODO Change -b to Kconfig variable. -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 \ - -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \ - -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ - -o $(CONFIG_CBFS_ROM_OFFSET) - @printf " CBFS $(subst $(obj)/,,$(@))\n" - $(CBFSTOOL) $@.tmp add-stage \ - -f $(objcbfs)/romstage.elf -b 0 \ - -n $(CONFIG_CBFS_PREFIX)/romstage -c none - $(prebuild-files) true - $(call add-cpu-microcode-to-cbfs,$@.tmp) - mv $@.tmp $@ -else -.PHONY: $(obj)/coreboot.pre -$(obj)/coreboot.pre: $(CBFSTOOL) - mv $(obj)/coreboot.rom $@ -endif - -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" - cp $(obj)/coreboot.pre $@.tmp - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG) -ifeq ($(CONFIG_PAYLOAD_NONE),y) - @printf " PAYLOAD none (as specified by user)\n" -endif -ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(DOTCONFIG)\n" - if [ -f $(DOTCONFIG) ]; then \ - echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ - sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ - $(CBFSTOOL) $@.tmp add -f $(obj)/config.tmp -n config -t raw; rm -f $(obj)/config.tmp ; fi -endif - mv $@.tmp $@ - @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" - $(CBFSTOOL) $@ print - -bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) -bootsplash.jpg-type := bootsplash - +# ARM specific options ################################################################################ -# armv7 specific tools -################################################################################ -# Common recipes for all stages - -$(objcbfs)/%.bin: $(objcbfs)/%.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ - -$(objcbfs)/%.elf: $(objcbfs)/%.debug - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cp $< $@.tmp - $(NM) -n $@.tmp | sort > $(basename $(a)).map - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp - mv $@.tmp $@ +COREBOOT_PRE1_OPTS = -m armv7 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) +COREBOOT_PRE_OPTS = -b 0 stages_c = $(src)/arch/armv7/stages.c stages_o = $(obj)/arch/armv7/stages.o @@ -115,26 +42,6 @@ $(stages_o): $(stages_c) $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I. $(INCLUDES) -c -o $@ $< -marm - -################################################################################ -# Build the ramstage (stage 2) - -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/armv7/ramstage.ld - @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld -else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $< -endif - -$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) - @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group -else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group -endif - CFLAGS += \ -ffixed-r8\ -march=armv7-a\ @@ -143,82 +50,16 @@ CFLAGS += \ -mthumb\ -mthumb-interwork -ldscripts = -ldscripts += $(src)/arch/armv7/romstage.ld - -#crt0s += $(src)/cpu/arm/fpu_enable.inc -# FIXME: CONFIG_NEON or something similar for ARM? -#ifeq ($(CONFIG_SSE),y) -#crt0s += $(src)/cpu/arm/sse_enable.inc -#endif - -crt0s += $(cpu_incs) -crt0s += $(cpu_incs-y) - -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" - $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ - -# Things that appear in every board -ramstage-y += exception.c -ramstage-y += exception_asm.S +################################################################################ +# Bootblock +################################################################################ bootblock-y += cache.c - -romstage-y += cache.c -romstage-y += div0.c - -ramstage-y += div0.c -#ramstage-y += interrupts.c -ramstage-y += cache.c -ramstage-y += mmu.c - -romstage-y += eabi_compat.c -ramstage-y += eabi_compat.c bootblock-y += eabi_compat.c - -ramstage-y += boot.c -ramstage-y += tables.c - -romstage-y += memset.S -ramstage-y += memset.S bootblock-y += memset.S -romstage-y += memcpy.S -ramstage-y += memcpy.S bootblock-y += memcpy.S -romstage-y += memmove.S -ramstage-y += memmove.S bootblock-y += memmove.S -romstage-srcs += $(objgenerated)/crt0.s -ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) -ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/irq_tables.c -endif -ifeq ($(CONFIG_BOARD_HAS_HARD_RESET),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c -endif -ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl -# make doesn't have arithmetic operators or greater-than comparisons -ifeq ($(subst 5,4,$(CONFIG_ACPI_SSDTX_NUM)),4) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt2.asl -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt3.asl -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt4.asl -endif -ifeq ($(CONFIG_ACPI_SSDTX_NUM),5) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl -endif -endif - -ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c -endif - -################################################################################ -# Build the bootblock - bootblock_lds = $(src)/arch/armv7/bootblock.lds bootblock_lds += $(chipset_bootblock_lds) @@ -262,6 +103,30 @@ else endif ################################################################################ +# Romstage +################################################################################ + +romstage-y += cache.c +romstage-y += div0.c +romstage-y += eabi_compat.c +romstage-y += memset.S +romstage-y += memcpy.S +romstage-y += memmove.S +romstage-srcs += $(objgenerated)/crt0.s + +ldscripts = +ldscripts += $(src)/arch/armv7/romstage.ld + + +#crt0s += $(src)/cpu/arm/fpu_enable.inc +# FIXME: CONFIG_NEON or something similar for ARM? +#ifeq ($(CONFIG_SSE),y) +#crt0s += $(src)/cpu/arm/sse_enable.inc +#endif + +crt0s += $(cpu_incs) +crt0s += $(cpu_incs-y) + # Build the romstage $(objcbfs)/romstage.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage.ld @@ -290,3 +155,68 @@ $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/b @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h + @printf " CC romstage.inc\n" + $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ + +################################################################################ +# Ramstage +################################################################################ + +# Things that appear in every board +ramstage-y += exception.c +ramstage-y += exception_asm.S +ramstage-y += div0.c +#ramstage-y += interrupts.c +ramstage-y += cache.c +ramstage-y += mmu.c +ramstage-y += eabi_compat.c +ramstage-y += boot.c +ramstage-y += tables.c +ramstage-y += memset.S +ramstage-y += memcpy.S +ramstage-y += memmove.S +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) + +# Build the ramstage (stage 2) + +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/armv7/ramstage.ld + @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld +else + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $< +endif + +$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) + @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group +else + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group +endif + +ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/irq_tables.c +endif +ifeq ($(CONFIG_BOARD_HAS_HARD_RESET),y) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c +endif +ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl +# make doesn't have arithmetic operators or greater-than comparisons +ifeq ($(subst 5,4,$(CONFIG_ACPI_SSDTX_NUM)),4) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt2.asl +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt3.asl +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt4.asl +endif +ifeq ($(CONFIG_ACPI_SSDTX_NUM),5) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl +endif +endif + +ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) +ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c +endif + diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index db8e500..7cd658e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -21,7 +21,9 @@ ## ################################################################################ +################################################################################ # Take care of subdirectories +################################################################################ subdirs-y += boot # subdirs-y += init subdirs-y += lib @@ -42,128 +44,6 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -################################################################################ -# Build the final rom image -COREBOOT_ROM_DEPENDENCIES:= -ifeq ($(CONFIG_PAYLOAD_ELF),y) -COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE) -endif -ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) -COREBOOT_ROM_DEPENDENCIES+=seabios -endif -ifeq ($(CONFIG_PAYLOAD_FILO),y) -COREBOOT_ROM_DEPENDENCIES+=filo -endif -ifeq ($(CONFIG_PAYLOAD_GRUB2),y) -COREBOOT_ROM_DEPENDENCIES+=grub2 -endif - -extract_nth=$(word $(1), $(subst |, ,$(2))) - -ifneq ($(CONFIG_UPDATE_IMAGE),y) -prebuild-files = \ - $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@.tmp \ - add$(if $(filter stage,$(call extract_nth,3,$(file))),-stage)$(if $(filter payload,$(call extract_nth,3,$(file))),-payload) \ - -f $(call extract_nth,1,$(file)) \ - -n $(call extract_nth,2,$(file)) $(if $(filter-out stage,$(call extract_nth,3,$(file))),-t $(call extract_nth,3,$(file))) \ - $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) -prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) - -$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) - $(CBFSTOOL) $@.tmp create -m x86 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 \ - -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) - $(prebuild-files) true - $(call add-cpu-microcode-to-cbfs,$@.tmp) - mv $@.tmp $@ -else -.PHONY: $(obj)/coreboot.pre1 -$(obj)/coreboot.pre1: $(CBFSTOOL) - mv $(obj)/coreboot.rom $@ -endif - -ifeq ($(CONFIG_PAYLOAD_LINUX),y) -LINUX_ADDITIONAL_CONFIG:= -ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),) - LINUX_ADDITIONAL_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE) -endif -ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),) - LINUX_ADDITIONAL_CONFIG+=-I $(CONFIG_LINUX_INITRD) -endif -endif - -ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) -REFCODE_BLOB=$(obj)/refcode.rmod -$(REFCODE_BLOB): $(RMODTOOL) - $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ -endif - -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB) - @printf " CBFS $(subst $(obj)/,,$(@))\n" - cp $(obj)/coreboot.pre $@.tmp - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG) -ifeq ($(CONFIG_PAYLOAD_NONE),y) - @printf " PAYLOAD none (as specified by user)\n" -endif -ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_PAYLOAD_LINUX),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) -endif -ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) - @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_PAYLOAD_FILO),y) - @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif - -ifeq ($(CONFIG_PAYLOAD_GRUB2),y) - @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif - -ifeq ($(CONFIG_PAYLOAD_TIANOCORE),y) - @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(DOTCONFIG)\n" - if [ -f $(DOTCONFIG) ]; then \ - echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ - sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ - $(CBFSTOOL) $@.tmp add -f $(obj)/config.tmp -n config -t raw; rm -f $(obj)/config.tmp ; fi -endif -ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) - $(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y) - $(CBFSTOOL) $@.tmp add-stage -f $(CONFIG_REFCODE_BLOB_FILE) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_PXE_ROM),y) - $(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw -endif -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -ifeq ($(CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD),y) - @printf " UPDATE-FIT \n" - $(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -endif -endif - mv $@.tmp $@ - @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" - $(CBFSTOOL) $@ print - stripped_vgabios_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_ID)) cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)) @@ -173,9 +53,8 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE)) mbi.bin-type := mbi -cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg -bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) -bootsplash.jpg-type := bootsplash +COREBOOT_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) +COREBOOT_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) ################################################################################ # i386 specific tools @@ -189,56 +68,76 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -################################################################################ -# Common recipes for all stages - -$(objcbfs)/%.bin: $(objcbfs)/%.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ - -$(objcbfs)/%.elf: $(objcbfs)/%.debug - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cp $< $@.tmp - $(NM) -n $@.tmp | sort > $(basename $(a)).map - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp - mv $@.tmp $@ ################################################################################ -# Build the ramstage (stage 2) - -ramstage-libs ?= - -ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) +# Bootblock +################################################################################ -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE))) +# Build the bootblock -# The rmodule_link defintion creates an elf file with .rmod extension. -$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod - cp $< $@ +bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb +bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds +bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds +bootblock_lds += $(src)/arch/x86/lib/id.lds +bootblock_lds += $(chipset_bootblock_lds) +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +bootblock_lds += $(src)/cpu/intel/fit/fit.lds +endif -else +bootblock_inc = $(src)/arch/x86/init/prologue.inc +bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc +bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc +bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc +bootblock_inc += $(src)/arch/x86/lib/id.inc +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +bootblock_inc += $(src)/cpu/intel/fit/fit.inc +endif +bootblock_inc += $(chipset_bootblock_inc) -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld - @printf " CC $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld -else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $< +ifeq ($(CONFIG_SSE),y) +bootblock_inc += $(src)/cpu/x86/sse_enable.inc endif +bootblock_inc += $(objgenerated)/bootblock.inc +bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S +bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ +ifeq ($(CONFIG_SSE),y) +bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ endif -$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) +$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ + +$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ + +$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + +$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + +$(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) + @printf " ROMCC $(subst $(obj)/,,$(@))\n" + $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $< > $(objgenerated)/bootblock.inc.d + $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@ + +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group + $(LD) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif ################################################################################ -# done +# Romstage +################################################################################ crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = @@ -287,8 +186,68 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/ mv $@.tmp $@ endif -# Things that appear in every board romstage-srcs += $(objgenerated)/crt0.s + +# Build the romstage + +romstage-libs ?= + +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) + @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld +else + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group +endif + $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ + echo "Forbidden global variables in romstage:"; \ + $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ + else true; fi + +$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) + @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld +else + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group +endif + +$(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp + printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp + mv $@.tmp $@ + +$(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(objcbfs)/base_xip.txt > $@.tmp + sed -e '/ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp + mv $@.tmp $@ + +$(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin + rm -f $@ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } + mv $@.tmp $@ + +$(objgenerated)/crt0.romstage.S: $$(crt0s) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ + +$(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + +$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + +################################################################################ +# Ramstage +################################################################################ + ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_MP_TABLE),y) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/mptable.c),) @@ -329,136 +288,40 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -################################################################################ -# Build the final rom image - -$(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) - @printf " CBFS $(subst $(obj)/,,$(@))\n" - cp $(obj)/coreboot.pre1 $@.tmp - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/romstage_xip.elf \ - -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ - -b $(shell cat $(objcbfs)/base_xip.txt) - mv $@.tmp $@ - -################################################################################ -# Build the bootblock - -bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb -bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds -bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds -bootblock_lds += $(src)/arch/x86/lib/id.lds -bootblock_lds += $(chipset_bootblock_lds) -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_lds += $(src)/cpu/intel/fit/fit.lds -endif - -bootblock_inc = $(src)/arch/x86/init/prologue.inc -bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc -bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc -bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc -bootblock_inc += $(src)/arch/x86/lib/id.inc -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_inc += $(src)/cpu/intel/fit/fit.inc -endif -bootblock_inc += $(chipset_bootblock_inc) +# Build the ramstage (stage 2) -ifeq ($(CONFIG_SSE),y) -bootblock_inc += $(src)/cpu/x86/sse_enable.inc -endif -bootblock_inc += $(objgenerated)/bootblock.inc -bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S +ramstage-libs ?= -bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ -ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ -endif +ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ +$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE))) -$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ +# The rmodule_link defintion creates an elf file with .rmod extension. +$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod + cp $< $@ -$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm +else -$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ - -$(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) - @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ - $< > $(objgenerated)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@ - -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $< endif -################################################################################ -# Build the romstage - -romstage-libs ?= - -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) - @printf " LINK $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld -else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif - $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ - echo "Forbidden global variables in romstage:"; \ - $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ - else true; fi -$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) - @printf " LINK $(subst $(obj)/,,$(@))\n" +$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif -$(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" - rm -f $@ - printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp - mv $@.tmp $@ - -$(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt - @printf " GEN $(subst $(obj)/,,$(@))\n" - rm -f $@ - sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(objcbfs)/base_xip.txt > $@.tmp - sed -e '/ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp - mv $@.tmp $@ - -$(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin - rm -f $@ - $(CBFSTOOL) $(obj)/coreboot.pre1 locate -T -f $(objcbfs)/romstage_null.bin -n $(CONFIG_CBFS_PREFIX)/romstage -P $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ - || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } - mv $@.tmp $@ - -$(objgenerated)/crt0.romstage.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ - -$(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm -$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ +################################################################################ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \

1 0

New patch to review for coreboot: 204e779 coreboot: Rename coreboot_ram stage to ramstage
by Furquan Shaikh 23 Apr '14

23 Apr '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5567 -gerrit commit 204e7791e5ede252c60dc452be5ed5dfd65b1370 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 22 10:41:05 2014 -0700 coreboot: Rename coreboot_ram stage to ramstage Patch to rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names(bootblock, romstage) and to allow any Makefile rule generalization. (Required for patches to be submitted later) Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile.inc | 2 +- src/Kconfig | 2 +- src/arch/armv7/Makefile.inc | 14 +-- src/arch/armv7/coreboot_ram.ld | 131 ------------------------- src/arch/armv7/ramstage.ld | 131 +++++++++++++++++++++++++ src/arch/armv7/romstage.ld | 2 +- src/arch/x86/Makefile.inc | 18 ++-- src/arch/x86/coreboot_ram.ld | 127 ------------------------ src/arch/x86/ramstage.ld | 127 ++++++++++++++++++++++++ src/cpu/amd/car/disable_cache_as_ram.c | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 2 +- src/cpu/amd/geode_lx/msrinit.c | 4 +- src/cpu/intel/fsp_model_206ax/cache_as_ram.inc | 2 +- src/cpu/intel/model_2065x/cache_as_ram.inc | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 2 +- src/cpu/x86/pae/pgtbl.c | 2 +- src/lib/loaders/load_and_run_ramstage.c | 2 +- src/lib/rmodule.ld | 2 +- src/lib/selfboot.c | 4 +- src/mainboard/cubietech/cubieboard/romstage.c | 2 +- src/mainboard/emulation/qemu-armv7/romstage.c | 2 +- src/mainboard/google/pit/romstage.c | 2 +- src/mainboard/google/snow/romstage.c | 2 +- src/mainboard/ti/beaglebone/romstage.c | 2 +- src/northbridge/amd/amdfam10/amdfam10.h | 2 +- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 2 +- util/genprof/README | 2 +- util/genprof/log2dress | 4 +- 29 files changed, 300 insertions(+), 300 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 90a50aa..72f3951 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -331,7 +331,7 @@ clean-abuild: rm -rf coreboot-builds clean-for-update-target: - rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a + rm -f $(obj)/ramstage* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot diff --git a/src/Kconfig b/src/Kconfig index 27f532b..4a9e843 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -166,7 +166,7 @@ config INCLUDE_CONFIG_FILE Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 - fallback/coreboot_ram 0x53440 stage 186664 + fallback/ramstage 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440 diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index f0adc0a..6395b0c 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -65,10 +65,10 @@ $(obj)/coreboot.pre: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD none (as specified by user)\n" endif @@ -117,17 +117,17 @@ $(stages_o): $(stages_c) $(obj)/config.h ################################################################################ -# Build the coreboot_ram (stage 2) +# Build the ramstage (stage 2) -$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/armv7/coreboot_ram.ld +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/armv7/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/coreboot_ram.ld + $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/coreboot_ram.ld $< + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $< endif -$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld deleted file mode 100644 index 452d2d7..0000000 --- a/src/arch/armv7/coreboot_ram.ld +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -INCLUDE ldoptions - -ENTRY(stage_entry) - -PHDRS -{ - to_load PT_LOAD; -} - -SECTIONS -{ - . = CONFIG_SYS_SDRAM_BASE; - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - _start = .; - *(.text.stage_entry.armv7); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } : to_load - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - _rodata = .; - . = ALIGN(4); - pci_drivers = . ; - *(.rodata.pci_driver) - epci_drivers = . ; - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - _bs_init_begin = .; - *(.bs_init) - _bs_init_end = .; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - _end = .; - - /* coreboot really "ends" here. Only heap and stack are placed after - * this line. - */ - - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; - - _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; - - /* The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* Discard the sections we don't need/want */ - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/armv7/ramstage.ld b/src/arch/armv7/ramstage.ld new file mode 100644 index 0000000..42090f4 --- /dev/null +++ b/src/arch/armv7/ramstage.ld @@ -0,0 +1,131 @@ +/* + * Memory map: + * + * CONFIG_RAMBASE : text segment + * : rodata segment + * : data segment + * : bss segment + * : stack + * : heap + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add ramstage cross the vga font buffer handling + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +INCLUDE ldoptions + +ENTRY(stage_entry) + +PHDRS +{ + to_load PT_LOAD; +} + +SECTIONS +{ + . = CONFIG_SYS_SDRAM_BASE; + /* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ + .text : { + _text = .; + _start = .; + *(.text.stage_entry.armv7); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } : to_load + + .ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + *(.ctors); + LONG(0); + __CTOR_END__ = .; + } + + .rodata : { + _rodata = .; + . = ALIGN(4); + pci_drivers = . ; + *(.rodata.pci_driver) + epci_drivers = . ; + cpu_drivers = . ; + *(.rodata.cpu_driver) + ecpu_drivers = . ; + _bs_init_begin = .; + *(.bs_init) + _bs_init_end = .; + *(.rodata) + *(.rodata.*) + /* kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + */ + . = ALIGN(4); + + _erodata = .; + } + /* After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + + /* bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + _end = .; + + /* coreboot really "ends" here. Only heap and stack are placed after + * this line. + */ + + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; + + _stack = CONFIG_STACK_BOTTOM; + _estack = CONFIG_STACK_TOP; + + /* The ram segment. This includes all memory used by the memory + * resident copy of coreboot, except the tables that are produced on + * the fly, but including stack and heap. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + /* Discard the sections we don't need/want */ + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 459f714..0203efb 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -16,7 +16,7 @@ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + * 2005.12 yhlu add ramstage cross the vga font buffer handling */ /* We use ELF as output format. So that we can debug the code in some form. */ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f986c3b..db8e500 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -99,10 +99,10 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD none (as specified by user)\n" endif @@ -205,31 +205,31 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug mv $@.tmp $@ ################################################################################ -# Build the coreboot_ram (stage 2) +# Build the ramstage (stage 2) ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -$(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE))) +$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE))) # The rmodule_link defintion creates an elf file with .rmod extension. -$(objcbfs)/coreboot_ram.elf: $(objcbfs)/coreboot_ram.debug.rmod +$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod cp $< $@ else -$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld + $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $< endif endif -$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) +$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/coreboot_ram.ld deleted file mode 100644 index 1d1143c..0000000 --- a/src/arch/x86/coreboot_ram.ld +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -INCLUDE ldoptions - -ENTRY(_start) - -SECTIONS -{ - . = CONFIG_RAMBASE; - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - *(.textfirst); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; - } - - .ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - __CTOR_END__ = .; - } - - .rodata : { - _rodata = .; - . = ALIGN(4); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - pci_drivers = . ; - *(.rodata.pci_driver) - epci_drivers = . ; - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - _bs_init_begin = .; - *(.bs_init) - _bs_init_end = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } - - /* bss does not contain data, it is just a space that should be zero - * initialized on startup. (typically uninitialized global variables) - * crt0.S fills between _bss and _ebss with zeroes. - */ - _bss = .; - .bss . : { - *(.bss) - *(.sbss) - *(COMMON) - } - _ebss = .; - - _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; - - /* The ram segment. This includes all memory used by the memory - * resident copy of coreboot, except the tables that are produced on - * the fly, but including stack and heap. - */ - _ram_seg = _text; - _eram_seg = _eheap; - - /* CONFIG_RAMTOP is the upper address of cached memory (among other - * things). We must not exceed beyond that address, there be dragons. - */ - _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); - - /* Discard the sections we don't need/want */ - - /DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) - } -} diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld new file mode 100644 index 0000000..1c8e8dc --- /dev/null +++ b/src/arch/x86/ramstage.ld @@ -0,0 +1,127 @@ +/* + * Memory map: + * + * CONFIG_RAMBASE : text segment + * : rodata segment + * : data segment + * : bss segment + * : stack + * : heap + */ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + * Rewritten by Eric Biederman + * 2005.12 yhlu add ramstage cross the vga font buffer handling + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +INCLUDE ldoptions + +ENTRY(_start) + +SECTIONS +{ + . = CONFIG_RAMBASE; + /* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ + .text : { + _text = .; + *(.textfirst); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; + } + + .ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + *(.ctors); + LONG(0); + __CTOR_END__ = .; + } + + .rodata : { + _rodata = .; + . = ALIGN(4); + + /* If any changes are made to the driver start/symbols or the + * section names the equivalent changes need to made to + * rmodule.ld. */ + pci_drivers = . ; + *(.rodata.pci_driver) + epci_drivers = . ; + cpu_drivers = . ; + *(.rodata.cpu_driver) + ecpu_drivers = . ; + _bs_init_begin = .; + *(.bs_init) + _bs_init_end = .; + + *(.rodata) + *(.rodata.*) + /* kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + */ + . = ALIGN(4); + + _erodata = .; + } + /* After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data : { + _data = .; + *(.data) + _edata = .; + } + + /* bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between _bss and _ebss with zeroes. + */ + _bss = .; + .bss . : { + *(.bss) + *(.sbss) + *(COMMON) + } + _ebss = .; + + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .; + + /* The ram segment. This includes all memory used by the memory + * resident copy of coreboot, except the tables that are produced on + * the fly, but including stack and heap. + */ + _ram_seg = _text; + _eram_seg = _eheap; + + /* CONFIG_RAMTOP is the upper address of cached memory (among other + * things). We must not exceed beyond that address, there be dragons. + */ + _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + + /* Discard the sections we don't need/want */ + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 24533c7..7776ae7 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) #if CONFIG_DCACHE_RAM_SIZE > 0x8000 wrmsr(MTRRfix4K_C0000_MSR, msr); #endif - /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + /* disable fixed mtrr from now on, it will be enabled by ramstage again*/ msr = rdmsr(SYSCFG_MSR); msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index f74f915..9712785 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -153,7 +153,7 @@ cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) set_sysinfo_in_ram(1); // So other core0 could start to train mem - /*copy and execute coreboot_ram */ + /*copy and execute ramstage */ copy_and_run(); /* We will not return */ diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c index 1118250..84fa548 100644 --- a/src/cpu/amd/geode_lx/msrinit.c +++ b/src/cpu/amd/geode_lx/msrinit.c @@ -42,11 +42,11 @@ static const msrinit_t msr_table[] = /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. * It doesn't really matter in fact how much, however, because the only usage - * of this extended memory will be to host the coreboot_ram stage at RAMBASE, + * of this extended memory will be to host the ramstage stage at RAMBASE, * currently 1Mb. * These registers will be set to their correct value by the Northbridge init code. * - * WARNING: if coreboot_ram could not be loaded, these registers are probably + * WARNING: if ramstage could not be loaded, these registers are probably * incorrectly set here. You may comment the following two lines and set RAMBASE * to 0x4000 to revert to the previous behavior for LX-boards. */ diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc index a269fb9..cc35060 100644 --- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc @@ -162,7 +162,7 @@ _clear_mtrrs_: post_code(0x38) /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. + * and ramstage. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index b791881..e46a2ee 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -227,7 +227,7 @@ before_romstage: post_code(0x38) /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. + * and ramstage. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 887d92b..1a19707 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -239,7 +239,7 @@ before_romstage: post_code(0x38) /* Enable Write Back and Speculative Reads for the first MB - * and coreboot_ram. + * and ramstage. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 814c5f1..9354738 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -1,5 +1,5 @@ /* - 2005.12 yhlu add coreboot_ram cross the vga font buffer handling + 2005.12 yhlu add ramstage cross the vga font buffer handling */ #include <console/console.h> diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index be2be82..71eb22c 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -36,7 +36,7 @@ static const struct ramstage_loader_ops *loaders[] = { &cbfs_ramstage_loader, }; -static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/ramstage"; static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; static void diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 63b99b3..6916b03 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -34,7 +34,7 @@ SECTIONS /* The driver sections are to allow linking coreboot's * ramstage with the rmodule linker. Any changes made in - * coreboot_ram.ld should be made here as well. */ + * ramstage.ld should be made here as well. */ pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index feff03e..8e9e0de 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -29,7 +29,7 @@ #include <bootmem.h> #include <payload_loader.h> -/* from coreboot_ram.ld: */ +/* from ramstage.ld: */ extern unsigned char _ram_seg; extern unsigned char _eram_seg; @@ -418,7 +418,7 @@ static int load_self_segments( /* Zero the extra bytes */ memset(middle, 0, end - middle); } - /* Copy the data that's outside the area that shadows coreboot_ram */ + /* Copy the data that's outside the area that shadows ramstage */ printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer); if ((unsigned long)end > bounce_buffer) { if ((unsigned long)dest < bounce_buffer) { diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 199842b..6a32c56 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -87,7 +87,7 @@ void main(void) a1x_set_cpu_clock(384); } - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); stage_exit(entry); diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c index 4a16436..00dfecd 100644 --- a/src/mainboard/emulation/qemu-armv7/romstage.c +++ b/src/mainboard/emulation/qemu-armv7/romstage.c @@ -23,7 +23,7 @@ void main(void) console_init(); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); stage_exit(entry); } diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index b74c27f..c971d0c 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -274,7 +274,7 @@ void main(void) cbmem_initialize_empty(); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); simple_spi_test(); stage_exit(entry); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index d45b861..3a8b5e8 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -186,6 +186,6 @@ void main(void) cbmem_initialize_empty(); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); stage_exit(entry); } diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone/romstage.c index e66a3dd..5dce23d 100644 --- a/src/mainboard/ti/beaglebone/romstage.c +++ b/src/mainboard/ti/beaglebone/romstage.c @@ -32,7 +32,7 @@ void main(void) console_init(); printk(BIOS_INFO, "Hello from romstage.\n"); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); stage_exit(entry); diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index aef2ad6..6e71b4e 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1033,7 +1033,7 @@ struct nodes_info_t { u32 up_planes; // down planes will be [up_planes, planes) } __attribute__((packed)); -/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/ +/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/ #if !CONFIG_AMDMCT //#define MEM_CS_COPY 1 diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index e5bcdcb..a4943bd 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -80,7 +80,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * pci1234[0] will record the south bridge link and bus range * pci1234[i] will record HT chain i. * - * For example, on the Tyan S2885 coreboot_ram will put the AMD8151 chain (HT + * For example, on the Tyan S2885 ramstage will put the AMD8151 chain (HT * link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the * register 0xE4. * diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 60f7abb..9dee295 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -177,7 +177,7 @@ static void bcm5785_early_setup(void) byte |= (1<<0); // SATA enable pci_write_config8(dev, 0x84, byte); -// WDT and cf9 for later in coreboot_ram to call hard_reset +// WDT and cf9 for later in ramstage to call hard_reset bcm5785_enable_wdt_port_cf9(); bcm5785_enable_msg(); diff --git a/util/genprof/README b/util/genprof/README index fc14849..d4159c2 100644 --- a/util/genprof/README +++ b/util/genprof/README @@ -26,6 +26,6 @@ that. Great use is: make -./genprof /tmp/yourlog ; gprof ../../build/coreboot_ram | ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png +./genprof /tmp/yourlog ; gprof ../../build/ramstage | ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png Which generates a PNG with a call graph. diff --git a/util/genprof/log2dress b/util/genprof/log2dress index c901a81..99d1f2f 100755 --- a/util/genprof/log2dress +++ b/util/genprof/log2dress @@ -10,9 +10,9 @@ A=`echo $line | cut -c 1` if [ "$A" = '~' ] ; then FROM=`echo $line | tr \~ $ | tr $ $ | awk -F\( '{print $3}'` TO=`echo $line | tr \~ \( | tr $ \(|awk -F\( '{print $2}'` -addr2line -e ../../build/cbfs/fallback/coreboot_ram.debug "$FROM" | tr -d "\n" +addr2line -e ../../build/cbfs/fallback/ramstage.debug "$FROM" | tr -d "\n" echo -n " calls " -addr2line -e ../../build/cbfs/fallback/coreboot_ram.debug "$TO" +addr2line -e ../../build/cbfs/fallback/ramstage.debug "$TO" else echo "$line" fi

1 0

New patch to review for coreboot: ad15b45 coreboot ARM: Get rid of HAVE_INIT_TIMER config option
by Furquan Shaikh 23 Apr '14

23 Apr '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5569 -gerrit commit ad15b45b4e658b08f86553f59e526cf379c49ace Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 22 11:48:30 2014 -0700 coreboot ARM: Get rid of HAVE_INIT_TIMER config option There is redundancy in terms of use of init_timer. We have a Kconfig option to decide whether a board has init_timer as well as we use stub for init_timer in places where we do not have any init_timer defined. Thus, removing the Kconfig option. Henceforth, all boards that do not have init_timer functionality can include include a stub_timer if required. Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/Kconfig | 5 ----- src/cpu/allwinner/a10/Kconfig | 1 - src/cpu/amd/agesa/family10/Kconfig | 4 ---- src/cpu/amd/agesa/family12/Kconfig | 4 ---- src/cpu/amd/agesa/family14/Kconfig | 4 ---- src/cpu/amd/agesa/family15/Kconfig | 4 ---- src/cpu/amd/agesa/family15tn/Kconfig | 4 ---- src/cpu/amd/agesa/family16kb/Kconfig | 4 ---- src/cpu/intel/model_2065x/Kconfig | 1 - src/drivers/pc80/udelay_io.c | 4 ++++ src/include/delay.h | 4 ---- src/mainboard/google/pit/Kconfig | 1 - 12 files changed, 4 insertions(+), 36 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 4a9e843..6356b19 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -321,11 +321,6 @@ config HAVE_HARD_RESET This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. -config HAVE_INIT_TIMER - bool - default n if UDELAY_IO - default y - config HAVE_MONOTONIC_TIMER def_bool n help diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 8512c38..267e1f4 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -6,7 +6,6 @@ if CPU_ALLWINNER_A10 config CPU_SPECIFIC_OPTIONS def_bool y - select HAVE_INIT_TIMER select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 621ee58..97802c7 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -45,10 +45,6 @@ config XIP_ROM_SIZE hex default 0x80000 -config HAVE_INIT_TIMER - bool - default y - config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" default n diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 757db9a..111a93e 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -57,8 +57,4 @@ config XIP_ROM_SIZE hex default 0x80000 -config HAVE_INIT_TIMER - bool - default y - endif diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 7acd520..4ff277f 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -57,10 +57,6 @@ config XIP_ROM_SIZE hex default 0x80000 -config HAVE_INIT_TIMER - bool - default y - config HIGH_SCRATCH_MEMORY_SIZE hex # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 02991a0..fbd6e3b 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -66,10 +66,6 @@ config XIP_ROM_SIZE hex default 0x80000 -config HAVE_INIT_TIMER - bool - default y - config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" default n diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 9885570..b9edc22 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -57,10 +57,6 @@ config XIP_ROM_SIZE hex default 0x100000 -config HAVE_INIT_TIMER - bool - default y - config HIGH_SCRATCH_MEMORY_SIZE hex # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 9a8bce2..c9f4fb2 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -61,10 +61,6 @@ config XIP_ROM_SIZE hex default 0x100000 -config HAVE_INIT_TIMER - bool - default y - config HIGH_SCRATCH_MEMORY_SIZE hex # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 50a7e6c..bbb4eb1 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -11,7 +11,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG - select HAVE_INIT_TIMER select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/drivers/pc80/udelay_io.c b/src/drivers/pc80/udelay_io.c index 37f3f73..48ff32c 100644 --- a/src/drivers/pc80/udelay_io.c +++ b/src/drivers/pc80/udelay_io.c @@ -1,6 +1,10 @@ #include <arch/io.h> #include <delay.h> +void init_timer(void) +{ +} + void udelay(unsigned usecs) { int i; diff --git a/src/include/delay.h b/src/include/delay.h index 676579b..b3d8ed9 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,11 +1,7 @@ #ifndef DELAY_H #define DELAY_H -#if CONFIG_HAVE_INIT_TIMER void init_timer(void); -#else -#define init_timer() do{} while(0) -#endif void udelay(unsigned usecs); void mdelay(unsigned msecs); diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index 1c20015..e7e9a31 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT - select HAVE_INIT_TIMER select DRIVER_PARADE_PS8625 config MAINBOARD_DIR

1 0

Patch set updated for coreboot: 6b5765e coreboot: Move ARCH_* from board/Kconfig to cpu or soc Kconfig
by Furquan Shaikh 23 Apr '14

23 Apr '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5570 -gerrit commit 6b5765ef562df92d1d734fe317bbffc60f0ce703 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 22 15:16:54 2014 -0700 coreboot: Move ARCH_* from board/Kconfig to cpu or soc Kconfig CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, moving ARCH_* from every single board to respective cpu or soc Kconfigs. Also updated abuild to ignore ARCH_ from mainboard Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/cpu/Kconfig | 7 +-- src/cpu/allwinner/a10/Kconfig | 1 + src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/geode_gx1/Kconfig | 1 + src/cpu/amd/geode_gx2/Kconfig | 1 + src/cpu/amd/geode_lx/Kconfig | 1 + src/cpu/amd/model_10xxx/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/cpu/amd/sc520/Kconfig | 1 + src/cpu/armltd/cortex-a9/Kconfig | 2 +- src/cpu/dmp/vortex86ex/Kconfig | 1 + src/cpu/intel/ep80579/Kconfig | 1 + src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_1067x/Kconfig | 1 + src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_206ax/Kconfig | 1 + src/cpu/intel/model_65x/Kconfig | 1 + src/cpu/intel/model_67x/Kconfig | 1 + src/cpu/intel/model_68x/Kconfig | 1 + src/cpu/intel/model_69x/Kconfig | 1 + src/cpu/intel/model_6bx/Kconfig | 1 + src/cpu/intel/model_6dx/Kconfig | 1 + src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/intel/model_6xx/Kconfig | 1 + src/cpu/intel/model_f0x/Kconfig | 1 + src/cpu/intel/model_f1x/Kconfig | 1 + src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/intel/model_f3x/Kconfig | 1 + src/cpu/intel/model_f4x/Kconfig | 1 + src/cpu/qemu-x86/Kconfig | 1 + src/cpu/samsung/exynos5250/Kconfig | 2 +- src/cpu/samsung/exynos5420/Kconfig | 2 +- src/cpu/ti/am335x/Kconfig | 2 +- src/cpu/via/c3/Kconfig | 1 + src/cpu/via/c7/Kconfig | 1 + src/cpu/via/nano/Kconfig | 1 + src/mainboard/a-trend/atc-6220/Kconfig | 1 - src/mainboard/a-trend/atc-6240/Kconfig | 1 - src/mainboard/aaeon/pfm-540i_revb/Kconfig | 1 - src/mainboard/abit/be6-ii_v2_0/Kconfig | 1 - src/mainboard/advansus/a785e-i/Kconfig | 1 - src/mainboard/advantech/pcm-5820/Kconfig | 1 - src/mainboard/amd/bimini_fam10/Kconfig | 1 - src/mainboard/amd/db800/Kconfig | 1 - src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/dinar/Kconfig | 1 - src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/mahogany/Kconfig | 1 - src/mainboard/amd/mahogany_fam10/Kconfig | 1 - src/mainboard/amd/norwich/Kconfig | 1 - src/mainboard/amd/olivehill/Kconfig | 1 - src/mainboard/amd/parmer/Kconfig | 1 - src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/amd/rumba/Kconfig | 1 - src/mainboard/amd/serengeti_cheetah/Kconfig | 1 - src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 1 - src/mainboard/amd/south_station/Kconfig | 1 - src/mainboard/amd/thatcher/Kconfig | 1 - src/mainboard/amd/tilapia_fam10/Kconfig | 1 - src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/aopen/dxplplusu/Kconfig | 1 - src/mainboard/arima/hdama/Kconfig | 1 - src/mainboard/artecgroup/dbe61/Kconfig | 1 - src/mainboard/asi/mb_5blgp/Kconfig | 1 - src/mainboard/asi/mb_5blmp/Kconfig | 1 - src/mainboard/asrock/939a785gmh/Kconfig | 1 - src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asrock/imb-a180/Kconfig | 1 - src/mainboard/asus/a8n_e/Kconfig | 1 - src/mainboard/asus/a8n_sli/Kconfig | 1 - src/mainboard/asus/a8v-e_deluxe/Kconfig | 1 - src/mainboard/asus/a8v-e_se/Kconfig | 1 - src/mainboard/asus/dsbf/Kconfig | 1 - src/mainboard/asus/f2a85-m/Kconfig | 1 - src/mainboard/asus/k8v-x/Kconfig | 1 - src/mainboard/asus/m2n-e/Kconfig | 1 - src/mainboard/asus/m2v-mx_se/Kconfig | 1 - src/mainboard/asus/m2v/Kconfig | 1 - src/mainboard/asus/m4a78-em/Kconfig | 1 - src/mainboard/asus/m4a785-m/Kconfig | 1 - src/mainboard/asus/m4a785t-m/Kconfig | 1 - src/mainboard/asus/m5a88-v/Kconfig | 1 - src/mainboard/asus/mew-am/Kconfig | 1 - src/mainboard/asus/mew-vm/Kconfig | 1 - src/mainboard/asus/p2b-d/Kconfig | 1 - src/mainboard/asus/p2b-ds/Kconfig | 1 - src/mainboard/asus/p2b-f/Kconfig | 1 - src/mainboard/asus/p2b-ls/Kconfig | 1 - src/mainboard/asus/p2b/Kconfig | 1 - src/mainboard/asus/p3b-f/Kconfig | 1 - src/mainboard/avalue/eax-785e/Kconfig | 1 - src/mainboard/axus/tc320/Kconfig | 1 - src/mainboard/azza/pt-6ibd/Kconfig | 1 - src/mainboard/bachmann/ot200/Kconfig | 1 - src/mainboard/bcom/winnet100/Kconfig | 1 - src/mainboard/bcom/winnetp680/Kconfig | 1 - src/mainboard/biostar/m6tba/Kconfig | 1 - src/mainboard/broadcom/blast/Kconfig | 1 - src/mainboard/compaq/deskpro_en_sff_p600/Kconfig | 1 - src/mainboard/cubietech/cubieboard/Kconfig | 1 - src/mainboard/digitallogic/adl855pc/Kconfig | 1 - src/mainboard/digitallogic/msm586seg/Kconfig | 1 - src/mainboard/digitallogic/msm800sev/Kconfig | 1 - src/mainboard/dmp/vortex86ex/Kconfig | 1 - src/mainboard/eaglelion/5bcm/Kconfig | 1 - src/mainboard/ecs/p6iwp-fe/Kconfig | 1 - src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/gigabyte/ga-6bxc/Kconfig | 1 - src/mainboard/gigabyte/ga-6bxe/Kconfig | 1 - src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 1 - src/mainboard/gigabyte/m57sli/Kconfig | 1 - src/mainboard/gigabyte/ma785gm/Kconfig | 1 - src/mainboard/gigabyte/ma785gmt/Kconfig | 1 - src/mainboard/gigabyte/ma78gm/Kconfig | 1 - src/mainboard/gizmosphere/gizmo/Kconfig | 1 - src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/pit/Kconfig | 1 - src/mainboard/google/rambi/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/google/snow/Kconfig | 1 - src/mainboard/google/stout/Kconfig | 1 - src/mainboard/hp/dl145_g1/Kconfig | 1 - src/mainboard/hp/dl145_g3/Kconfig | 1 - src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 - src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 - src/mainboard/ibase/mb899/Kconfig | 1 - src/mainboard/ibm/e325/Kconfig | 1 - src/mainboard/ibm/e326/Kconfig | 1 - src/mainboard/iei/juki-511p/Kconfig | 1 - src/mainboard/iei/kino-780am2-fam10/Kconfig | 1 - src/mainboard/iei/nova4899r/Kconfig | 1 - src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 1 - src/mainboard/iei/pm-lx-800-r11/Kconfig | 1 - src/mainboard/iei/pm-lx2-800-r10/Kconfig | 1 - src/mainboard/iei/rocky-512/Kconfig | 1 - src/mainboard/intel/baskingridge/Kconfig | 1 - src/mainboard/intel/cougar_canyon2/Kconfig | 1 - src/mainboard/intel/d810e2cb/Kconfig | 1 - src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/intel/eagleheights/Kconfig | 1 - src/mainboard/intel/emeraldlake2/Kconfig | 1 - src/mainboard/intel/jarrell/Kconfig | 1 - src/mainboard/intel/mtarvon/Kconfig | 1 - src/mainboard/intel/truxton/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/mainboard/intel/xe7501devkit/Kconfig | 1 - src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/mainboard/iwill/dk8_htx/Kconfig | 1 - src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/iwill/dk8x/Kconfig | 1 - src/mainboard/jetway/j7f2/Kconfig | 1 - src/mainboard/jetway/j7f4k1g2e/Kconfig | 1 - src/mainboard/jetway/j7f4k1g5d/Kconfig | 1 - src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 - src/mainboard/jetway/pa78vm5/Kconfig | 1 - src/mainboard/kontron/986lcd-m/Kconfig | 1 - src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/lanner/em8510/Kconfig | 1 - src/mainboard/lenovo/t530/Kconfig | 1 - src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x201/Kconfig | 1 - src/mainboard/lenovo/x230/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 - src/mainboard/linutop/linutop1/Kconfig | 1 - src/mainboard/lippert/frontrunner-af/Kconfig | 1 - src/mainboard/lippert/frontrunner/Kconfig | 1 - src/mainboard/lippert/hurricane-lx/Kconfig | 1 - src/mainboard/lippert/literunner-lx/Kconfig | 1 - src/mainboard/lippert/roadrunner-lx/Kconfig | 1 - src/mainboard/lippert/spacerunner-lx/Kconfig | 1 - src/mainboard/lippert/toucan-af/Kconfig | 1 - src/mainboard/mitac/6513wu/Kconfig | 1 - src/mainboard/msi/ms6119/Kconfig | 1 - src/mainboard/msi/ms6147/Kconfig | 1 - src/mainboard/msi/ms6156/Kconfig | 1 - src/mainboard/msi/ms6178/Kconfig | 1 - src/mainboard/msi/ms7135/Kconfig | 1 - src/mainboard/msi/ms7260/Kconfig | 1 - src/mainboard/msi/ms9185/Kconfig | 1 - src/mainboard/msi/ms9282/Kconfig | 1 - src/mainboard/msi/ms9652_fam10/Kconfig | 1 - src/mainboard/nec/powermate2000/Kconfig | 1 - src/mainboard/newisys/khepri/Kconfig | 1 - src/mainboard/nokia/ip530/Kconfig | 1 - src/mainboard/nvidia/l1_2pvv/Kconfig | 1 - src/mainboard/pcengines/alix1c/Kconfig | 1 - src/mainboard/pcengines/alix2c/Kconfig | 1 - src/mainboard/pcengines/alix2d/Kconfig | 1 - src/mainboard/pcengines/alix6/Kconfig | 1 - src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/roda/rk886ex/Kconfig | 1 - src/mainboard/roda/rk9/Kconfig | 1 - src/mainboard/samsung/lumpy/Kconfig | 1 - src/mainboard/samsung/stumpy/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/soyo/sy-6ba-plus-iii/Kconfig | 1 - src/mainboard/sunw/ultra40/Kconfig | 1 - src/mainboard/supermicro/h8dme/Kconfig | 1 - src/mainboard/supermicro/h8dmr/Kconfig | 1 - src/mainboard/supermicro/h8dmr_fam10/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Kconfig | 1 - src/mainboard/supermicro/h8qme_fam10/Kconfig | 1 - src/mainboard/supermicro/h8scm/Kconfig | 1 - src/mainboard/supermicro/h8scm_fam10/Kconfig | 1 - src/mainboard/supermicro/x6dai_g/Kconfig | 1 - src/mainboard/supermicro/x6dhe_g/Kconfig | 1 - src/mainboard/supermicro/x6dhe_g2/Kconfig | 1 - src/mainboard/supermicro/x6dhr_ig/Kconfig | 1 - src/mainboard/supermicro/x6dhr_ig2/Kconfig | 1 - src/mainboard/supermicro/x7db8/Kconfig | 1 - src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim8690/Kconfig | 1 - src/mainboard/technologic/ts5300/Kconfig | 1 - src/mainboard/televideo/tc7020/Kconfig | 1 - src/mainboard/thomson/ip1000/Kconfig | 1 - src/mainboard/ti/beaglebone/Kconfig | 1 - src/mainboard/traverse/geos/Kconfig | 1 - src/mainboard/tyan/s1846/Kconfig | 1 - src/mainboard/tyan/s2735/Kconfig | 1 - src/mainboard/tyan/s2850/Kconfig | 1 - src/mainboard/tyan/s2875/Kconfig | 1 - src/mainboard/tyan/s2880/Kconfig | 1 - src/mainboard/tyan/s2881/Kconfig | 1 - src/mainboard/tyan/s2882/Kconfig | 1 - src/mainboard/tyan/s2885/Kconfig | 1 - src/mainboard/tyan/s2891/Kconfig | 1 - src/mainboard/tyan/s2892/Kconfig | 1 - src/mainboard/tyan/s2895/Kconfig | 1 - src/mainboard/tyan/s2912/Kconfig | 1 - src/mainboard/tyan/s2912_fam10/Kconfig | 1 - src/mainboard/tyan/s4880/Kconfig | 1 - src/mainboard/tyan/s4882/Kconfig | 1 - src/mainboard/tyan/s8226/Kconfig | 1 - src/mainboard/via/epia-cn/Kconfig | 1 - src/mainboard/via/epia-m/Kconfig | 1 - src/mainboard/via/epia-m700/Kconfig | 1 - src/mainboard/via/epia-m850/Kconfig | 1 - src/mainboard/via/epia-mii/Kconfig | 1 - src/mainboard/via/epia-ml/Kconfig | 1 - src/mainboard/via/epia-n/Kconfig | 1 - src/mainboard/via/epia/Kconfig | 1 - src/mainboard/via/pc2500e/Kconfig | 1 - src/mainboard/via/vt8454c/Kconfig | 1 - src/mainboard/winent/mb6047/Kconfig | 1 - src/mainboard/winent/pl6064/Kconfig | 1 - src/mainboard/wyse/s50/Kconfig | 1 - src/soc/Kconfig | 2 - src/soc/intel/baytrail/Kconfig | 1 + util/abuild/abuild | 52 ----------------------- 264 files changed, 41 insertions(+), 285 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f3883d3..aec6330 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -1,17 +1,12 @@ # Warning: This file is included whether or not the if is here. # The if controls how the evaluation occurs. # (See also src/Kconfig) -if ARCH_ARMV7 source src/cpu/allwinner/Kconfig source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig source src/cpu/ti/Kconfig -endif # ARCH_ARM - -if ARCH_X86 - source src/cpu/amd/Kconfig source src/cpu/dmp/Kconfig source src/cpu/intel/Kconfig @@ -19,6 +14,8 @@ source src/cpu/via/Kconfig source src/cpu/qemu-x86/Kconfig source src/cpu/x86/Kconfig +if ARCH_X86 + config CACHE_AS_RAM bool default !ROMCC diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 267e1f4..f76a7b6 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -6,6 +6,7 @@ if CPU_ALLWINNER_A10 config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index a73c5ce..fa36f38 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,6 +26,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n + select ARCH_X86 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER diff --git a/src/cpu/amd/geode_gx1/Kconfig b/src/cpu/amd/geode_gx1/Kconfig index fa1d052..b87e8bc 100644 --- a/src/cpu/amd/geode_gx1/Kconfig +++ b/src/cpu/amd/geode_gx1/Kconfig @@ -19,6 +19,7 @@ config CPU_AMD_GEODE_GX1 bool + select ARCH_X86 if CPU_AMD_GEODE_GX1 diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index fe5a291..b96c770 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -19,6 +19,7 @@ config CPU_AMD_GEODE_GX2 bool + select ARCH_X86 if CPU_AMD_GEODE_GX2 diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index ac59c3f..6aceab2 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -1,5 +1,6 @@ config CPU_AMD_GEODE_LX bool + select ARCH_X86 if CPU_AMD_GEODE_LX diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 99358e0..2d061f1 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -1,5 +1,6 @@ config CPU_AMD_MODEL_10XXX bool + select ARCH_X86 select SSE select SSE2 select MMCONF_SUPPORT_DEFAULT diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index fb094b1..e92e5e2 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -1,5 +1,6 @@ config CPU_AMD_MODEL_FXX bool + select ARCH_X86 select MMX select SSE select SSE2 diff --git a/src/cpu/amd/sc520/Kconfig b/src/cpu/amd/sc520/Kconfig index 6d9494e..46377be 100644 --- a/src/cpu/amd/sc520/Kconfig +++ b/src/cpu/amd/sc520/Kconfig @@ -1,2 +1,3 @@ config CPU_AMD_SC520 bool + select ARCH_X86 diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index 04861a6..f46c6ff 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -1,6 +1,6 @@ config CPU_ARMLTD_CORTEX_A9 - depends on ARCH_ARMV7 bool + select ARCH_ARMV7 select EARLY_CONSOLE default n diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 54db4e0..aea8889 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -19,4 +19,5 @@ config CPU_DMP_VORTEX86EX bool + select ARCH_X86 select UDELAY_TSC diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 380869a..fa96f8d 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_EP80579 bool + select ARCH_X86 select SSE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 6a008bf..22d01e6 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -28,6 +28,7 @@ if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index b13d686..97309ae 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,6 +6,7 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select BACKUP_DEFAULT_SMM_REGION select SMP select SSE2 diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 7d5bf94..4d6add6 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,5 +1,6 @@ config CPU_INTEL_MODEL_1067X bool + select ARCH_X86 select SMP select SSE2 select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index c438008..ea6f5ca 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,5 +1,6 @@ config CPU_INTEL_MODEL_106CX bool + select ARCH_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index bbb4eb1..4c7456d 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -5,6 +5,7 @@ if CPU_INTEL_MODEL_2065X config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select SMP select SSE select SSE2 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 90af45d..64b2a0a 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -8,6 +8,7 @@ if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index e8f0767..b3fa7bd 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_65X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 74ef8d5..7558bc2 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_67X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 9d9983e..670163a 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -20,5 +20,6 @@ config CPU_INTEL_MODEL_68X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig index 4e88979..e4a0e6c 100644 --- a/src/cpu/intel/model_69x/Kconfig +++ b/src/cpu/intel/model_69x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_69X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 26b5995..4dc6fe6 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_6BX bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig index 546d9ec..e6d5f1e 100644 --- a/src/cpu/intel/model_6dx/Kconfig +++ b/src/cpu/intel/model_6dx/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_6DX bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 8187838..eee864d 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,5 +1,6 @@ config CPU_INTEL_MODEL_6EX bool + select ARCH_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 3335a26..b8de303 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,5 +1,6 @@ config CPU_INTEL_MODEL_6FX bool + select ARCH_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index b572385..49cfe2d 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_6XX bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig index 0616589..2ed68d1 100644 --- a/src/cpu/intel/model_f0x/Kconfig +++ b/src/cpu/intel/model_f0x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_F0X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig index fd64920..3bdb7f6 100644 --- a/src/cpu/intel/model_f1x/Kconfig +++ b/src/cpu/intel/model_f1x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_F1X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 8483d33..62393a8 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_F2X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 8ae2dcf..5c9d0a3 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_F3X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index c21a274..849dcd0 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,4 +1,5 @@ config CPU_INTEL_MODEL_F4X bool + select ARCH_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 6c5c3fd..e54e4db 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,3 +19,4 @@ config CPU_QEMU_X86 bool + select ARCH_X86 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 9320184..b8042e3 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,5 +1,5 @@ config CPU_SAMSUNG_EXYNOS5250 - depends on ARCH_ARMV7 + select ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 5f78cc5..6207adf 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -1,5 +1,5 @@ config CPU_SAMSUNG_EXYNOS5420 - depends on ARCH_ARMV7 + select ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index fdc5824..22a02ad 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -1,5 +1,5 @@ config CPU_TI_AM335X - depends on ARCH_ARMV7 + select ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig index 259a1f2..566f07c 100644 --- a/src/cpu/via/c3/Kconfig +++ b/src/cpu/via/c3/Kconfig @@ -5,6 +5,7 @@ if CPU_VIA_C3 config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select UDELAY_TSC select MMX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index ebbb8f9..d5f1a41 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -5,6 +5,7 @@ if CPU_VIA_C7 config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select UDELAY_TSC select MMX select SSE2 diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 674c0f3..0f4f994 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -24,6 +24,7 @@ if CPU_VIA_NANO config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select UDELAY_TSC select MMX select SSE2 diff --git a/src/mainboard/a-trend/atc-6220/Kconfig b/src/mainboard/a-trend/atc-6220/Kconfig index 81c23a8..036d8e6 100644 --- a/src/mainboard/a-trend/atc-6220/Kconfig +++ b/src/mainboard/a-trend/atc-6220/Kconfig @@ -20,7 +20,6 @@ if BOARD_A_TREND_ATC_6220 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/a-trend/atc-6240/Kconfig b/src/mainboard/a-trend/atc-6240/Kconfig index da94c7f..d19f92d 100644 --- a/src/mainboard/a-trend/atc-6240/Kconfig +++ b/src/mainboard/a-trend/atc-6240/Kconfig @@ -20,7 +20,6 @@ if BOARD_A_TREND_ATC_6240 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig index 9986987..6b156b2 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig +++ b/src/mainboard/aaeon/pfm-540i_revb/Kconfig @@ -2,7 +2,6 @@ if BOARD_AAEON_PFM_540I_REVB config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/abit/be6-ii_v2_0/Kconfig b/src/mainboard/abit/be6-ii_v2_0/Kconfig index feb00de..5dc1ca0 100644 --- a/src/mainboard/abit/be6-ii_v2_0/Kconfig +++ b/src/mainboard/abit/be6-ii_v2_0/Kconfig @@ -20,7 +20,6 @@ if BOARD_ABIT_BE6_II_V2_0 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 32500d6..52ec827 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -2,7 +2,6 @@ if BOARD_ADVANSUS_A785E_I config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_ASB2 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig index 25ff69c..86bcd7a 100644 --- a/src/mainboard/advantech/pcm-5820/Kconfig +++ b/src/mainboard/advantech/pcm-5820/Kconfig @@ -20,7 +20,6 @@ if BOARD_ADVANTECH_PCM_5820 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index a04c131..f9557b2 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_BIMINI_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_ASB2 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig index ee2aa0f..c6f99e9 100644 --- a/src/mainboard/amd/db800/Kconfig +++ b/src/mainboard/amd/db800/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_DB800 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index ba68a54..70d63ad 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_DBM690T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index b5434b4..068af32 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_DINAR config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_G34 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 8ce4aae..58937a4 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_INAGUA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 7e3486f..394ad77 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_MAHOGANY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index 2bc6a1d..b719592 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_MAHOGANY_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2R2 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig index dec8e01..eb83c1e 100644 --- a/src/mainboard/amd/norwich/Kconfig +++ b/src/mainboard/amd/norwich/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_NORWICH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 8be5a18..452f16d 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 16fadfa..df26b2b 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_PARMER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e4ae8d0..14c9617 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 2eb6612..9a91eec 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_PISTACHIO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index d600a58..2aea274 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -20,7 +20,6 @@ if BOARD_AMD_RUMBA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index 5a6f022..53dd595 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_SERENGETI_CHEETAH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_AMD_AMD8151 select CPU_AMD_SOCKET_F diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 37cbfa4..04a1ce0 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_SERENGETI_CHEETAH_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index d7e848d..97aebf8 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_SOUTHSTATION config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index 66374f2..1f12883 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_THATCHER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 111ac29..7ebf487 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_AMD_TILAPIA_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 5191720..3d949fe 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_TORPEDO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select DIMM_DDR3 select DIMM_UNREGISTERED select CPU_AMD_AGESA_FAMILY12 diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 7d9f115..df116a4 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -21,7 +21,6 @@ if BOARD_AMD_UNIONSTATION config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c620c9a..1802b5a 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -2,7 +2,6 @@ if BOARD_AOPEN_DXPLPLUSU config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7505 select SOUTHBRIDGE_INTEL_I82870 diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 2b6f758..49860b3 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -2,7 +2,6 @@ if BOARD_ARIMA_HDAMA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig index 99a6218..c512f7b 100644 --- a/src/mainboard/artecgroup/dbe61/Kconfig +++ b/src/mainboard/artecgroup/dbe61/Kconfig @@ -2,7 +2,6 @@ if BOARD_ARTECGROUP_DBE61 || BOARD_LINUTOP_LINUTOP1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig index 08ab2e0..f69f6ef 100644 --- a/src/mainboard/asi/mb_5blgp/Kconfig +++ b/src/mainboard/asi/mb_5blgp/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASI_MB_5BLGP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig index e8c8dde..a40c86c 100644 --- a/src/mainboard/asi/mb_5blmp/Kconfig +++ b/src/mainboard/asi/mb_5blmp/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASI_MB_5BLMP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index 9d3dd5c..cfaa599 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASROCK_939A785GMH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index e430688..eacf834 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -21,7 +21,6 @@ if BOARD_ASROCK_E350M1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index ccd060e..d27e1d4 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -21,7 +21,6 @@ if BOARD_ASROCK_IMB_A180 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 43a2d2c..86601ed 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_A8N_E || BOARD_ASUS_A8N_SLI config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/asus/a8n_sli/Kconfig b/src/mainboard/asus/a8n_sli/Kconfig index fdeaf87..e2ac03d 100644 --- a/src/mainboard/asus/a8n_sli/Kconfig +++ b/src/mainboard/asus/a8n_sli/Kconfig @@ -1,7 +1,6 @@ if BOARD_ASUS_A8N_SLI # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index e953ed4..a1533c4 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_A8V_E_DELUXE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index c5b9374..dcc75fa 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_A8V_E_SE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 99aa56d..c130a9f 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_DSBF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA771 select SOUTHBRIDGE_INTEL_I3100 select NORTHBRIDGE_INTEL_I5000 diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 3859156..2280451 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -22,7 +22,6 @@ if BOARD_ASUS_F2A85_M config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 51426ac..0e829f0 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 959ad6c..5f7a39e 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -22,7 +22,6 @@ if BOARD_ASUS_M2N_E config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index f76ff7b..2c1331f 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_M2V_MX_SE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 263bad9..0993096 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_M2V config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index 197b3a0..744b881 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_M4A78_EM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDFAM10 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index f6ba242..9e49ba0 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_M4A785M config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDFAM10 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index af4fb7c..1a709bc 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_M4A785TM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 7ff25d4..ae59599 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -2,7 +2,6 @@ if BOARD_ASUS_M5A88_V config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index ffd6e22..ad08c31 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_MEW_AM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 341c533..58910be 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_MEW_VM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig index 54a1bae..b84a142 100644 --- a/src/mainboard/asus/p2b-d/Kconfig +++ b/src/mainboard/asus/p2b-d/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_P2B_D config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig index 652b31a..6a70e71 100644 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ b/src/mainboard/asus/p2b-ds/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_P2B_DS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig index e0554ca..07fa744 100644 --- a/src/mainboard/asus/p2b-f/Kconfig +++ b/src/mainboard/asus/p2b-f/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_P2B_F config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index f138463..3822eb7 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_P2B_LS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index a57f7fb..b1b5597 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_P2B config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig index d47dfdb..07cd91f 100644 --- a/src/mainboard/asus/p3b-f/Kconfig +++ b/src/mainboard/asus/p3b-f/Kconfig @@ -20,7 +20,6 @@ if BOARD_ASUS_P3B_F config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index abfaaec..3b96d19 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -2,7 +2,6 @@ if BOARD_AVALUE_EAX_785E config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig index 868c8d1..97c33aa 100644 --- a/src/mainboard/axus/tc320/Kconfig +++ b/src/mainboard/axus/tc320/Kconfig @@ -20,7 +20,6 @@ if BOARD_AXUS_TC320 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/azza/pt-6ibd/Kconfig b/src/mainboard/azza/pt-6ibd/Kconfig index 50ac62b..8897102 100644 --- a/src/mainboard/azza/pt-6ibd/Kconfig +++ b/src/mainboard/azza/pt-6ibd/Kconfig @@ -20,7 +20,6 @@ if BOARD_AZZA_PT_6IBD config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index 23b206e..baef807 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -2,7 +2,6 @@ if BOARD_BACHMANN_OT200 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig index d0a7807..503c92b 100644 --- a/src/mainboard/bcom/winnet100/Kconfig +++ b/src/mainboard/bcom/winnet100/Kconfig @@ -20,7 +20,6 @@ if BOARD_BCOM_WINNET100 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/bcom/winnetp680/Kconfig b/src/mainboard/bcom/winnetp680/Kconfig index 78e014e..f6a80af 100644 --- a/src/mainboard/bcom/winnetp680/Kconfig +++ b/src/mainboard/bcom/winnetp680/Kconfig @@ -2,7 +2,6 @@ if BOARD_BCOM_WINNETP680 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/biostar/m6tba/Kconfig b/src/mainboard/biostar/m6tba/Kconfig index 8d86ab4..d83ceac 100644 --- a/src/mainboard/biostar/m6tba/Kconfig +++ b/src/mainboard/biostar/m6tba/Kconfig @@ -20,7 +20,6 @@ if BOARD_BIOSTAR_M6TBA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index 502576c..a02fa12 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -2,7 +2,6 @@ if BOARD_BROADCOM_BLAST config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig index 1242a94..62f038c 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig +++ b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig @@ -20,7 +20,6 @@ if BOARD_COMPAQ_DESKPRO_EN_SFF_P600 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig index 6cb84cf..176a3b3 100644 --- a/src/mainboard/cubietech/cubieboard/Kconfig +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -2,7 +2,6 @@ if BOARD_CUBIETECH_CUBIEBOARD config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_ARMV7 select CPU_ALLWINNER_A10 select BOARD_ROMSIZE_KB_4096 select DRIVER_XPOWERS_AXP209 diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index a20a5c8..8c57a89 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -2,7 +2,6 @@ if BOARD_DIGITALLOGIC_ADL855PC config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/mainboard/digitallogic/msm586seg/Kconfig b/src/mainboard/digitallogic/msm586seg/Kconfig index d54037a..4cd6f11 100644 --- a/src/mainboard/digitallogic/msm586seg/Kconfig +++ b/src/mainboard/digitallogic/msm586seg/Kconfig @@ -2,7 +2,6 @@ if BOARD_DIGITALLOGIC_MSM586SEG config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SC520 select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig index 0b54906..bc8e3ac 100644 --- a/src/mainboard/digitallogic/msm800sev/Kconfig +++ b/src/mainboard/digitallogic/msm800sev/Kconfig @@ -2,7 +2,6 @@ if BOARD_DIGITALLOGIC_MSM800SEV config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index 4b130b8..b164ca5 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -21,7 +21,6 @@ if BOARD_DMP_EX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_DMP_VORTEX86EX select NORTHBRIDGE_DMP_VORTEX86EX select SOUTHBRIDGE_DMP_VORTEX86EX diff --git a/src/mainboard/eaglelion/5bcm/Kconfig b/src/mainboard/eaglelion/5bcm/Kconfig index cc507f0..3c0a800 100644 --- a/src/mainboard/eaglelion/5bcm/Kconfig +++ b/src/mainboard/eaglelion/5bcm/Kconfig @@ -20,7 +20,6 @@ if BOARD_EAGLELION_5BCM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index c88d976..99170be 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -21,7 +21,6 @@ if BOARD_ECS_P6IWP_FE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 040ed9c..7865abd 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -23,7 +23,6 @@ if BOARD_EMULATION_QEMU_ARMV7 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 select DRIVERS_UART_PL011 select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index b9df41e..0a750df 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -2,7 +2,6 @@ if BOARD_EMULATION_QEMU_X86_I440FX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82371EB select CACHE_AS_RAM diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index ad7576b..674d890 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -2,7 +2,6 @@ if BOARD_EMULATION_QEMU_X86_Q35 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index db42233..3696b14 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -20,7 +20,6 @@ if BOARD_GETAC_P470 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/gigabyte/ga-6bxc/Kconfig b/src/mainboard/gigabyte/ga-6bxc/Kconfig index 62625fb..8ea1abd 100644 --- a/src/mainboard/gigabyte/ga-6bxc/Kconfig +++ b/src/mainboard/gigabyte/ga-6bxc/Kconfig @@ -20,7 +20,6 @@ if BOARD_GIGABYTE_GA_6BXC config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/gigabyte/ga-6bxe/Kconfig b/src/mainboard/gigabyte/ga-6bxe/Kconfig index 6e3462e..5b35e7d 100644 --- a/src/mainboard/gigabyte/ga-6bxe/Kconfig +++ b/src/mainboard/gigabyte/ga-6bxe/Kconfig @@ -21,7 +21,6 @@ if BOARD_GIGABYTE_GA_6BXE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index 9b0ef05..3fbb8cd 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -2,7 +2,6 @@ if BOARD_GIGABYTE_GA_2761GXDK config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 1ffa552..491df9c 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -2,7 +2,6 @@ if BOARD_GIGABYTE_M57SLI config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 7582320..94b449f 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -2,7 +2,6 @@ if BOARD_GIGABYTE_MA785GM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 0ea4eb7..f98c0dd 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -2,7 +2,6 @@ if BOARD_GIGABYTE_MA785GMT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM3 select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index d663eca..4a87aab 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -2,7 +2,6 @@ if BOARD_GIGABYTE_MA78GM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2R2 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 85eddfb..5c94723 100755 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -22,7 +22,6 @@ if BOARD_GIZMOSPHERE_GIZMO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 47d41ed..0910661 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_BOLT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 51ce13b..1b7fe32 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_BUTTERFLY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 5d19ffc..b369d62 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_FALCO config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index efe9519..fcecca0 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_LINK config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index d8a4e7a..23cea06 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_PARROT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index f401feb..204e28d 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_PEPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index e7e9a31..861740f 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -21,7 +21,6 @@ if BOARD_GOOGLE_PIT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5420 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 00af512..c0cb8ca 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_RAMBI config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select SOC_INTEL_BAYTRAIL select EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index ba6a6fe..3c34938 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_SLIPPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index e808eb8..14e26a9 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -21,7 +21,6 @@ if BOARD_GOOGLE_SNOW config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5250 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index d5e265f..e683455 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -2,7 +2,6 @@ if BOARD_GOOGLE_STOUT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index a169b88..0c6d642 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -2,7 +2,6 @@ if BOARD_HP_DL145_G1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index be3f009..9885e2b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -2,7 +2,6 @@ if BOARD_HP_DL145_G3 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index b72b8dd..ba8c799 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_HP_DL165_G6_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index e78238c..c5aa340 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -24,7 +24,6 @@ if BOARD_HP_E_VECTRA_P2706T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index d6cdb10..202f831 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -21,7 +21,6 @@ if BOARD_HP_PAVILION_M6_1035DX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 72b916f..8975be2 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -2,7 +2,6 @@ if BOARD_IBASE_MB899 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 0a8442b..d002dce 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -2,7 +2,6 @@ if BOARD_IBM_E325 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 2016ef9..5632c30 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -2,7 +2,6 @@ if BOARD_IBM_E326 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/iei/juki-511p/Kconfig b/src/mainboard/iei/juki-511p/Kconfig index 03dffff..e17d69a 100644 --- a/src/mainboard/iei/juki-511p/Kconfig +++ b/src/mainboard/iei/juki-511p/Kconfig @@ -20,7 +20,6 @@ if BOARD_IEI_JUKI_511P || BOARD_IEI_ROCKY_512 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 62c8671..05abdf6 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_IEI_KINO_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2R2 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/iei/nova4899r/Kconfig b/src/mainboard/iei/nova4899r/Kconfig index 36db67b..8d0a9a4 100644 --- a/src/mainboard/iei/nova4899r/Kconfig +++ b/src/mainboard/iei/nova4899r/Kconfig @@ -20,7 +20,6 @@ if BOARD_IEI_NOVA_4899R config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index 69e106e..74a3c10 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -2,7 +2,6 @@ if BOARD_IEI_PCISA_LX_800_R10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index e443c6c..61c2772 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -23,7 +23,6 @@ if BOARD_IEI_PM_LX_800_R11 config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/iei/pm-lx2-800-r10/Kconfig b/src/mainboard/iei/pm-lx2-800-r10/Kconfig index 1485c94..8e92e69 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/Kconfig +++ b/src/mainboard/iei/pm-lx2-800-r10/Kconfig @@ -23,7 +23,6 @@ if BOARD_IEI_PM_LX2_800_R10 config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/iei/rocky-512/Kconfig b/src/mainboard/iei/rocky-512/Kconfig index 0d6ac38..864da86 100644 --- a/src/mainboard/iei/rocky-512/Kconfig +++ b/src/mainboard/iei/rocky-512/Kconfig @@ -1,7 +1,6 @@ if BOARD_IEI_ROCKY_512 # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 710094e..b52df97 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_BASKING_RIDGE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 61f1c6d..774bbb8 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_COUGAR_CANYON2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_FSP_IVYBRIDGE select SOUTHBRIDGE_INTEL_FSP_BD82X6X diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 91edf33..85b0e6c 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -20,7 +20,6 @@ if BOARD_INTEL_D810E2CB config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_FC_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801BX diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index b676eb6..490aa80 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -20,7 +20,6 @@ if BOARD_INTEL_D945GCLF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GC diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index e74705b..bc0799c 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_EAGLEHEIGHTS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_BGA956 select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 01082d4..77aa910 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_EMERALDLAKE2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 2a62777..6ecbc87 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_JARRELL config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_PXHD diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig index af40cad..4097fa7 100644 --- a/src/mainboard/intel/mtarvon/Kconfig +++ b/src/mainboard/intel/mtarvon/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_MTARVON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig index 5f7de08..5aa4b57 100644 --- a/src/mainboard/intel/truxton/Kconfig +++ b/src/mainboard/intel/truxton/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_TRUXTON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_EP80579 select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 00ea604..6fd3813 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_WTM2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_HASWELL select SOUTHBRIDGE_INTEL_LYNXPOINT diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig index 276b1f7..923d39a 100644 --- a/src/mainboard/intel/xe7501devkit/Kconfig +++ b/src/mainboard/intel/xe7501devkit/Kconfig @@ -2,7 +2,6 @@ if BOARD_INTEL_XE7501DEVKIT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index c6c15d5..e29615e 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -3,7 +3,6 @@ if BOARD_IWAVE_RAINBOW_G6 # TODO: move options to chipset components as appropriate config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_SCH select SOUTHBRIDGE_INTEL_SCH diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index 6ccee76..11b11b9 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -2,7 +2,6 @@ if BOARD_IWILL_DK8_HTX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index d7fefd8..c270f6f 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -2,7 +2,6 @@ if BOARD_IWILL_DK8S2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index bdbeb69..8457944 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -2,7 +2,6 @@ if BOARD_IWILL_DK8X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/jetway/j7f2/Kconfig b/src/mainboard/jetway/j7f2/Kconfig index 811b37e..d2b413b 100644 --- a/src/mainboard/jetway/j7f2/Kconfig +++ b/src/mainboard/jetway/j7f2/Kconfig @@ -2,7 +2,6 @@ if BOARD_JETWAY_J7F2 || BOARD_JETWAY_J7F4K1G2E || BOARD_JETWAY_J7F4K1G5D config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/jetway/j7f4k1g2e/Kconfig b/src/mainboard/jetway/j7f4k1g2e/Kconfig index b46e29e..8c8bbaf 100644 --- a/src/mainboard/jetway/j7f4k1g2e/Kconfig +++ b/src/mainboard/jetway/j7f4k1g2e/Kconfig @@ -1,7 +1,6 @@ if BOARD_JETWAY_J7F4K1G2E # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/jetway/j7f4k1g5d/Kconfig b/src/mainboard/jetway/j7f4k1g5d/Kconfig index edd75f8..d59e703 100644 --- a/src/mainboard/jetway/j7f4k1g5d/Kconfig +++ b/src/mainboard/jetway/j7f4k1g5d/Kconfig @@ -1,7 +1,6 @@ if BOARD_JETWAY_J7F4K1G5D # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index badf590..ca48de3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -22,7 +22,6 @@ if BOARD_JETWAY_NF81_T56N_LF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index 01c4a59..106b610 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -2,7 +2,6 @@ if BOARD_JETWAY_PA78VM5 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2R2 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 29d4da4..f5d4f8c 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -2,7 +2,6 @@ if BOARD_KONTRON_986LCD_M config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index b0b0195..2891736 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -2,7 +2,6 @@ if BOARD_KONTRON_KT690 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index e9d1ce7..96153f7 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -2,7 +2,6 @@ if BOARD_KONTRON_KTQM77 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig index 1a306cf..e042e81 100644 --- a/src/mainboard/lanner/em8510/Kconfig +++ b/src/mainboard/lanner/em8510/Kconfig @@ -2,7 +2,6 @@ if BOARD_LANNER_EM8510 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 701b2ed..99b5849 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 6a743d5..cb2bb39 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_T60 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 860a953..ff9f0ae 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_X201 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select NORTHBRIDGE_INTEL_NEHALEM select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index cd1f761..2ce51a8 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_X230 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..1158046 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_X60 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/linutop/linutop1/Kconfig b/src/mainboard/linutop/linutop1/Kconfig index feb5f78..c8f9a24 100644 --- a/src/mainboard/linutop/linutop1/Kconfig +++ b/src/mainboard/linutop/linutop1/Kconfig @@ -1,7 +1,6 @@ if BOARD_LINUTOP_LINUTOP1 # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index d4beecf..4daaef0 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -21,7 +21,6 @@ if BOARD_LIPPERT_FRONTRUNNER_AF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig index ba1d5f1..fdba7ba 100644 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ b/src/mainboard/lippert/frontrunner/Kconfig @@ -2,7 +2,6 @@ if BOARD_LIPPERT_FRONTRUNNER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 64e1631..4e41bbd 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -2,7 +2,6 @@ if BOARD_LIPPERT_HURRICANE_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index c4684c9..c3aab0e 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -2,7 +2,6 @@ if BOARD_LIPPERT_LITERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index f5ec9b9..051713a 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -2,7 +2,6 @@ if BOARD_LIPPERT_ROADRUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index c4a2ce8..65645fd 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -2,7 +2,6 @@ if BOARD_LIPPERT_SPACERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index d984a08..5a940d3 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -21,7 +21,6 @@ if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index e552982..6228a6e 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -20,7 +20,6 @@ if BOARD_MITAC_6513WU config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/msi/ms6119/Kconfig b/src/mainboard/msi/ms6119/Kconfig index 7705522..00ed0d9 100644 --- a/src/mainboard/msi/ms6119/Kconfig +++ b/src/mainboard/msi/ms6119/Kconfig @@ -20,7 +20,6 @@ if BOARD_MSI_MS_6119 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/msi/ms6147/Kconfig b/src/mainboard/msi/ms6147/Kconfig index 9b51a49..fa4af80 100644 --- a/src/mainboard/msi/ms6147/Kconfig +++ b/src/mainboard/msi/ms6147/Kconfig @@ -20,7 +20,6 @@ if BOARD_MSI_MS_6147 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/msi/ms6156/Kconfig b/src/mainboard/msi/ms6156/Kconfig index 58654f6..840751c 100644 --- a/src/mainboard/msi/ms6156/Kconfig +++ b/src/mainboard/msi/ms6156/Kconfig @@ -20,7 +20,6 @@ if BOARD_MSI_MS_6156 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index 4baee5e..cc70e76 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -20,7 +20,6 @@ if BOARD_MSI_MS_6178 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 76b6625..f2cfd9a 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -2,7 +2,6 @@ if BOARD_MSI_MS7135 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 27bd3e5..c8ff25e 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -2,7 +2,6 @@ if BOARD_MSI_MS7260 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 7823d56..0b0ff1c 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -2,7 +2,6 @@ if BOARD_MSI_MS9185 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index 1359a89..76903e2 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -2,7 +2,6 @@ if BOARD_MSI_MS9282 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 42ceff4..e305551 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_MSI_MS9652_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index 82c2f9d..6fddcc1 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -20,7 +20,6 @@ if BOARD_NEC_POWERMATE_2000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 94de54b..e3d5698 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -2,7 +2,6 @@ if BOARD_NEWISYS_KHEPRI config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig index 58d6d37..bb72688 100644 --- a/src/mainboard/nokia/ip530/Kconfig +++ b/src/mainboard/nokia/ip530/Kconfig @@ -20,7 +20,6 @@ if BOARD_NOKIA_IP530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index e04caaa..4fe3b4d 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -2,7 +2,6 @@ if BOARD_NVIDIA_L1_2PVV config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index fab8710..bbd78a3 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -2,7 +2,6 @@ if BOARD_PCENGINES_ALIX1C config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/pcengines/alix2c/Kconfig b/src/mainboard/pcengines/alix2c/Kconfig index e2ff77c..8bed484 100644 --- a/src/mainboard/pcengines/alix2c/Kconfig +++ b/src/mainboard/pcengines/alix2c/Kconfig @@ -1,7 +1,6 @@ if BOARD_PCENGINES_ALIX2C # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 7ea32c3..a350e11 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -2,7 +2,6 @@ if BOARD_PCENGINES_ALIX2C || BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/pcengines/alix6/Kconfig b/src/mainboard/pcengines/alix6/Kconfig index 4329f19..41b9cf4 100644 --- a/src/mainboard/pcengines/alix6/Kconfig +++ b/src/mainboard/pcengines/alix6/Kconfig @@ -1,7 +1,6 @@ if BOARD_PCENGINES_ALIX6 # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index ecbd2cc..975977f 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -2,7 +2,6 @@ if BOARD_RCA_RM4100 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCBGA479 select NORTHBRIDGE_INTEL_I82830 select SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 365980e..94290d5 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -2,7 +2,6 @@ if BOARD_RODA_RK886EX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945 select NORTHBRIDGE_INTEL_SUBTYPE_I945GM diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 2c1944a..67fc88a 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -2,7 +2,6 @@ if BOARD_RODA_RK9 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_BGA956 select NORTHBRIDGE_INTEL_GM45 select SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 500427a..9c8c466 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -2,7 +2,6 @@ if BOARD_SAMSUNG_LUMPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index e1e0cfa..e38efe0 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -2,7 +2,6 @@ if BOARD_SAMSUNG_STUMPY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index 8d0ff80..dff329f 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -2,7 +2,6 @@ if BOARD_SIEMENS_SITEMP_G1P1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig index 096aa7c..a268bad 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig +++ b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig @@ -20,7 +20,6 @@ if BOARD_SOYO_SY_6BA_PLUS_III config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 80e08c4..f95fc8c 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUNW_ULTRA40 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index bfcb724..62ae51a 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_H8DME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 546dfa5..32f0391 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_H8DMR config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 2f48b32..e1ce4e7 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_H8DMR_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 6371d9e..7b3e830 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -21,7 +21,6 @@ if BOARD_SUPERMICRO_H8QGI config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_G34 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 27172ff..8d91f6f 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_H8QME_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index 86395e4..42e5e1c 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -21,7 +21,6 @@ if BOARD_SUPERMICRO_H8SCM config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_C32 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 87cfc73..de48dba 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_H9SCM_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_C32_NON_AGESA select DIMM_DDR3 select DIMM_REGISTERED diff --git a/src/mainboard/supermicro/x6dai_g/Kconfig b/src/mainboard/supermicro/x6dai_g/Kconfig index 90a800c..4999320 100644 --- a/src/mainboard/supermicro/x6dai_g/Kconfig +++ b/src/mainboard/supermicro/x6dai_g/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_X6DAI_G config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7525 select SOUTHBRIDGE_INTEL_ESB6300 diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig index 03bb0a8..b6001c5 100644 --- a/src/mainboard/supermicro/x6dhe_g/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_X6DHE_G config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_ESB6300 diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig index 397087c..022cbfe 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_X6DHE_G2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig index 0b25fcd..e02b2dd 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_X6DHR_IG config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig index 70df01a..9c8e4a6 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_X6DHR_IG2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 7becacb..f5b0e11 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -2,7 +2,6 @@ if BOARD_SUPERMICRO_X7DB8 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_LGA771 select SOUTHBRIDGE_INTEL_I3100 select NORTHBRIDGE_INTEL_I5000 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index c0aca27..072919d 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -2,7 +2,6 @@ if BOARD_TECHNEXION_TIM5690 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 890b7ac..4e0b25a 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -2,7 +2,6 @@ if BOARD_TECHNEXION_TIM8690 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_S1G1 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_RS690 diff --git a/src/mainboard/technologic/ts5300/Kconfig b/src/mainboard/technologic/ts5300/Kconfig index 8def16d..0006fd7 100644 --- a/src/mainboard/technologic/ts5300/Kconfig +++ b/src/mainboard/technologic/ts5300/Kconfig @@ -2,7 +2,6 @@ if BOARD_TECHNOLOGIC_TS5300 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SC520 select ROMCC select HAVE_OPTION_TABLE diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig index ab41e5b..6d77f59 100644 --- a/src/mainboard/televideo/tc7020/Kconfig +++ b/src/mainboard/televideo/tc7020/Kconfig @@ -20,7 +20,6 @@ if BOARD_TELEVIDEO_TC7020 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index b1988dd..971c41c 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -2,7 +2,6 @@ if BOARD_THOMSON_IP1000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MFCBGA479 select NORTHBRIDGE_INTEL_I82830 select SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index c842a5d..7dd0edc 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -21,7 +21,6 @@ if BOARD_TI_BEAGLEBONE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_ARMV7 select CPU_TI_AM335X select BOARD_ROMSIZE_KB_4096 diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 3139d7d..945ab09 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -2,7 +2,6 @@ if BOARD_TRAVERSE_GEOS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/tyan/s1846/Kconfig b/src/mainboard/tyan/s1846/Kconfig index b4e6c92..e491d3f 100644 --- a/src/mainboard/tyan/s1846/Kconfig +++ b/src/mainboard/tyan/s1846/Kconfig @@ -20,7 +20,6 @@ if BOARD_TYAN_S1846 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index f908908..a13db8b 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2735 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index 88ab969..e6e3df2 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2850 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 8e77709..30aa01e 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2875 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8151 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index c6fed4b..5186337 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2880 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index fcc93f3..6c759e1 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2881 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 0a0909a..646b5a8 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2882 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index aab6732..86e43f8 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2885 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index ddd7ed0..85206df 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2891 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index ddf2901..a550942 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2892 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 0201eb4..c8510aa 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2895 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 731cc5c..84be620 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2912 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index a7f9954..e13d7c4 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S2912_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index 449aa39..d4feacb 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S4880 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index ec1f7a9..2bd3854 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -2,7 +2,6 @@ if BOARD_TYAN_S4882 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 68ce152..7b46bc1 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -21,7 +21,6 @@ if BOARD_TYAN_S8226 config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 select CPU_AMD_AGESA_FAMILY15 select CPU_AMD_SOCKET_C32 select NORTHBRIDGE_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig index e7920e7..266e7e9 100644 --- a/src/mainboard/via/epia-cn/Kconfig +++ b/src/mainboard/via/epia-cn/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_EPIA_CN config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/via/epia-m/Kconfig b/src/mainboard/via/epia-m/Kconfig index 3e8a93d..f05c99c 100644 --- a/src/mainboard/via/epia-m/Kconfig +++ b/src/mainboard/via/epia-m/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_EPIA_M || BOARD_VIA_EPIA_MII || BOARD_VIA_EPIA_ML config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C3 select NORTHBRIDGE_VIA_VT8623 select SOUTHBRIDGE_VIA_VT8235 diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig index fcadabc..c64f8d2 100644 --- a/src/mainboard/via/epia-m700/Kconfig +++ b/src/mainboard/via/epia-m700/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_EPIA_M700 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_VX800 select SUPERIO_WINBOND_W83697HF diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig index 01ef032..65fd478 100644 --- a/src/mainboard/via/epia-m850/Kconfig +++ b/src/mainboard/via/epia-m850/Kconfig @@ -21,7 +21,6 @@ if BOARD_VIA_EPIA_M850 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_NANO select NORTHBRIDGE_VIA_VX900 select SUPERIO_FINTEK_F81865F diff --git a/src/mainboard/via/epia-mii/Kconfig b/src/mainboard/via/epia-mii/Kconfig index 6106ad2..ff31b93 100644 --- a/src/mainboard/via/epia-mii/Kconfig +++ b/src/mainboard/via/epia-mii/Kconfig @@ -1,7 +1,6 @@ if BOARD_VIA_EPIA_MII # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/via/epia-ml/Kconfig b/src/mainboard/via/epia-ml/Kconfig index 54eac0d..5e7b6ab 100644 --- a/src/mainboard/via/epia-ml/Kconfig +++ b/src/mainboard/via/epia-ml/Kconfig @@ -1,7 +1,6 @@ if BOARD_VIA_EPIA_ML # Dummy for abuild -#select ARCH_X86 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 2b327b7..3ea6878 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_EPIA_N config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C3 select NORTHBRIDGE_VIA_CN400 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/via/epia/Kconfig b/src/mainboard/via/epia/Kconfig index 60ce4f5..7ee1ed8 100644 --- a/src/mainboard/via/epia/Kconfig +++ b/src/mainboard/via/epia/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_EPIA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C3 select NORTHBRIDGE_VIA_VT8601 select SOUTHBRIDGE_VIA_VT8231 diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig index 70aa8d7..97f2088 100644 --- a/src/mainboard/via/pc2500e/Kconfig +++ b/src/mainboard/via/pc2500e/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_PC2500E config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index 14eebe6..da71c87 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -2,7 +2,6 @@ if BOARD_VIA_VT8454C config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_VIA_C7 select NORTHBRIDGE_VIA_CX700 select SUPERIO_VIA_VT1211 diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 507340c..ee34d1a 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -2,7 +2,6 @@ if BOARD_WINENT_MB6047 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig index 7db7de5..3a36f29 100644 --- a/src/mainboard/winent/pl6064/Kconfig +++ b/src/mainboard/winent/pl6064/Kconfig @@ -2,7 +2,6 @@ if BOARD_WINENT_PL6064 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig index d8d2628..fbb5246 100644 --- a/src/mainboard/wyse/s50/Kconfig +++ b/src/mainboard/wyse/s50/Kconfig @@ -20,7 +20,6 @@ if BOARD_WYSE_S50 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/soc/Kconfig b/src/soc/Kconfig index ac29205..823d76c 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,3 +1 @@ -if ARCH_X86 source src/soc/intel/Kconfig -endif diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 2360b36..1b3ee05 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,6 +8,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y + select ARCH_X86 select CACHE_MRC_SETTINGS select CAR_MIGRATION select COLLECT_TIMESTAMPS diff --git a/util/abuild/abuild b/util/abuild/abuild index a5a57c9..ebb3415 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -306,58 +306,6 @@ function build_target mkdir -p $TOP/$TARGET/${VENDOR}_${MAINBOARD} $TOP/$TARGET/abuild XMLFILE=$TOP/$TARGET/abuild/${VENDOR}_${MAINBOARD}.xml - if [ "$ARCH" = "$TARCH" -o $found_crosscompiler = true ]; then - printf "$TARCH: ok$CROSS_TEXT\n" - else - # FIXME this is basically the same as above. - found_crosscompiler=false - if [ "$ARCH" == amd64 -a "$TARCH" == i386 ]; then - CC="gcc -m32" - found_crosscompiler=true - fi - if [ "$ARCH" == ppc64 -a "$TARCH" == ppc ]; then - CC="gcc -m32" - found_crosscompiler=true - fi - if [ "$found_crosscompiler" == "false" -a "$TARCH" == ppc ];then - for prefix in powerpc-eabi- powerpc-linux- ppc_74xx- \ - powerpc-7450-linux-gnu- powerpc-elf-; do - if ${prefix}gcc --version > /dev/null 2> /dev/null ; then - found_crosscompiler=true - CROSS_COMPILE=$prefix - fi - done - fi - if [ "$found_crosscompiler" == "false" -a "$TARCH" == ARMV7 ];then - for prefix in armv7a-eabi- armv7-a-eabi- armv7a-cros-linux-gnueabi-; do - if ${prefix}gcc --version > /dev/null 2> /dev/null ; then - found_crosscompiler=true - CROSS_COMPILE=$prefix - fi - done - fi - - # TBD: look for suitable cross compiler suite - # cross-$TARCH-gcc and cross-$TARCH-ld - - # Check result: - if [ $found_crosscompiler == "false" ]; then - printf "$TARCH: skipped, we're $ARCH\n\n" - junit "<testcase classname='board' name='$TARCH/$VENDOR/$MAINBOARD' >" - junit " <failure type='NoCrossCompiler'>No cross-compiler for $TARCH found</failure>" - junit "</testcase>" - - return 0 - else - printf "$TARCH: ok, $ARCH using ${CROSS_COMPILE}gcc\n" - fi - fi - - CC=${CROSS_COMPILE}$CC - - if [ "$stackprotect" = "true" ]; then - CC="$CC -fno-stack-protector" - fi stime=`perl -e 'print time();' 2>/dev/null || date +%s` create_buildenv $VENDOR $MAINBOARD $CONFIG

1 0

New patch to review for coreboot: 769852a superio/ite/it8673f: Remove poor implementation
by Edward O'Callaghan 22 Apr '14

22 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5568 -gerrit commit 769852a9e9a6e8c7159badbf7313434c140676af Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 04:21:53 2014 +1000 superio/ite/it8673f: Remove poor implementation Following the reasoning of: HASH superio/ite/it8705f: Remove poor implementation Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/Kconfig | 2 - src/superio/ite/Makefile.inc | 1 - src/superio/ite/it8673f/Makefile.inc | 22 --------- src/superio/ite/it8673f/chip.h | 32 ------------ src/superio/ite/it8673f/early_serial.c | 90 ---------------------------------- src/superio/ite/it8673f/it8673f.h | 34 ------------- src/superio/ite/it8673f/superio.c | 74 ---------------------------- 7 files changed, 255 deletions(-) diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index a8ce104..4c0f927 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -22,8 +22,6 @@ config SUPERIO_ITE_IT8661F bool config SUPERIO_ITE_IT8671F bool -config SUPERIO_ITE_IT8673F - bool config SUPERIO_ITE_IT8712F bool config SUPERIO_ITE_IT8716F diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 28cf81c..2b71521 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -19,7 +19,6 @@ subdirs-y += it8661f subdirs-y += it8671f -subdirs-y += it8673f subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f diff --git a/src/superio/ite/it8673f/Makefile.inc b/src/superio/ite/it8673f/Makefile.inc deleted file mode 100644 index 10c2f7f..0000000 --- a/src/superio/ite/it8673f/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ramstage-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.c - diff --git a/src/superio/ite/it8673f/chip.h b/src/superio/ite/it8673f/chip.h deleted file mode 100644 index c5fd8de..0000000 --- a/src/superio/ite/it8673f/chip.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8673F_CHIP_H -#define SUPERIO_ITE_IT8673F_CHIP_H - -#include <device/device.h> -#include <pc80/keyboard.h> - -struct superio_ite_it8673f_config { - - struct pc_keyboard keyboard; -}; - -#endif diff --git a/src/superio/ite/it8673f/early_serial.c b/src/superio/ite/it8673f/early_serial.c deleted file mode 100644 index 987b5e6..0000000 --- a/src/superio/ite/it8673f/early_serial.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8673f.h" - -/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8673F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ - -#define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */ - -/* - * Special values used for entering MB PnP mode. The first four bytes of - * each line determine the address port, the last four are data. - */ -static const u8 init_values[] = { - 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, - 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, - 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, - 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, -}; - -static void it8673f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8673F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the serial port(s). */ -static void it8673f_enable_serial(device_t dev, u16 iobase) -{ - int i; - - /* (1) Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ - /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ - /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ - /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ - outb(0x86, IT8673F_CONFIGURATION_PORT); - outb(0x80, IT8673F_CONFIGURATION_PORT); - outb(0x55, IT8673F_CONFIGURATION_PORT); - outb(0x55, IT8673F_CONFIGURATION_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], SIO_BASE); - - /* (2) Modify the data of configuration registers. */ - - /* Enable all devices. */ - it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Select 24MHz CLKIN (clear bit 0). */ - it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); - - /* Clear software suspend mode (clear bit 0). */ - it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00); - - /* (3) Exit the configuration state (MB PnP mode). */ - it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); -} diff --git a/src/superio/ite/it8673f/it8673f.h b/src/superio/ite/it8673f/it8673f.h deleted file mode 100644 index b683a31..0000000 --- a/src/superio/ite/it8673f/it8673f.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8673F_IT8673F_H -#define SUPERIO_ITE_IT8673F_IT8673F_H - -/* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */ - -#define IT8673F_FDC 0x00 /* Floppy */ -#define IT8673F_SP1 0x01 /* Com1 */ -#define IT8673F_SP2 0x02 /* Com2 */ -#define IT8673F_PP 0x03 /* Parallel port */ -#define IT8673F_FAN 0x04 /* Fan controller */ -#define IT8673F_KBCK 0x05 /* PS/2 keyboard */ -#define IT8673F_KBCM 0x06 /* PS/2 mouse */ - -#endif diff --git a/src/superio/ite/it8673f/superio.c b/src/superio/ite/it8673f/superio.c deleted file mode 100644 index baa1ae1..0000000 --- a/src/superio/ite/it8673f/superio.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <pc80/keyboard.h> -#include <stdlib.h> -#include "chip.h" -#include "it8673f.h" - -static void init(device_t dev) -{ - struct superio_ite_it8673f_config *conf = dev->chip_info; - - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case IT8673F_FDC: /* TODO. */ - break; - case IT8673F_PP: /* TODO. */ - break; - case IT8673F_FAN: /* TODO. */ - break; - case IT8673F_KBCK: - pc_keyboard_init(&conf->keyboard); - break; - case IT8673F_KBCM: /* TODO. */ - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -/* TODO: FDC, PP, FAN, KBCM. */ -static struct pnp_info pnp_dev_info[] = { - { &ops, IT8673F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, IT8673F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, - { &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8673f_ops = { - CHIP_NAME("ITE IT8673F Super I/O") - .enable_dev = enable_dev, -};

1 0

New patch to review for coreboot: eb79e08 superio/ite/it8705f: Remove poor implementation
by Edward O'Callaghan 22 Apr '14

22 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5566 -gerrit commit eb79e08bdf16e4b847e5c97f1a11ba232437e7f4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 04:00:38 2014 +1000 superio/ite/it8705f: Remove poor implementation This super io support is poorly implemented and would not work for all boards since it hardcodes values. Since there are no users of it, remove for now pending a fresh reimplementation from scratch. Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/Kconfig | 2 - src/superio/ite/Makefile.inc | 1 - src/superio/ite/it8705f/Makefile.inc | 22 --------- src/superio/ite/it8705f/early_serial.c | 82 ---------------------------------- src/superio/ite/it8705f/it8705f.h | 38 ---------------- src/superio/ite/it8705f/superio.c | 72 ----------------------------- 6 files changed, 217 deletions(-) diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index 0cf112f..a8ce104 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -24,8 +24,6 @@ config SUPERIO_ITE_IT8671F bool config SUPERIO_ITE_IT8673F bool -config SUPERIO_ITE_IT8705F - bool config SUPERIO_ITE_IT8712F bool config SUPERIO_ITE_IT8716F diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 8610eea..28cf81c 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -20,7 +20,6 @@ subdirs-y += it8661f subdirs-y += it8671f subdirs-y += it8673f -subdirs-y += it8705f subdirs-y += it8712f subdirs-y += it8716f subdirs-y += it8718f diff --git a/src/superio/ite/it8705f/Makefile.inc b/src/superio/ite/it8705f/Makefile.inc deleted file mode 100644 index a2acd33..0000000 --- a/src/superio/ite/it8705f/Makefile.inc +++ /dev/null @@ -1,22 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ramstage-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.c - diff --git a/src/superio/ite/it8705f/early_serial.c b/src/superio/ite/it8705f/early_serial.c deleted file mode 100644 index ccc92c2..0000000 --- a/src/superio/ite/it8705f/early_serial.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8705f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ - -/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */ -#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */ -#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */ - -#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -static void it8705f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8705F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the serial port(s). */ -static void it8705f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8705F_CONFIGURATION_PORT); - outb(0x01, IT8705F_CONFIGURATION_PORT); - outb(0x55, IT8705F_CONFIGURATION_PORT); - outb(0x55, IT8705F_CONFIGURATION_PORT); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Select 24MHz CLKIN (set bit 0). */ - it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); -} diff --git a/src/superio/ite/it8705f/it8705f.h b/src/superio/ite/it8705f/it8705f.h deleted file mode 100644 index 2a05ace..0000000 --- a/src/superio/ite/it8705f/it8705f.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_ITE_IT8705F_IT8705F_H -#define SUPERIO_ITE_IT8705F_IT8705F_H - -/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */ - -/* Note: This should also work on an IT8705AF, they're almost the same. */ - -#define IT8705F_FDC 0x00 /* Floppy */ -#define IT8705F_SP1 0x01 /* Com1 */ -#define IT8705F_SP2 0x02 /* Com2 */ -#define IT8705F_PP 0x03 /* Parallel port */ -#define IT8705F_EC 0x04 /* Environment controller */ -#define IT8705F_GPIO 0x05 /* GPIO */ -#define IT8705F_GAME 0x06 /* GAME port */ -#define IT8705F_IR 0x07 /* Consumer IR */ -#define IT8705F_MIDI 0x08 /* MIDI port */ - -#endif diff --git a/src/superio/ite/it8705f/superio.c b/src/superio/ite/it8705f/superio.c deleted file mode 100644 index 0df7f2d..0000000 --- a/src/superio/ite/it8705f/superio.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pnp.h> -#include <stdlib.h> -#include "it8705f.h" - -static void init(device_t dev) -{ - if (!dev->enabled) - return; - - switch (dev->path.pnp.device) { - case IT8705F_FDC: /* TODO. */ - break; - case IT8705F_PP: /* TODO. */ - break; - case IT8705F_EC: /* TODO. */ - break; - case IT8705F_GPIO: /* TODO. */ - break; - case IT8705F_GAME: /* TODO. */ - break; - case IT8705F_IR: /* TODO. */ - break; - case IT8705F_MIDI: /* TODO. */ - break; - } -} - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, -}; - -/* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */ -static struct pnp_info pnp_dev_info[] = { - { &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_ite_it8705f_ops = { - CHIP_NAME("ITE IT8705F Super I/O") - .enable_dev = enable_dev, -};

1 0

Patch set updated for coreboot: 0bb5e3e superio/ite/it8716f: Rewrite from hardcoded base addr
by Edward O'Callaghan 22 Apr '14

22 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5565 -gerrit commit 0bb5e3eefe76495761e3d20829bb70ce55705dcb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 01:43:38 2014 +1000 superio/ite/it8716f: Rewrite from hardcoded base addr Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2n-e/romstage.c | 11 +++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 10 +++---- src/mainboard/gigabyte/m57sli/romstage.c | 11 ++++--- src/mainboard/via/pc2500e/romstage.c | 2 +- src/superio/ite/it8716f/Makefile.inc | 2 +- src/superio/ite/it8716f/chip.h | 3 +- src/superio/ite/it8716f/early_init.c | 37 ------------------------ src/superio/ite/it8716f/early_serial.c | 41 +++++++++++++++++++-------- src/superio/ite/it8716f/it8716f.h | 21 ++++++++------ 9 files changed, 59 insertions(+), 79 deletions(-) diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..6892b28 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,14 +37,14 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -104,11 +104,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */ - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..86158c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,14 +38,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +125,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..44dda27 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,15 +35,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -106,7 +105,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; - uint8_t tmp = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ @@ -118,6 +116,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); +#if 0 + uint8_t tmp = 0; pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); @@ -132,6 +132,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); +#endif + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0728154..e374cf9 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,7 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/ite/it8716f/early_serial.c" +#include <superio/ite/it8716f/it8716f.h> #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 5a67656..6b3c0ce 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c - diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h index 33a265a..afdcd96 100644 --- a/src/superio/ite/it8716f/chip.h +++ b/src/superio/ite/it8716f/chip.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_CHIP_H #define SUPERIO_ITE_IT8716F_CHIP_H -#include <device/device.h> #include <pc80/keyboard.h> struct superio_ite_it8716f_config { @@ -29,4 +28,4 @@ struct superio_ite_it8716f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_ITE_IT8716F_CHIP_H */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c deleted file mode 100644 index cfac2a9..0000000 --- a/src/superio/ite/it8716f/early_init.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8716f.h" - -void it8716f_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void it8716f_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 02f0304..2085a8f 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -2,9 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +21,9 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8716f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -36,7 +31,7 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void it8716f_enter_conf(device_t dev) { u16 port = dev >> 8; @@ -46,17 +41,39 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void it8716f_exit_conf(device_t dev) { pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); } +static void it8716f_reg_write(device_t dev, u8 index, u8 value) +{ + it8716f_enter_conf(dev); + pnp_write_config(dev, index, value); + it8716f_exit_conf(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) + * and pass: CLKIN_DEV + * IT8716F_UART_CLK_PREDIVIDE_24 + * IT8716F_UART_CLK_PREDIVIDE_48 (default) + */ +void it8716f_conf_clkin(device_t dev, u8 predivide) +{ + it8716f_reg_write(dev, IT8716F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + + +/* Enable the serial port(s). */ void it8716f_enable_serial(device_t dev, u16 iobase) { - pnp_enter_ext_func_mode(dev); + it8716f_enter_conf(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + it8716f_exit_conf(dev); } diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 6657db4..37b8b65 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -18,8 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8716F_IT8716F_H -#define SUPERIO_ITE_IT8716F_IT8716F_H +#ifndef SUPERIO_ITE_IT8716F_H +#define SUPERIO_ITE_IT8716F_H + +#include <device/pnp.h> +#include <stdint.h> /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ @@ -36,15 +39,15 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ +#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8716F_UART_CLK_PREDIVIDE_24 0x01 + +void it8716f_conf_clkin(device_t dev, u8 predivide); +void it8716f_enable_serial(device_t dev, u16 iobase); + #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) -void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, u16 iobase); -void it8716f_enable_serial(device_t dev, u16 iobase); -#endif - -#endif +#endif /* SUPERIO_ITE_IT8716F_H */

1 0

← Newer
1
...
20
21
22
23
24
25
26
...
78
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2014