coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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779 discussions

New patch to review for coreboot: ecbaa0f drivers/pc80/Kconfig: Do not initialize PS/2 keyboard with GRUB 2 payload
by Paul Menzel 26 Apr '14

26 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5583 -gerrit commit ecbaa0f0af0785ffda08697067e71cd980151e0b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 26 10:28:19 2014 +0200 drivers/pc80/Kconfig: Do not initialize PS/2 keyboard with GRUB 2 payload Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/pc80/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 37ba6bc..485dd64 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -2,8 +2,8 @@ # reliably support PS/2 init themselves. config DRIVERS_PS2_KEYBOARD bool "PS/2 keyboard init" - default n if PAYLOAD_SEABIOS - default y if !PAYLOAD_SEABIOS + default n if PAYLOAD_GRUB2 || PAYLOAD_SEABIOS + default y if !(PAYLOAD_GRUB2 || PAYLOAD_SEABIOS) help Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

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New patch to review for coreboot: 7ad328b drivers/pc80/Kconfig: Add GRUB 2 to list of payloads not needing PS/2 keyboard inits
by Paul Menzel 26 Apr '14

26 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5582 -gerrit commit 7ad328bbf83db6352b5db04b0c696042cd90cc53 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 26 10:22:43 2014 +0200 drivers/pc80/Kconfig: Add GRUB 2 to list of payloads not needing PS/2 keyboard inits Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/pc80/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index acd1503..37ba6bc 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -9,7 +9,7 @@ config DRIVERS_PS2_KEYBOARD to the PS/2 port. Some payloads (eg, filo) require this option. Other payloads - (eg, SeaBIOS, Linux) do not require it. + (eg, GRUB 2, SeaBIOS, Linux) do not require it. Initializing a PS/2 keyboard can take several hundred milliseconds. If you know you will only use a payload which does not require

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New patch to review for coreboot: f1e271b drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is used as payload
by Paul Menzel 26 Apr '14

26 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5581 -gerrit commit f1e271be20f465546e1e971c722b0e6ebb02eb88 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 26 10:18:12 2014 +0200 drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is used as payload As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is able to initialize the PS/2 keyboard itself, so it is not necessary to do it in coreboot. SeaBIOS is also able to do it faster as discussed in a thread from October 2010 [1]. [1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310 [coreboot] coreboot+seabios timings Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/pc80/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 3c8fd8c..acd1503 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -2,7 +2,8 @@ # reliably support PS/2 init themselves. config DRIVERS_PS2_KEYBOARD bool "PS/2 keyboard init" - default y + default n if PAYLOAD_SEABIOS + default y if !PAYLOAD_SEABIOS help Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

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Patch set updated for coreboot: 1f379b6 superio/fintek/f71869ad: Make hwm devicetree configurable
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5580 -gerrit commit 1f379b60b1f6f8f8610a389cbc2c90c78d0a067a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Apr 26 15:21:45 2014 +1000 superio/fintek/f71869ad: Make hwm devicetree configurable NOTFORMERGE Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 17 +++++ src/superio/fintek/f71869ad/Makefile.inc | 1 + src/superio/fintek/f71869ad/chip.h | 15 ++++ src/superio/fintek/f71869ad/f71869ad_hwm.c | 99 +++++++++++++++++++++++++ src/superio/fintek/f71869ad/fintek_internal.h | 1 + src/superio/fintek/f71869ad/superio.c | 1 + 6 files changed, 134 insertions(+) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 18722de..f09c146 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -61,6 +61,23 @@ chip northbridge/amd/agesa/family14/root_complex register "multi_function_register_3" = "0x24" register "multi_function_register_4" = "0x00" register "multi_function_register_5" = "0x60" +# +# HWM configuration registers + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_seg4_speed_count" = "0x00" + register "hwm_fan1_seg5_speed_count" = "0x00" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_smb_command_byte" = "0x01" + register "hwm_smb_status" = "0x01" + register "hwm_smb_protocal_sel" = "0x82" +# # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 35e596d..7ee2501 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -20,4 +20,5 @@ romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_hwm.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5011383..223ec63 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -33,6 +33,21 @@ struct superio_fintek_f71869ad_config { uint8_t multi_function_register_3; uint8_t multi_function_register_4; uint8_t multi_function_register_5; + /* HWM configuration registers */ + uint8_t hwm_smbus_control_reg; + uint8_t hwm_fan_type_sel_reg; + uint8_t hwm_fan1_temp_adj_rate_reg; + uint8_t hwm_fan_mode_sel_reg; + uint8_t hwm_fan1_idx_rpm_mode; + uint8_t hwm_fan1_seg1_speed_count; + uint8_t hwm_fan1_seg2_speed_count; + uint8_t hwm_fan1_seg3_speed_count; + uint8_t hwm_fan1_seg4_speed_count; + uint8_t hwm_fan1_seg5_speed_count; + uint8_t hwm_fan1_temp_map_sel; + uint8_t hwm_smb_command_byte; + uint8_t hwm_smb_status; + uint8_t hwm_smb_protocal_sel; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c new file mode 100644 index 0000000..81e5c01 --- /dev/null +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +/* + * The Fintek F71869AD Super I/O Hardware Monitor permits the configuration of + * three fans individually, where fan1 is typically taken as the CPU fan. Each + * fan is controlled by the relation: + * + * Tfan? = Tnow + (Ta - Tb)*Ct + * + * Parameters in this relation are specified in the devicetree.cb. + */ + +/* + * Register CR01 ~ CR03 -> Configuration Registers + * Register CR0A ~ CR0F -> PECI/TSI Control Register + * Register CR10 ~ CR37 -> Voltage Setting Register + * Register CR40 ~ CR4E -> PECI 3.0 Command and Register + * Register CR60 ~ CR8E -> Temperature Setting Register + * Register CR90 ~ CRDF -> Fan Control Setting Register + */ +#define HWM_SMBUS_CONTROL_REG 0x0A +#define HWM_FAN_TYPE_SEL_REG 0x94 +#define HWM_FAN1_TEMP_ADJ_RATE_REG 0x95 +#define HWM_FAN_MODE_SEL_REG 0x96 +#define HWM_FAN_FAULT_TIME_REG 0x9F /* bit7 FAN_PROG_SEL */ +#define HWM_FAN1_IDX_RPM_MODE 0xA3 +#define HWM_FAN1_SEG1_SPEED_COUNT 0xAA +#define HWM_FAN1_SEG2_SPEED_COUNT 0xAB +#define HWM_FAN1_SEG3_SPEED_COUNT 0xAC +#define HWM_FAN1_SEG4_SPEED_COUNT 0xAD +#define HWM_FAN1_SEG5_SPEED_COUNT 0xAE +#define HWM_FAN1_TEMP_MAP_SEL 0xAF +#define HWM_SMB_COMMAND_BYTE 0xED +#define HWM_SMB_STATUS 0xEE /* bit6 TSI_CMD_PROG */ +#define HWM_SMB_PROTOCAL_SEL 0xEF + +void f71869ad_hwm_init(device_t dev) +{ + struct superio_fintek_f71869ad_config *conf = dev->chip_info; + + pnp_enable_resources(dev); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + pnp_write_config(dev, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg); + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + pnp_write_config(dev, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel); + /* set FAN_PROG_SEL = 1 */ + pnp_write_config(dev, HWM_FAN_FAULT_TIME_REG, 0x8a); + /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + pnp_write_config(dev, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg); + /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + pnp_write_config(dev, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg); + /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = + 1, p.88 */ + pnp_write_config(dev, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg); + /* set FAN_PROG_SEL = 0 */ + pnp_write_config(dev, HWM_FAN_FAULT_TIME_REG, 0x0a); + /* FAN1 RPM mode p.70 */ + pnp_write_config(dev, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode); + /* FAN1 Segment X Speed Count */ + pnp_write_config(dev, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG4_SPEED_COUNT, conf->hwm_fan1_seg4_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG5_SPEED_COUNT, conf->hwm_fan1_seg5_speed_count); + /* .. */ + pnp_write_config(dev, HWM_SMB_COMMAND_BYTE, conf->hwm_smb_command_byte); + pnp_write_config(dev, HWM_SMB_STATUS, conf->hwm_smb_status); + pnp_write_config(dev, HWM_SMB_PROTOCAL_SEL, conf->hwm_smb_protocal_sel); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 86f5669..6856c01 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -25,5 +25,6 @@ #include <device/pnp.h> void f71869ad_multifunc_init(device_t dev); +void f71869ad_hwm_init(device_t dev); #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 770a712..cc690ec 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -43,6 +43,7 @@ static void f71869ad_init(device_t dev) break; case F71869AD_HWM: f71869ad_multifunc_init(dev); + f71869ad_hwm_init(dev); break; } }

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Patch set updated for coreboot: b00558d uart8250io: Fix build with DEBUG_SMI
by Kyösti Mälkki 26 Apr '14

26 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5574 -gerrit commit b00558dff5bc02ba1db4448a594698ecbabd5a0d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 23 10:28:59 2014 +0300 uart8250io: Fix build with DEBUG_SMI Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/uart8250io.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e1fb39b..b2f234b 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <rules.h> #include <arch/io.h> #include <console/uart.h> #include <trace.h> @@ -134,7 +135,7 @@ void uart_tx_flush(void) uart8250_tx_flush(bases[0]); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial;

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New patch to review for coreboot: bc4c48f superio/fintek/f71869ad: Make hwm devicetree configurable
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5580 -gerrit commit bc4c48fc2257442ded5a3e591f3cbc0c69c6921b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Apr 26 15:21:45 2014 +1000 superio/fintek/f71869ad: Make hwm devicetree configurable NOTFORMERGE Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 17 +++++ src/superio/fintek/f71869ad/chip.h | 15 ++++ src/superio/fintek/f71869ad/f71869ad_hwm.c | 99 +++++++++++++++++++++++++ src/superio/fintek/f71869ad/fintek_internal.h | 1 + src/superio/fintek/f71869ad/superio.c | 1 + 5 files changed, 133 insertions(+) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 18722de..f09c146 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -61,6 +61,23 @@ chip northbridge/amd/agesa/family14/root_complex register "multi_function_register_3" = "0x24" register "multi_function_register_4" = "0x00" register "multi_function_register_5" = "0x60" +# +# HWM configuration registers + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_seg4_speed_count" = "0x00" + register "hwm_fan1_seg5_speed_count" = "0x00" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_smb_command_byte" = "0x01" + register "hwm_smb_status" = "0x01" + register "hwm_smb_protocal_sel" = "0x82" +# # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5011383..223ec63 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -33,6 +33,21 @@ struct superio_fintek_f71869ad_config { uint8_t multi_function_register_3; uint8_t multi_function_register_4; uint8_t multi_function_register_5; + /* HWM configuration registers */ + uint8_t hwm_smbus_control_reg; + uint8_t hwm_fan_type_sel_reg; + uint8_t hwm_fan1_temp_adj_rate_reg; + uint8_t hwm_fan_mode_sel_reg; + uint8_t hwm_fan1_idx_rpm_mode; + uint8_t hwm_fan1_seg1_speed_count; + uint8_t hwm_fan1_seg2_speed_count; + uint8_t hwm_fan1_seg3_speed_count; + uint8_t hwm_fan1_seg4_speed_count; + uint8_t hwm_fan1_seg5_speed_count; + uint8_t hwm_fan1_temp_map_sel; + uint8_t hwm_smb_command_byte; + uint8_t hwm_smb_status; + uint8_t hwm_smb_protocal_sel; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c new file mode 100644 index 0000000..3848392 --- /dev/null +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +/* + * The Fintek F71869AD Super I/O Hardware Monitor permits the configuration of + * three fans individually, where fan1 is typically taken as the CPU fan. Each + * fan is controlled by the relation: + * + * Tfan? = Tnow + (Ta - Tb)*Ct + * + * Parameters in this relation are specified in the devicetree.cb. + */ + +/* + * Register CR01 ~ CR03 -> Configuration Registers + * Register CR0A ~ CR0F -> PECI/TSI Control Register + * Register CR10 ~ CR37 -> Voltage Setting Register + * Register CR40 ~ CR4E -> PECI 3.0 Command and Register + * Register CR60 ~ CR8E -> Temperature Setting Register + * Register CR90 ~ CRDF -> Fan Control Setting Register + */ +#define HWM_SMBUS_CONTROL_REG 0x0A +#define HWM_FAN_TYPE_SEL_REG 0x94 +#define HWM_FAN1_TEMP_ADJ_RATE_REG 0x95 +#define HWM_FAN_MODE_SEL_REG 0x96 +#define HWM_FAN_FAULT_TIME_REG 0x9F /* bit7 FAN_PROG_SEL */ +#define HWM_FAN1_IDX_RPM_MODE 0xA3 +#define HWM_FAN1_SEG1_SPEED_COUNT 0xAA +#define HWM_FAN1_SEG2_SPEED_COUNT 0xAB +#define HWM_FAN1_SEG3_SPEED_COUNT 0xAC +#define HWM_FAN1_SEG4_SPEED_COUNT 0xAD +#define HWM_FAN1_SEG5_SPEED_COUNT 0xAE +#define HWM_FAN1_TEMP_MAP_SEL 0xAF +#define HWM_SMB_COMMAND_BYTE 0xED +#define HWM_SMB_STATUS 0xEE /* bit6 TSI_CMD_PROG */ +#define HWM_SMB_PROTOCAL_SEL 0xEF + +void f71869ad_hwm_init(device_t dev) +{ + struct superio_fintek_f71869ad_config *conf = dev->chip_info; + + pnp_enable_resources(dev); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + pnp_write_config(dev, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg); + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + pnp_write_config(dev, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel); + /* set FAN_PROG_SEL = 1 */ + pnp_write_config(dev, HWM_FAN_FAULT_TIME_REG, 0x8a); + /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + pnp_write_config(dev, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg); + /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + pnp_write_config(dev, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg); + /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = + 1, p.88 */ + pnp_write_config(dev, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg); + /* set FAN_PROG_SEL = 0 */ + pnp_write_config(dev, HWM_FAN_FAULT_TIME_REG, 0x0a); + /* FAN1 RPM mode p.70 */ + pnp_write_config(dev, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode); + /* FAN1 Segment X Speed Count */ + pnp_write_config(dev, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG4_SPEED_COUNT, conf->hwm_fan1_seg4_speed_count); + pnp_write_config(dev, HWM_FAN1_SEG5_SPEED_COUNT, conf->hwm_fan1_seg5_speed_count); + /* .. */ + pnp_write_config(dev, HWM_SMBUS_COMMAND_BYTE, conf->hwm_smb_command_byte); + pnp_write_config(dev, HWM_SMBUS_STATUS, conf->hwm_smb_status); + pnp_write_config(dev, HWM_SMBUS_PROTOCAL_REL, conf->hwm_smb_protocal_sel); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 86f5669..6856c01 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -25,5 +25,6 @@ #include <device/pnp.h> void f71869ad_multifunc_init(device_t dev); +void f71869ad_hwm_init(device_t dev); #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 770a712..cc690ec 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -43,6 +43,7 @@ static void f71869ad_init(device_t dev) break; case F71869AD_HWM: f71869ad_multifunc_init(dev); + f71869ad_hwm_init(dev); break; } }

1 0

New patch to review for coreboot: 25e2aca Clean arch-level Kconfig files
by Furquan Shaikh 25 Apr '14

25 Apr '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5579 -gerrit commit 25e2acabf171566b41ae79d96c04c2f829576466 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Apr 25 14:35:45 2014 -0700 Clean arch-level Kconfig files General cleanup of arch-level (x86 and arm) Kconfig files: 1) Move common stuff to top-level Makefile. 2) Remove unwanted config options. 3) Make options default to n instead of y 4) Include all arch-level Kconfigs by default (Necessary for arch-aware stages) Change-Id: I09eca097c128f38632249d6a1de816f055cdcfd0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/Kconfig | 24 +++++++----------------- src/arch/armv7/Kconfig | 9 --------- src/arch/x86/Kconfig | 11 +---------- src/lib/Makefile.inc | 38 -------------------------------------- 4 files changed, 8 insertions(+), 74 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e85ab62..bad55f8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -232,6 +232,7 @@ config ARCH_BINARY_X86 bool default n select PCI + select PC80_SYSTEM config ARCH_BINARY_ARMV7 bool @@ -267,25 +268,8 @@ config ARCH_RAMSTAGE_X86 # Warning: The file is included whether or not the if is here. # but the if controls how the evaluation occurs. -if ARCH_BINARY_X86 source src/arch/x86/Kconfig -endif - -if ARCH_BINARY_ARMV7 source src/arch/armv7/Kconfig -endif - -config HAVE_ARCH_MEMSET - bool - default n - -config HAVE_ARCH_MEMCPY - bool - default n - -config HAVE_ARCH_MEMMOVE - bool - default n source src/vendorcode/Kconfig @@ -1147,3 +1131,9 @@ config REG_SCRIPT default n help Internal option that controls whether we compile in register scripts. + +# Maximum reboot count +# TODO: Improve description. +config MAX_REBOOT_CNT + int + default 3 diff --git a/src/arch/armv7/Kconfig b/src/arch/armv7/Kconfig index 4f9fc34..f521323 100644 --- a/src/arch/armv7/Kconfig +++ b/src/arch/armv7/Kconfig @@ -4,15 +4,6 @@ menu "Architecture (armv7)" config ARM_ARCH_OPTIONS bool default y - select HAVE_ARCH_MEMSET - select HAVE_ARCH_MEMCPY - select HAVE_ARCH_MEMMOVE - -# Maximum reboot count -# TODO: Improve description. -config MAX_REBOOT_CNT - int - default 3 choice prompt "Bootblock behaviour" diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 36c9356..b4f919e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -3,9 +3,6 @@ menu "Architecture (x86)" config X86_ARCH_OPTIONS bool default y - select HAVE_ARCH_MEMSET - select HAVE_ARCH_MEMCPY - select HAVE_ARCH_MEMMOVE # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. @@ -34,12 +31,6 @@ config STACK_SIZE hex default 0x1000 -# Maximum reboot count -# TODO: Improve description. -config MAX_REBOOT_CNT - int - default 3 - # This is something you almost certainly don't want to mess with. # How many SIPIs do we send when starting up APs and cores? # The answer in 2000 or so was '2'. Nowadays, on many systems, @@ -84,7 +75,7 @@ config ROMCC config PC80_SYSTEM bool - default y + default n config BOOTBLOCK_MAINBOARD_INIT string diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 3e2550c..07de0d0 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,27 +19,10 @@ subdirs-y += loaders bootblock-y += cbfs.c -ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) -bootblock-y += memset.c -endif bootblock-y += memchr.c -ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) -bootblock-y += memcpy.c -endif bootblock-y += memcmp.c -ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) -bootblock-y += memmove.c -endif -ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) -romstage-y += memset.c -rmodules-y += memset.c -endif romstage-y += memchr.c -ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) -romstage-y += memcpy.c -rmodules-y += memcpy.c -endif romstage-y += memcmp.c rmodules-y += memcmp.c romstage-y += cbfs.c @@ -53,26 +36,14 @@ romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c endif romstage-y += compute_ip_checksum.c -ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) -romstage-y += memmove.c -endif romstage-$(CONFIG_ARCH_BINARY_X86) += gcc.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c ramstage-y += coreboot_table.c ramstage-y += bootmem.c -ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) -ramstage-y += memset.c -endif ramstage-y += memchr.c -ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) -ramstage-y += memcpy.c -endif ramstage-y += memcmp.c -ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) -ramstage-y += memmove.c -endif ramstage-y += malloc.c smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += delay.c @@ -114,15 +85,6 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c -ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) -smm-y += memset.c -endif -ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) -smm-y += memcpy.c -endif -ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) -smm-y += memmove.c -endif smm-y += cbfs.c memcmp.c smm-y += gcc.c

1 0

Patch set updated for coreboot: 3d4f1e5 superio/fintek/f71869ad: Configure multi-func reg in devicetree
by Edward O'Callaghan 24 Apr '14

24 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5576 -gerrit commit 3d4f1e5c2535c27cca2b7962be56048db148c7d1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 24 02:58:11 2014 +1000 superio/fintek/f71869ad: Configure multi-func reg in devicetree Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 ++ src/superio/fintek/f71869ad/Makefile.inc | 1 + src/superio/fintek/f71869ad/chip.h | 9 +++- src/superio/fintek/f71869ad/f71869ad_multifunc.c | 61 ++++++++++++++++++++++++ src/superio/fintek/f71869ad/fintek_internal.h | 29 +++++++++++ src/superio/fintek/f71869ad/superio.c | 4 ++ 6 files changed, 108 insertions(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 574bb8a..18722de 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 12efbeb..35e596d 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -19,4 +19,5 @@ ## romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..5011383 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,10 +22,17 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> +#include <stdint.h> struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; + + /* Member variables are defined in devicetree.cb. */ + uint8_t multi_function_register_1; + uint8_t multi_function_register_2; + uint8_t multi_function_register_3; + uint8_t multi_function_register_4; + uint8_t multi_function_register_5; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c new file mode 100644 index 0000000..221d154 --- /dev/null +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +#define MULTI_FUNC_SEL_REG1 0x28 +#define MULTI_FUNC_SEL_REG2 0x29 +#define MULTI_FUNC_SEL_REG3 0x2A +#define MULTI_FUNC_SEL_REG4 0x2B +#define MULTI_FUNC_SEL_REG5 0x2C + +void f71869ad_multifunc_init(device_t dev) +{ + struct superio_fintek_f71869ad_config *conf = dev->chip_info; + + pnp_enable_resources(dev); + pnp_enter_conf_mode(dev); + + /* multi-func select reg1 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG1, + conf->multi_function_register_1); + + /* multi-func select reg2 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG2, + conf->multi_function_register_2); + + /* multi-func select reg3 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG3, + conf->multi_function_register_3); + + /* multi-func select reg4 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG4, + conf->multi_function_register_4); + + /* multi-func select reg5 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG5, + conf->multi_function_register_5); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h new file mode 100644 index 0000000..86f5669 --- /dev/null +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F71869AD_INTERNAL_H +#define SUPERIO_FINTEK_F71869AD_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f71869ad_multifunc_init(device_t dev); + +#endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..770a712 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <stdlib.h> +#include "fintek_internal.h" #include "chip.h" #include "f71869ad.h" @@ -40,6 +41,9 @@ static void f71869ad_init(device_t dev) case F71869AD_KBC: pc_keyboard_init(&conf->keyboard); break; + case F71869AD_HWM: + f71869ad_multifunc_init(dev); + break; } }

1 0

Patch set updated for coreboot: 6b2273a superio/fintek/f71869ad: devicetree conf of multi-func reg
by Edward O'Callaghan 24 Apr '14

24 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5576 -gerrit commit 6b2273ae6534caf6c2319a86bcc5c20f2aea931f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 24 02:58:11 2014 +1000 superio/fintek/f71869ad: devicetree conf of multi-func reg Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 ++ src/superio/fintek/f71869ad/Makefile.inc | 1 + src/superio/fintek/f71869ad/chip.h | 9 ++++ src/superio/fintek/f71869ad/f71869ad_multifunc.c | 61 ++++++++++++++++++++++++ src/superio/fintek/f71869ad/fintek_internal.h | 29 +++++++++++ src/superio/fintek/f71869ad/superio.c | 4 ++ 6 files changed, 109 insertions(+) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 574bb8a..18722de 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 117239a..87d96e4 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index ea2ee6e..f10c151 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,9 +22,18 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include <pc80/keyboard.h> +#include <stdint.h> struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; + + /* Member variables are defined in devicetree.cb. */ + u8 multi_function_register_1; + u8 multi_function_register_2; + u8 multi_function_register_3; + u8 multi_function_register_4; + u8 multi_function_register_5; + }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c new file mode 100644 index 0000000..221d154 --- /dev/null +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +#define MULTI_FUNC_SEL_REG1 0x28 +#define MULTI_FUNC_SEL_REG2 0x29 +#define MULTI_FUNC_SEL_REG3 0x2A +#define MULTI_FUNC_SEL_REG4 0x2B +#define MULTI_FUNC_SEL_REG5 0x2C + +void f71869ad_multifunc_init(device_t dev) +{ + struct superio_fintek_f71869ad_config *conf = dev->chip_info; + + pnp_enable_resources(dev); + pnp_enter_conf_mode(dev); + + /* multi-func select reg1 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG1, + conf->multi_function_register_1); + + /* multi-func select reg2 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG2, + conf->multi_function_register_2); + + /* multi-func select reg3 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG3, + conf->multi_function_register_3); + + /* multi-func select reg4 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG4, + conf->multi_function_register_4); + + /* multi-func select reg5 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG5, + conf->multi_function_register_5); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h new file mode 100644 index 0000000..86f5669 --- /dev/null +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F71869AD_INTERNAL_H +#define SUPERIO_FINTEK_F71869AD_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f71869ad_multifunc_init(device_t dev); + +#endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..770a712 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <stdlib.h> +#include "fintek_internal.h" #include "chip.h" #include "f71869ad.h" @@ -40,6 +41,9 @@ static void f71869ad_init(device_t dev) case F71869AD_KBC: pc_keyboard_init(&conf->keyboard); break; + case F71869AD_HWM: + f71869ad_multifunc_init(dev); + break; } }

1 0

Patch set updated for coreboot: 5b8b0a7 Introduce stage-specific architecture for coreboot
by Furquan Shaikh 23 Apr '14

23 Apr '14

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5577 -gerrit commit 5b8b0a7489469899fdcb97c564b44d30f2dce529 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Apr 23 10:18:48 2014 -0700 Introduce stage-specific architecture for coreboot Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These arch specific options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). In addition to different architectures/modes per stage, a separate binary arch is introduced to help to indentify the arch of CBFS binaries. Also, for now this arch type is used at places which are not clearly part of any of the above stages (eg seabios and others). The original CONFIG_ARCH variable is thus removed and replaced by CONFIG_BINARY_ARCH. Ultimate goal is to get rid of all the occurences of CONFIG_BINARY_ARCH and when we understand the arch for currently not-so-sure components. However, the general idea is that CONFIG_BINARY_ARCH should be declared as the topmost arch of the SoC or the arch which is actually responsible for loading the kernel. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage, CC_binary and similarly others. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- Makefile | 90 +++++++++++++++++++++-------- Makefile.inc | 66 +++++++++++++-------- src/Kconfig | 50 ++++++++++++---- src/arch/armv7/Makefile.inc | 50 ++++++++++------ src/arch/x86/Kconfig | 4 +- src/arch/x86/Makefile.inc | 85 +++++++++++++++++---------- src/arch/x86/boot/Makefile.inc | 8 +++ src/arch/x86/lib/Makefile.inc | 21 +++++-- src/console/Kconfig | 2 +- src/cpu/Kconfig | 6 +- src/cpu/Makefile.inc | 4 +- src/cpu/allwinner/a10/Kconfig | 5 +- src/cpu/amd/agesa/Kconfig | 5 +- src/cpu/amd/geode_gx1/Kconfig | 5 +- src/cpu/amd/geode_gx2/Kconfig | 5 +- src/cpu/amd/geode_lx/Kconfig | 5 +- src/cpu/amd/model_10xxx/Kconfig | 5 +- src/cpu/amd/model_fxx/Kconfig | 5 +- src/cpu/amd/sc520/Kconfig | 5 +- src/cpu/armltd/cortex-a9/Kconfig | 5 +- src/cpu/dmp/vortex86ex/Kconfig | 5 +- src/cpu/intel/ep80579/Kconfig | 5 +- src/cpu/intel/fsp_model_206ax/Kconfig | 5 +- src/cpu/intel/fsp_model_206ax/Makefile.inc | 2 +- src/cpu/intel/haswell/Kconfig | 5 +- src/cpu/intel/haswell/Makefile.inc | 6 +- src/cpu/intel/model_1067x/Kconfig | 5 +- src/cpu/intel/model_106cx/Kconfig | 5 +- src/cpu/intel/model_2065x/Kconfig | 5 +- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_65x/Kconfig | 5 +- src/cpu/intel/model_67x/Kconfig | 5 +- src/cpu/intel/model_68x/Kconfig | 5 +- src/cpu/intel/model_69x/Kconfig | 5 +- src/cpu/intel/model_6bx/Kconfig | 5 +- src/cpu/intel/model_6dx/Kconfig | 5 +- src/cpu/intel/model_6ex/Kconfig | 5 +- src/cpu/intel/model_6fx/Kconfig | 5 +- src/cpu/intel/model_6xx/Kconfig | 5 +- src/cpu/intel/model_f0x/Kconfig | 5 +- src/cpu/intel/model_f1x/Kconfig | 5 +- src/cpu/intel/model_f2x/Kconfig | 5 +- src/cpu/intel/model_f3x/Kconfig | 5 +- src/cpu/intel/model_f4x/Kconfig | 5 +- src/cpu/qemu-x86/Kconfig | 5 +- src/cpu/samsung/exynos5250/Kconfig | 5 +- src/cpu/samsung/exynos5420/Kconfig | 5 +- src/cpu/ti/am335x/Kconfig | 5 +- src/cpu/ti/am335x/Makefile.inc | 4 +- src/cpu/via/c3/Kconfig | 5 +- src/cpu/via/c7/Kconfig | 5 +- src/cpu/via/nano/Kconfig | 5 +- src/cpu/x86/Makefile.inc | 6 +- src/cpu/x86/smm/Makefile.inc | 26 ++++----- src/device/Kconfig | 8 +-- src/device/Makefile.inc | 2 +- src/device/device.c | 4 +- src/device/oprom/include/io.h | 2 +- src/device/oprom/yabel/compat/functions.c | 2 +- src/device/oprom/yabel/device.h | 8 +-- src/device/oprom/yabel/io.c | 2 +- src/drivers/Makefile.inc | 2 +- src/drivers/pc80/mc146818rtc.c | 2 +- src/drivers/uart/Kconfig | 4 +- src/ec/google/chromeec/Kconfig | 2 +- src/lib/Makefile.inc | 8 +-- src/lib/cbfs_core.c | 2 +- src/lib/coreboot_table.c | 2 +- src/mainboard/advansus/a785e-i/Makefile.inc | 2 +- src/mainboard/asus/m5a88-v/Makefile.inc | 2 +- src/mainboard/avalue/eax-785e/Makefile.inc | 2 +- src/mainboard/bifferos/bifferboard/Kconfig | 5 +- src/soc/intel/baytrail/Kconfig | 5 +- src/superio/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f10/Makefile.inc | 5 +- src/vendorcode/amd/agesa/f12/Makefile.inc | 5 +- src/vendorcode/amd/agesa/f14/Makefile.inc | 5 +- src/vendorcode/amd/agesa/f15/Makefile.inc | 5 +- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 5 +- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 5 +- src/vendorcode/amd/cimx/rd890/Makefile.inc | 6 +- src/vendorcode/amd/cimx/sb700/Makefile.inc | 5 +- src/vendorcode/amd/cimx/sb800/Makefile.inc | 5 +- src/vendorcode/amd/cimx/sb900/Makefile.inc | 5 +- src/vendorcode/google/chromeos/Makefile.inc | 17 +++--- src/vendorcode/intel/Makefile.inc | 5 +- 86 files changed, 529 insertions(+), 232 deletions(-) diff --git a/Makefile b/Makefile index b709d14..5207bba 100644 --- a/Makefile +++ b/Makefile @@ -113,33 +113,74 @@ else include $(HAVE_DOTCONFIG) -ARCHDIR-$(CONFIG_ARCH_ARMV7) := armv7 -ARCHDIR-$(CONFIG_ARCH_X86) := x86 +# Each stage of coreboot can have a different arch. For this we need separate +# config vars +# bootblock arch +ARCH-BOOTBLOCK-$(CONFIG_ARCH_BOOTBLOCK_ARMV7) := armv7 +ARCH-BOOTBLOCK-$(CONFIG_ARCH_BOOTBLOCK_X86) := i386 -ARCH-y := $(ARCHDIR-y) +# romstage arch +ARCH-ROMSTAGE-$(CONFIG_ARCH_BOOTBLOCK_ARMV7) := armv7 +ARCH-ROMSTAGE-$(CONFIG_ARCH_BOOTBLOCK_X86) := i386 -# If architecture folder name is different from GCC binutils architecture name, -# override here. -ARCH-$(CONFIG_ARCH_ARMV7) := armv7 -ARCH-$(CONFIG_ARCH_X86) := i386 +# ramstage arch +ARCH-RAMSTAGE-$(CONFIG_ARCH_BOOTBLOCK_ARMV7) := armv7 +ARCH-RAMSTAGE-$(CONFIG_ARCH_BOOTBLOCK_X86) := i386 -ifneq ($(INNER_SCANBUILD),y) -CC := $(CC_$(ARCH-y)) -endif -CPP := $(CPP_$(ARCH-y)) -AS := $(AS_$(ARCH-y)) -LD := $(LD_$(ARCH-y)) -NM := $(NM_$(ARCH-y)) -OBJCOPY := $(OBJCOPY_$(ARCH-y)) -OBJDUMP := $(OBJDUMP_$(ARCH-y)) -READELF := $(READELF_$(ARCH-y)) -STRIP := $(STRIP_$(ARCH-y)) -AR := $(AR_$(ARCH-y)) +# overall binary arch +ARCH-BINARY-$(CONFIG_ARCH_BINARY_ARMV7) := armv7 +ARCH-BINARY-$(CONFIG_ARCH_BINARY_X86) := i386 -CFLAGS += $(CFLAGS_$(ARCH-y)) +ARCHDIR-armv7 := armv7 +ARCHDIR-i386 := x86 -LIBGCC_FILE_NAME := $(shell test -r `$(CC) -print-libgcc-file-name` && \ - $(CC) -print-libgcc-file-name) +# If architecture folder name is different from GCC binutils architecture name, +# override here. +ARCH-$(CONFIG_ARCH_BINARY_ARMV7) := armv7 +ARCH-$(CONFIG_ARCH_BINARY_X86) := i386 + +# Since there can be a different arch for each stage, we can have a different cc +# for each stage +CC_bootblock := $(CC_$(ARCH-BOOTBLOCK-y)) +CC_romstage := $(CC_$(ARCH-ROMSTAGE-y)) +CC_ramstage := $(CC_$(ARCH-RAMSTAGE-y)) +CC_binary := $(CC_$(ARCH-BINARY-y)) + +# Since there can be a different arch for each stage, we can have a different nm +# for each stage +NM_bootblock := $(NM_$(ARCH-BOOTBLOCK-y)) +NM_romstage := $(NM_$(ARCH-ROMSTAGE-y)) +NM_ramstage := $(NM_$(ARCH-RAMSTAGE-y)) +NM_binary := $(NM_$(ARCH-BINARY-y)) + +# Since there can be a different arch for each stage, we can have a different +# objcopy for each stage +OBJCOPY_bootblock := $(OBJCOPY_$(ARCH-BOOTBLOCK-y)) +OBJCOPY_romstage := $(OBJCOPY_$(ARCH-ROMSTAGE-y)) +OBJCOPY_ramstage := $(OBJCOPY_$(ARCH-RAMSTAGE-y)) +OBJCOPY_binary := $(OBJCOPY_$(ARCH-BINARY-y)) + +# CFLAGS +CFLAGS_bootblock += $(CFLAGS_$(ARCH-BOOTBLOCK-y)) +CFLAGS_romstage += $(CFLAGS_$(ARCH-ROMSTAGE-y)) +CFLAGS_ramstage += $(CFLAGS_$(ARCH-RAMSTAGE-y)) +CFLAGS_binary += $(CFLAGS_$(ARCH-BINARY-y)) + +AS_binary := $(AS_$(ARCH-BINARY-y)) +LD_binary := $(LD_$(ARCH-BINARY-y)) +NM_binary := $(NM_$(ARCH-BINARY-y)) +OBJCOPY_binary := $(OBJCOPY_$(ARCH-BINARY-y)) +OBJDUMP_binary := $(OBJDUMP_$(ARCH-BINARY-y)) +READELF_binary := $(READELF_$(ARCH-BINARY-y)) +STRIP_binary := $(STRIP_$(ARCH-BINARY-y)) +AR_binary := $(AR_$(ARCH-BINARY-y)) + +LIBGCC_FILE_NAME_bootblock := $(shell test -r `$(CC_bootblock) -print-libgcc-file-name` && \ + $(CC_bootblock) -print-libgcc-file-name) +LIBGCC_FILE_NAME_romstage := $(shell test -r `$(CC_romstage) -print-libgcc-file-name` && \ + $(CC_romstage) -print-libgcc-file-name) +LIBGCC_FILE_NAME_ramstage := $(shell test -r `$(CC_ramstage) -print-libgcc-file-name` && \ + $(CC_ramstage) -print-libgcc-file-name) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) @@ -264,7 +305,8 @@ ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template $(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" - $(CC) $(3) -MMD $$$$(CFLAGS) -c -o $$$$@ $$$$< + $(eval cc-class := $(call find-class-comm,$(class))) + $(CC_$(cc-class)) $(3) -MMD $$$$(CFLAGS_$(cc-class)) -c -o $$$$@ $$$$< en$(EMPTY)def end$(EMPTY)if endef @@ -285,7 +327,7 @@ printall: @echo alldirs:=$(alldirs) @echo allsrcs=$(allsrcs) @echo DEPENDENCIES=$(DEPENDENCIES) - @echo LIBGCC_FILE_NAME=$(LIBGCC_FILE_NAME) + @echo LIBGCC_FILE_NAME=$(LIBGCC_FILE_NAME_$(class)) @$(foreach class,$(special-classes),echo $(class):='$($(class))'; ) endif diff --git a/Makefile.inc b/Makefile.inc index 326358e..90337c0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -65,7 +65,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool -subdirs-y += src/arch/$(ARCHDIR-y) +subdirs-y += src/arch/armv7 src/arch/x86 subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += site-local @@ -105,7 +105,7 @@ files-in-dir=$(filter-out $(call dir-wildcards,$(call filter-out-dirs,$(1),$(dir # reduce command line length by linking the objects of each # directory into an intermediate file ramstage-postprocess=$(foreach d,$(sort $(dir $(1))), \ - $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD) -o $$@ -r $$^ ) \ + $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD_binary) -o $$@ -r $$^ ) \ $(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(call files-in-dir,$(d),$(1)),$(ramstage-objs)))) romstage-c-ccopts:=-D__PRE_RAM__ @@ -146,10 +146,10 @@ smm-c-deps:=$$(OPTION_TABLE_H) define ramstage-objs_asl_template $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" - $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-y)/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl + $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-RAMSTAGE-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$(a))).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c - $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c + $(CC_ramstage) $$(CFLAGS_ramstage) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c # keep %.o: %.c rule from catching the temporary .c file after a make clean mv $$(basename $$(a)).c $$(basename $$(a)).hex endef @@ -168,7 +168,7 @@ cbfs-files-processor-nvramtool= \ # arg2: binary file name cbfs-files-processor-vsa= \ $(eval $(2): $(1) ; \ - printf " CREATE $(2) (from $(1))\n"; $(OBJCOPY) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(1) $(2).tmp && $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(2).tmp -o $(2)) + printf " CREATE $(2) (from $(1))\n"; $(OBJCOPY_binary) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(1) $(2).tmp && $(LD_binary) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(2).tmp -o $(2)) ####################################################################### # Add handler for arbitrary files in CBFS @@ -211,19 +211,29 @@ ifneq ($(CONFIG_LOCALVERSION),"") COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) endif -INCLUDES := -Isrc -Isrc/include -I$(obj) -Isrc/arch/$(ARCHDIR-y)/include +INCLUDES := -Isrc -Isrc/include -I$(obj) INCLUDES += -Isrc/device/oprom/include # abspath is a workaround for romcc INCLUDES += -include $(src)/include/kconfig.h -CFLAGS = $(INCLUDES) -Os -pipe -g -nostdinc -CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow +INCLUDES_binary := -Isrc/arch/$(ARCHDIR-$(ARCH-BINARY-y))/include +INCLUDES_bootblock := -Isrc/arch/$(ARCHDIR-$(ARCH-BOOTBLOCK-y))/include +INCLUDES_romstage := -Isrc/arch/$(ARCHDIR-$(ARCH-ROMSTAGE-y))/include +INCLUDES_ramstage := -Isrc/arch/$(ARCHDIR-$(ARCH-RAMSTAGE-y))/include + +CFLAGS_common = $(INCLUDES) -Os -pipe -g -nostdinc +CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes +CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS_common += -Wstrict-aliasing -Wshadow ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) -CFLAGS += -Werror +CFLAGS_common += -Werror endif -CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer + +CFLAGS_binary = $(CFLAGS_common) $(INCLUDES_binary) +CFLAGS_bootblock = $(CFLAGS_common) $(INCLUDES_bootblock) +CFLAGS_romstage = $(CFLAGS_common) $(INCLUDES_romstage) +CFLAGS_ramstage = $(CFLAGS_common) $(INCLUDES_ramstage) additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ $(objutil)/ifdfake $(objutil)/options @@ -245,9 +255,9 @@ $(obj)/build.h: .xcompile printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x`LANG= date +"%w"`\n" >> $(obj)/build.ht printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht - printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht - printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC_binary) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS_binary) --version | head -n1)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD_binary) --version | head -n1)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s 2>/dev/null || hostname 2>/dev/null)\"\n" >> $(obj)/build.ht @@ -315,15 +325,15 @@ $(objutil)/%.o: $(objutil)/%.c $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -c -o $@ $< + $(CC_ramstage) -MMD $(CFLAGS_ramstage) -c -o $@ $< $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $< + $(CC_romstage) -MMD -D__PRE_RAM__ $(CFLAGS_romstage) -c -o $@ $< $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(bootblock-c-ccopts) $(CFLAGS) -c -o $@ $< + $(CC_bootblock) -MMD $(bootblock-c-ccopts) $(CFLAGS_bootblock) -c -o $@ $< ####################################################################### # Clean up rules @@ -339,7 +349,7 @@ clean-for-update-target: rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean OUT=$(abspath $(obj)) HOSTCC="$(HOSTCC)" CC="$(CC)" LD="$(LD)" + $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean OUT=$(abspath $(obj)) HOSTCC="$(HOSTCC)" CC="$(CC_binary)" LD="$(LD_binary)" clean-target: rm -f $(obj)/coreboot* @@ -412,16 +422,22 @@ tools: $(objutil)/kconfig/conf $(objutil)/cbfstool/cbfstool $(objutil)/cbfstool/ # Common recipes for all stages ######################################################################################################################################################################## +find-class = $(if $(filter $(1),$(basename $(1))),$(1),$(call find-class,$(basename $(1)))) + +find-class-comm = $(if $(CC_$(call find-class,$(1))),$(call find-class,$(1)),binary) + $(objcbfs)/%.bin: $(objcbfs)/%.elf + $(eval class := $(call find-class-comm,$(@F))) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ + $(OBJCOPY_$(class)) -O binary $< $@ $(objcbfs)/%.elf: $(objcbfs)/%.debug + $(eval class := $(call find-class-comm,$(@F))) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cp $< $@.tmp - $(NM) -n $@.tmp | sort > $(basename $(a)).map - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp + $(NM_$(class)) -n $@.tmp | sort > $(basename $(a)).map + $(OBJCOPY_$(class)) --strip-debug $@.tmp + $(OBJCOPY_$(class)) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ ######################################################################################################################################################################## @@ -550,10 +566,10 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -ifeq ($(CONFIG_ARCH_ARMV7),y) +ifeq ($(CONFIG_ARCH_BINARY_ARMV7),y) ROMSTAGE_ELF := romstage.elf endif -ifeq ($(CONFIG_ARCH_X86),y) +ifeq ($(CONFIG_ARCH_BINARY_X86),y) ROMSTAGE_ELF := romstage_xip.elf endif diff --git a/src/Kconfig b/src/Kconfig index 6356b19..e85ab62 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -228,22 +228,50 @@ source src/mainboard/Kconfig # This option is used to set the architecture of a mainboard to X86. # It is usually set in mainboard/*/Kconfig. -config ARCH_X86 +config ARCH_BINARY_X86 bool default n select PCI -config ARCH_ARMV7 +config ARCH_BINARY_ARMV7 bool default n +# This option is used to set the architecture of bootblock stage +config ARCH_BOOTBLOCK_ARMV7 + bool + default n + +config ARCH_BOOTBLOCK_X86 + bool + default n + +# This option is used to set the architecture of romstage stage +config ARCH_ROMSTAGE_ARMV7 + bool + default n + +config ARCH_ROMSTAGE_X86 + bool + default n + +# This option is used to set the architecture of ramstage stage +config ARCH_RAMSTAGE_ARMV7 + bool + default n + +config ARCH_RAMSTAGE_X86 + bool + default n + + # Warning: The file is included whether or not the if is here. # but the if controls how the evaluation occurs. -if ARCH_X86 +if ARCH_BINARY_X86 source src/arch/x86/Kconfig endif -if ARCH_ARMV7 +if ARCH_BINARY_ARMV7 source src/arch/armv7/Kconfig endif @@ -334,7 +362,7 @@ config TIMER_QUEUE config COOP_MULTITASKING def_bool n - depends on TIMER_QUEUE && ARCH_X86 + depends on TIMER_QUEUE && ARCH_BINARY_X86 help Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple @@ -433,7 +461,7 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM by the board and/or chipset. config HAVE_REFCODE_BLOB - depends on ARCH_X86 + depends on ARCH_BINARY_X86 bool "An external reference code blob should be put into cbfs." default n help @@ -518,7 +546,7 @@ config GENERATE_PIRQ_TABLE If unsure, say Y. config GENERATE_SMBIOS_TABLES - depends on ARCH_X86 + depends on ARCH_BINARY_X86 bool "Generate SMBIOS tables" default y help @@ -532,8 +560,8 @@ menu "Payload" choice prompt "Add a payload" - default PAYLOAD_NONE if !ARCH_X86 - default PAYLOAD_SEABIOS if ARCH_X86 + default PAYLOAD_NONE if !ARCH_BINARY_X86 + default PAYLOAD_SEABIOS if ARCH_BINARY_X86 config PAYLOAD_NONE bool "None" @@ -567,7 +595,7 @@ config PAYLOAD_LINUX config PAYLOAD_SEABIOS bool "SeaBIOS" - depends on ARCH_X86 + depends on ARCH_BINARY_X86 help Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is @@ -1115,7 +1143,7 @@ config POWER_BUTTON_IS_OPTIONAL config REG_SCRIPT bool - default y if ARCH_X86 + default y if ARCH_BINARY_X86 default n help Internal option that controls whether we compile in register scripts. diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index aa85cc6..e90716a 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -32,6 +32,7 @@ subdirs-y += lib/ # ARM specific options ################################################################################ +ifeq ($(CONFIG_ARCH_BINARY_ARMV7),y) COREBOOT_PRE1_OPTS = -m armv7 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) COREBOOT_PRE_OPTS = -b 0 @@ -40,20 +41,23 @@ stages_o = $(obj)/arch/armv7/stages.o $(stages_o): $(stages_c) $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -I. $(INCLUDES) -c -o $@ $< -marm + $(CC_binary) -I. $(INCLUDES) $(INCLUDES_binary) -c -o $@ $< -marm -CFLAGS += \ +CFLAGS_common += \ -ffixed-r8\ -march=armv7-a\ -marm\ -mno-unaligned-access\ -mthumb\ -mthumb-interwork +endif # CONFIG_ARCH_BINARY_ARMV7 ################################################################################ # Bootblock ################################################################################ +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV7),y) + bootblock-y += cache.c bootblock-y += eabi_compat.c bootblock-y += memset.S @@ -81,31 +85,35 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC_bootblock) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC_bootblock) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(bootblock-c-ccopts) $(INCLUDES) -MM \ + $(CC_bootblock) $(bootblock-c-ccopts) $(INCLUDES) $(INCLUDES_bootblock) -MM \ -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@ + $(CC_bootblock) $(bootblock-c-ccopts) -c -S $(CFLAGS_bootblock) -I. $(INCLUDES) $(INCLUDES_bootblock) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC_bootblock) -nostdlib -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(bootblock-objs) $(stages) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group endif +endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 + ################################################################################ # Romstage ################################################################################ +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y) + romstage-y += cache.c romstage-y += div0.c romstage-y += eabi_compat.c @@ -132,9 +140,9 @@ crt0s += $(cpu_incs-y) $(objcbfs)/romstage.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif $(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions @@ -149,21 +157,24 @@ $(objgenerated)/crt0.romstage.S: $$(crt0s) $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm + $(CC_romstage) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + $(CC_romstage) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" - $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ + $(CC_romstage) -MMD $(CFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ + +endif # CONFIG_ARCH_ROMSTAGE_ARMV7 ################################################################################ # Ramstage ################################################################################ -# Things that appear in every board +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7),y) + ramstage-y += exception.c ramstage-y += exception_asm.S ramstage-y += div0.c @@ -183,17 +194,17 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/armv7/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld + $(LD_ramstage) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $< + $(CC_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/ramstage.ld $< endif -$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group + $(LD_ramstage) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group endif ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y) @@ -220,3 +231,4 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif +endif # CONFIG_ARCH_RAMSTAGE_ARMV7 \ No newline at end of file diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 8854e6b..36c9356 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -13,14 +13,14 @@ config X86_ARCH_OPTIONS config AP_IN_SIPI_WAIT bool default n - depends on ARCH_X86 && SMP + depends on ARCH_BINARY_X86 && SMP # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM bool default n - depends on ARCH_X86 + depends on ARCH_BINARY_X86 config RAMBASE hex diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a09c66f..4d96f2f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -53,9 +53,13 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE)) mbi.bin-type := mbi +ifeq ($(CONFIG_ARCH_BINARY_X86),y) + COREBOOT_PRE1_OPTS = -m x86 -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) COREBOOT_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) +endif + ################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -75,6 +79,8 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l # Build the bootblock +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86),y) + bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds @@ -114,31 +120,35 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_bootblock) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC_bootblock) $(INCLUDES) $(INCLUDES_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $(INCLUDES_bootblock) $< -o $@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< + $(CC_bootblock) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif +endif # CONFIG_ARCH_BOOTBLOCK_X86 + ################################################################################ # Romstage ################################################################################ +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86),y) + crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = ldscripts += $(src)/arch/x86/init/romstage.ld @@ -170,14 +180,26 @@ else ROMCCFLAGS := -mcpu=i386 -O2 # !MMX, !SSE endif +$(objcbfs)/romstage_%.bin: $(objcbfs)/romstage_%.elf + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_romstage) -O binary $< $@ + +$(objcbfs)/romstage_%.elf: $(objcbfs)/romstage_%.debug + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + cp $< $@.tmp + $(NM_romstage) -n $@.tmp | sort > $(basename $(a)).map + $(OBJCOPY_romstage) --strip-debug $@.tmp + $(OBJCOPY_romstage) --add-gnu-debuglink=$< $@.tmp + mv $@.tmp $@ + $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" - $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $(INCLUDES_romstage) $< -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" - $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ + $(CC_romstage) -MMD $(CFLAGS_romstage) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc @printf " POST romstage.inc\n" @@ -195,21 +217,21 @@ romstage-libs ?= $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif - $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ + $(NM_romstage) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ - $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ + $(NM_romstage) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ else true; fi $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) --end-group -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions @@ -238,16 +260,20 @@ $(objgenerated)/crt0.romstage.S: $$(crt0s) $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + $(CC_romstage) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + $(CC_romstage) $(INCLUDES) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + +endif # CONFIG_ARCH_ROMSTAGE_X86 ################################################################################ # Ramstage ################################################################################ +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86),y) + ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_MP_TABLE),y) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/mptable.c),) @@ -305,30 +331,31 @@ else $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld + $(LD_ramstage) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $< + $(CC_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $< endif endif -$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) +$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group + $(LD_ramstage) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group endif +endif # CONFIG_ARCH_RAMSTAGE_X86 ################################################################################ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ - CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ - OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ - AS="$(AS)" CPP="$(CPP)" \ + CC="$(CC_binary)" LD="$(LD_binary)" OBJDUMP="$(OBJDUMP_binary)" \ + OBJCOPY="$(OBJCOPY_binary)" STRIP="$(STRIP_binary)" \ + AS="$(AS_binary)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ @@ -337,8 +364,8 @@ seabios: filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ - CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ - OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + CC="$(CC_binary)" LD="$(LD_binary)" OBJDUMP="$(OBJDUMP_binary)" \ + OBJCOPY="$(OBJCOPY_binary)" STRIP="$(STRIP_binary)" \ CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \ CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE) @@ -346,6 +373,6 @@ filo: grub2: $(MAKE) -C payloads/external/GRUB2 -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ - CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ - OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + CC="$(CC_binary)" LD="$(LD_binary)" OBJDUMP="$(OBJDUMP_binary)" \ + OBJCOPY="$(OBJCOPY_binary)" STRIP="$(STRIP_binary)" \ CONFIG_GRUB2_MASTER=$(CONFIG_GRUB2_MASTER) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 928fc03..061074c 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,6 +1,13 @@ + +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86),y) + romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c +endif # CONFIG_ARCH_ROMSTAGE_X86 + +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86),y) + ramstage-y += boot.c ramstage-y += gdt.c ramstage-y += tables.c @@ -14,3 +21,4 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S $(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h +endif # CONFIG_ARCH_RAMSTAGE_X86 \ No newline at end of file diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 8b7418b..03e6c88 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,3 +1,16 @@ + +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86),y) + +romstage-y += cbfs_and_run.c +romstage-y += memset.c +romstage-y += memcpy.c +romstage-y += memmove.c +romstage-y += rom_media.c + +endif # CONFIG_ARCH_ROMSTAGE_X86 + +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86),y) + ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c @@ -12,12 +25,6 @@ ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S -romstage-y += cbfs_and_run.c -romstage-y += memset.c -romstage-y += memcpy.c -romstage-y += memmove.c -romstage-y += rom_media.c - smm-y += memset.c smm-y += memcpy.c smm-y += memmove.c @@ -26,3 +33,5 @@ smm-y += rom_media.c rmodules-y += memset.c rmodules-y += memcpy.c rmodules-y += memmove.c + +endif # CONFIG_ARCH_RAMSTAGE_X86 \ No newline at end of file diff --git a/src/console/Kconfig b/src/console/Kconfig index 65fc1aa..c3d88a2 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -2,7 +2,7 @@ menu "Console" config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on ARCH_ARMV7 + depends on ARCH_BINARY_ARMV7 default n help Use console during the bootblock if supported diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6fced37..59407c2 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -14,7 +14,7 @@ source src/cpu/via/Kconfig source src/cpu/qemu-x86/Kconfig source src/cpu/x86/Kconfig -if ARCH_X86 +if ARCH_BINARY_X86 config CACHE_AS_RAM bool @@ -62,7 +62,7 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -endif # ARCH_X86 +endif # ARCH_BINARY_X86 config SUPPORT_CPU_UCODE_IN_CBFS bool @@ -80,7 +80,7 @@ config CPU_MICROCODE_ADDED_DURING_BUILD default y if CPU_MICROCODE_CBFS_GENERATE || CPU_MICROCODE_CBFS_EXTERNAL choice - prompt "Include CPU microcode in CBFS" if ARCH_X86 + prompt "Include CPU microcode in CBFS" if ARCH_BINARY_X86 default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index f206fdc..e66585b 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -42,13 +42,13 @@ endif # final microcode file. $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) @printf " LD $(subst $(obj)/,,$(@))\n" - $(LD) -static --entry=0 $+ -o $@ + $(LD_binary) -static --entry=0 $+ -o $@ # We have a lot of useless data in the large blob, and we are only interested in # the data section, so we only copy that part to the final microcode file $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -j .data -O binary $< $@ + $(OBJCOPY_binary) -j .data -O binary $< $@ ifeq ($(cbfs_include_ucode),y) # Add CPU microcode to specified rom image $(1) diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index f76a7b6..0e13f94 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -6,7 +6,10 @@ if CPU_ALLWINNER_A10 config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ARMV7 + select ARCH_BINARY_ARMV7 + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index fa36f38..7670f17 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,7 +26,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER diff --git a/src/cpu/amd/geode_gx1/Kconfig b/src/cpu/amd/geode_gx1/Kconfig index b87e8bc..f04c8d5 100644 --- a/src/cpu/amd/geode_gx1/Kconfig +++ b/src/cpu/amd/geode_gx1/Kconfig @@ -19,7 +19,10 @@ config CPU_AMD_GEODE_GX1 bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 if CPU_AMD_GEODE_GX1 diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index b96c770..9d74830 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -19,7 +19,10 @@ config CPU_AMD_GEODE_GX2 bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 if CPU_AMD_GEODE_GX2 diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 6aceab2..9527ea7 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -1,6 +1,9 @@ config CPU_AMD_GEODE_LX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 if CPU_AMD_GEODE_LX diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 30c2486..e0f0198 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -1,6 +1,9 @@ config CPU_AMD_MODEL_10XXX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SSE select SSE2 select MMCONF_SUPPORT_DEFAULT diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 1a811f4..34bf71d 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -1,6 +1,9 @@ config CPU_AMD_MODEL_FXX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select MMX select SSE select SSE2 diff --git a/src/cpu/amd/sc520/Kconfig b/src/cpu/amd/sc520/Kconfig index 46377be..a92724c 100644 --- a/src/cpu/amd/sc520/Kconfig +++ b/src/cpu/amd/sc520/Kconfig @@ -1,3 +1,6 @@ config CPU_AMD_SC520 bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index f46c6ff..b354444 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -1,6 +1,9 @@ config CPU_ARMLTD_CORTEX_A9 bool - select ARCH_ARMV7 + select ARCH_BINARY_ARMV7 + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 select EARLY_CONSOLE default n diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index aea8889..da8834c 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -19,5 +19,8 @@ config CPU_DMP_VORTEX86EX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select UDELAY_TSC diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index fa96f8d..d5aa4c8 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_EP80579 bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SSE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 22d01e6..527de90 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -28,7 +28,10 @@ if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index 1ea9c2a..b4d18c3 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -9,4 +9,4 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_incs += $(src)/cpu/intel/fsp_model_206ax/cache_as_ram.inc -CC := $(CC) -I$(CONFIG_MICROCODE_INCLUDE_PATH) +CC := $(CC_binary) -I$(CONFIG_MICROCODE_INCLUDE_PATH) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 97309ae..1726128 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,7 +6,10 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select BACKUP_DEFAULT_SMM_REGION select SMP select SSE2 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 63c1939..e504a68 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -26,14 +26,14 @@ rmodules-y += sipi_vector.S rmodules-y += sipi_header.c $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules.o - $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ + $(CC_ramstage) $(LDFLAGS) -nostdlib -r -o $@ $^ $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0)) $(SIPI_BIN): $(SIPI_ELF).rmod - $(OBJCOPY) -O binary $< $@ + $(OBJCOPY_ramstage) -O binary $< $@ $(SIPI_BIN).ramstage.o: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) + cd $(dir $@); $(OBJCOPY_ramstage) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 4d6add6..346d218 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,6 +1,9 @@ config CPU_INTEL_MODEL_1067X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE2 select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index ea6f5ca..3a9b4e5 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,6 +1,9 @@ config CPU_INTEL_MODEL_106CX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 4c7456d..48dfc82 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -5,7 +5,10 @@ if CPU_INTEL_MODEL_2065X config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE select SSE2 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 64b2a0a..60d0899 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -8,7 +8,10 @@ if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index b3fa7bd..6a417ec 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_65X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 7558bc2..4e3d6aa 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_67X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 670163a..b926b43 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -20,6 +20,9 @@ config CPU_INTEL_MODEL_68X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig index e4a0e6c..7ea9cdc 100644 --- a/src/cpu/intel/model_69x/Kconfig +++ b/src/cpu/intel/model_69x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_69X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 4dc6fe6..c0da73b 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_6BX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig index e6d5f1e..74c5b33 100644 --- a/src/cpu/intel/model_6dx/Kconfig +++ b/src/cpu/intel/model_6dx/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_6DX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index eee864d..6b6d5d9 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,6 +1,9 @@ config CPU_INTEL_MODEL_6EX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index b8de303..a7de42c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,6 +1,9 @@ config CPU_INTEL_MODEL_6FX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SSE2 select UDELAY_LAPIC diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index 49cfe2d..ef04e89 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_6XX bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig index 2ed68d1..d985254 100644 --- a/src/cpu/intel/model_f0x/Kconfig +++ b/src/cpu/intel/model_f0x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_F0X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig index 3bdb7f6..33e587f 100644 --- a/src/cpu/intel/model_f1x/Kconfig +++ b/src/cpu/intel/model_f1x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_F1X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 62393a8..9cef453 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_F2X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 5c9d0a3..d9f0f93 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_F3X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 849dcd0..3375326 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,5 +1,8 @@ config CPU_INTEL_MODEL_F4X bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select SMP select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index e54e4db..5284bf9 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,4 +19,7 @@ config CPU_QEMU_X86 bool - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index b8042e3..3dbfef7 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,5 +1,8 @@ config CPU_SAMSUNG_EXYNOS5250 - select ARCH_ARMV7 + select ARCH_BINARY_ARMV7 + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 6207adf..ab86349 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -1,5 +1,8 @@ config CPU_SAMSUNG_EXYNOS5420 - select ARCH_ARMV7 + select ARCH_BINARY_ARMV7 + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select EARLY_CONSOLE diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index 22a02ad..5432c24 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -1,5 +1,8 @@ config CPU_TI_AM335X - select ARCH_ARMV7 + select ARCH_BINARY_ARMV7 + select ARCH_BOOTBLOCK_ARMV7 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 5b10bd8..2017371 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -28,14 +28,14 @@ get_header_size= \ $(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -include $(obj)/config.h \ + $(CC_binary) -nostdlib -nostartfiles -static -include $(obj)/config.h \ -Wl,--defsym,header_load_size=$(strip \ $(call get_header_size,$(obj)/coreboot.rom, \ $(CONFIG_CBFS_PREFIX)/romstage \ ) \ ) \ -o $@.tmp $< -T $(header_ld) - $(OBJCOPY) --only-section=".header" -O binary $@.tmp $@ + $(OBJCOPY_binary) --only-section=".header" -O binary $@.tmp $@ $(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin @printf " HEADER $(subst $(obj)/,,$(@))\n" diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig index 566f07c..b898f81 100644 --- a/src/cpu/via/c3/Kconfig +++ b/src/cpu/via/c3/Kconfig @@ -5,7 +5,10 @@ if CPU_VIA_C3 config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select UDELAY_TSC select MMX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index d5f1a41..c4d27f7 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -5,7 +5,10 @@ if CPU_VIA_C7 config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select UDELAY_TSC select MMX select SSE2 diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 0f4f994..b4471a1 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -24,7 +24,10 @@ if CPU_VIA_NANO config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select UDELAY_TSC select MMX select SSE2 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 514d96c..bc6a116 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -16,13 +16,13 @@ endif rmodules-$(CONFIG_PARALLEL_MP) += sipi_vector.S $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules.o - $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ + $(CC_ramstage) $(LDFLAGS) -nostdlib -r -o $@ $^ $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0)) $(SIPI_BIN): $(SIPI_RMOD) - $(OBJCOPY) -O binary $< $@ + $(OBJCOPY_ramstage) -O binary $< $@ $(SIPI_BIN).ramstage.o: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) + cd $(dir $@); $(OBJCOPY_ramstage) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 9720630..2d31f07 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -32,32 +32,32 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smmstub # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs) - $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ + $(CC_ramstage) $(LDFLAGS) -nostdlib -r -o $@ $^ # Link the SMM stub module with a 0-byte heap. $(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0)) $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod - $(OBJCOPY) -O binary $< $@ + $(OBJCOPY_ramstage) -O binary $< $@ $(obj)/cpu/x86/smm/smmstub.ramstage.o: $(obj)/cpu/x86/smm/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) + cd $(dir $@); $(OBJCOPY_ramstage) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) # C-based SMM handler. -$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME) - $(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group +$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME_ramstage) + $(CC_ramstage) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group $(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE))) $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod - $(OBJCOPY) -O binary $< $@ + $(OBJCOPY_ramstage) -O binary $< $@ $(obj)/cpu/x86/smm/smm.ramstage.o: $(obj)/cpu/x86/smm/smm @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) + cd $(dir $@); $(OBJCOPY_ramstage) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) else # CONFIG_SMM_MODULES @@ -79,18 +79,18 @@ endif smm-y += smihandler.c -$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME) - $(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group +$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME_ramstage) + $(CC_ramstage) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions - $(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o - $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map - $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm + $(CC_ramstage) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o + $(NM_ramstage) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map + $(OBJCOPY_ramstage) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm # change to the target path because objcopy will use the path name in its # ELF symbol names. $(obj)/cpu/x86/smm/smm_wrap.ramstage.o: $(obj)/cpu/x86/smm/smm_wrap @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(obj)/cpu/x86/smm; $(OBJCOPY) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.o + cd $(obj)/cpu/x86/smm; $(OBJCOPY_ramstage) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.o endif # CONFIG_SMM_MODULES diff --git a/src/device/Kconfig b/src/device/Kconfig index 932b4de..8f5a0f8 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -91,14 +91,14 @@ config ON_DEVICE_ROM_RUN choice prompt "Option ROM execution type" - default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 - default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86 + default PCI_OPTION_ROM_RUN_YABEL if !ARCH_BINARY_X86 + default PCI_OPTION_ROM_RUN_REALMODE if ARCH_BINARY_X86 depends on VGA_ROM_RUN || GEODE_VSA config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_BINARY_X86 help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, @@ -161,7 +161,7 @@ config YABEL_VIRTMEM_LOCATION config YABEL_DIRECTHW prompt "Direct hardware access" bool - depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_X86 + depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_BINARY_X86 help YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index bd41b12..5df4843 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -9,7 +9,7 @@ ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c -ramstage-$(CONFIG_ARCH_X86) += pnp_device.c +ramstage-$(CONFIG_ARCH_BINARY_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c diff --git a/src/device/device.c b/src/device/device.c index e068cee..2b808e7 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -40,7 +40,7 @@ #include <stdlib.h> #include <string.h> #include <smp/spinlock.h> -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 #include <arch/ebda.h> #endif #include <timer.h> @@ -1189,7 +1189,7 @@ void dev_initialize(void) printk(BIOS_INFO, "Initializing devices...\n"); -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 /* Ensure EBDA is prepared before Option ROMs. */ setup_default_ebda(); #endif diff --git a/src/device/oprom/include/io.h b/src/device/oprom/include/io.h index 96dd572..6adce71 100644 --- a/src/device/oprom/include/io.h +++ b/src/device/oprom/include/io.h @@ -1,4 +1,4 @@ -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 #include <arch/io.h> #else void outb(u8 val, u16 port); diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index 2c3dc33..851917a 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -48,7 +48,7 @@ unsigned long tb_freq = 0; u64 get_time(void) { u64 act = 0; -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 u32 eax, edx; __asm__ __volatile__( diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h index 017aab9..1fce2ce 100644 --- a/src/device/oprom/yabel/device.h +++ b/src/device/oprom/yabel/device.h @@ -128,7 +128,7 @@ u8 biosemu_dev_translate_address(int type, unsigned long * addr); static inline void out32le(void *addr, u32 val) { -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7 +#if CONFIG_ARCH_BINARY_X86 || CONFIG_ARCH_BINARY_ARMV7 *((u32*) addr) = cpu_to_le32(val); #else asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr)); @@ -139,7 +139,7 @@ static inline u32 in32le(void *addr) { u32 val; -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7 +#if CONFIG_ARCH_BINARY_X86 || CONFIG_ARCH_BINARY_ARMV7 val = cpu_to_le32(*((u32 *) addr)); #else asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr)); @@ -150,7 +150,7 @@ in32le(void *addr) static inline void out16le(void *addr, u16 val) { -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7 +#if CONFIG_ARCH_BINARY_X86 || CONFIG_ARCH_BINARY_ARMV7 *((u16*) addr) = cpu_to_le16(val); #else asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr)); @@ -161,7 +161,7 @@ static inline u16 in16le(void *addr) { u16 val; -#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7 +#if CONFIG_ARCH_BINARY_X86 || CONFIG_ARCH_BINARY_ARMV7 val = cpu_to_le16(*((u16*) addr)); #else asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr)); diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 94f610d..1449f52 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -26,7 +26,7 @@ #include <device/resource.h> #endif -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 #include <arch/io.h> #else // these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index f11e4b8..413b4ae 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -37,4 +37,4 @@ subdirs-y += ti subdirs-y += ipmi subdirs-y += elog subdirs-y += xpowers -subdirs-$(CONFIG_ARCH_X86) += pc80 +subdirs-$(CONFIG_ARCH_BINARY_X86) += pc80 diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 51cd6c3..685f073 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -52,7 +52,7 @@ static void rtc_set_checksum(int range_start, int range_end, int cks_loc) } #endif -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) #else diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index a979437..bb71f69 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -5,9 +5,9 @@ config DRIVERS_UART config DRIVERS_UART_8250IO bool "Serial port on SuperIO" - depends on !ARCH_ARMV7 + depends on !ARCH_BINARY_ARMV7 default n if NO_UART_ON_SUPERIO - default y if ARCH_X86 + default y if ARCH_BINARY_X86 # Select this for mainboard without SuperIO serial port. config NO_UART_ON_SUPERIO diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 342db3e..2d63b5f 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -21,7 +21,7 @@ config EC_GOOGLE_CHROMEEC_I2C_CHIP default 0x1e config EC_GOOGLE_CHROMEEC_LPC - depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + depends on EC_GOOGLE_CHROMEEC && ARCH_BINARY_X86 # Needs Plug-and-play. def_bool y help Google Chrome EC via LPC bus. diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f8cf3b1..3e2550c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -56,7 +56,7 @@ romstage-y += compute_ip_checksum.c ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) romstage-y += memmove.c endif -romstage-$(CONFIG_ARCH_X86) += gcc.c +romstage-$(CONFIG_ARCH_BINARY_X86) += gcc.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c @@ -83,7 +83,7 @@ ramstage-y += cbfs.c ramstage-y += lzma.c #ramstage-y += lzmadecode.c ramstage-y += stack.c -ramstage-$(CONFIG_ARCH_X86) += gcc.c +ramstage-$(CONFIG_ARCH_BINARY_X86) += gcc.c ramstage-y += clog2.c romstage-y += clog2.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c @@ -143,8 +143,8 @@ RMODULE_LDFLAGS := -nostartfiles -Wl,--emit-relocs -Wl,-z,defs -Wl,-Bsymbolic - # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(RMODULE_LDSCRIPT) $$(obj)/ldoptions $$(RMODTOOL) - $$(CC) $$(CFLAGS) $$(RMODULE_LDFLAGS) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--start-group $(strip $(2)) $$(LIBGCC_FILE_NAME) -Wl,--end-group - $$(NM) -n $$@ > $$(basename $$(a)).map + $$(CC_ramstage) $$(CFLAGS_ramstage) $$(RMODULE_LDFLAGS) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--start-group $(strip $(2)) $$(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group + $$(NM_ramstage) -n $$@ > $$(basename $$(a)).map $(strip $(1)).rmod: $(strip $(1)) $$(RMODTOOL) -i $$^ -o $$@ diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 50c037e..a6bd270 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -118,7 +118,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) // TODO Add a "size" in CBFS header for a platform independent way to // determine the end of CBFS data. -#if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 +#if defined(CONFIG_ARCH_BINARY_X86) && CONFIG_ARCH_BINARY_X86 romsize -= htonl(header->bootblocksize); #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8e7f85d..b2dd048 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -38,7 +38,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif -#if CONFIG_ARCH_X86 +#if CONFIG_ARCH_BINARY_X86 #include <cpu/x86/mtrr.h> #endif diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index 924f9d6..0bbc26f 100644 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -11,5 +11,5 @@ ifneq ($(CONFIG_CPU_AMD_AGESA),y) -I$(AGESA_ROOT)/Proc/CPU/ \ -I$(AGESA_ROOT)/Proc/CPU/Family - CFLAGS += $(AGESA_INC) + CFLAGS_common += $(AGESA_INC) endif diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index 924f9d6..0bbc26f 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -11,5 +11,5 @@ ifneq ($(CONFIG_CPU_AMD_AGESA),y) -I$(AGESA_ROOT)/Proc/CPU/ \ -I$(AGESA_ROOT)/Proc/CPU/Family - CFLAGS += $(AGESA_INC) + CFLAGS_common += $(AGESA_INC) endif diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index 924f9d6..0bbc26f 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -11,5 +11,5 @@ ifneq ($(CONFIG_CPU_AMD_AGESA),y) -I$(AGESA_ROOT)/Proc/CPU/ \ -I$(AGESA_ROOT)/Proc/CPU/Family - CFLAGS += $(AGESA_INC) + CFLAGS_common += $(AGESA_INC) endif diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig index 4ee9958..d97a889 100644 --- a/src/mainboard/bifferos/bifferboard/Kconfig +++ b/src/mainboard/bifferos/bifferboard/Kconfig @@ -2,7 +2,10 @@ if BOARD_BIFFEROS_BIFFERBOARD config BOARD_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select ROMCC select BOARD_ROMSIZE_KB_128 select NORTHBRIDGE_RDC_R8610 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 1b3ee05..a57d273 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,7 +8,10 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_X86 + select ARCH_BINARY_X86 + select ARCH_BOOTBLOCK_X86 + select ARCH_ROMSTAGE_X86 + select ARCH_RAMSTAGE_X86 select CACHE_MRC_SETTINGS select CAR_MIGRATION select COLLECT_TIMESTAMPS diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index e34fa89..4b55827 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -28,4 +28,4 @@ subdirs-y += smsc subdirs-y += via subdirs-y += winbond -ramstage-$(CONFIG_ARCH_X86) += common/conf_mode.c +ramstage-$(CONFIG_ARCH_BINARY_X86) += common/conf_mode.c diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc index 203efab..177302c 100644 --- a/src/vendorcode/amd/agesa/f10/Makefile.inc +++ b/src/vendorcode/amd/agesa/f10/Makefile.inc @@ -48,5 +48,8 @@ AGESA_CFLAGS = -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT export AGESA_INC export AGESA_CFLAGS -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_binary := $(CC_binary) $(AGESA_INC) $(AGESA_CFLAGS) diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index e1bafbe..4c5ec84 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -86,5 +86,8 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_binary := $(CC_binary) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index f457277..509b3ad 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -67,7 +67,10 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_binary := $(CC_binary) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### classes-y += libagesa diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 2a7acce..d8ee520 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -529,5 +529,8 @@ AGESA_CFLAGS = -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT export AGESA_INC export AGESA_CFLAGS -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_binary := $(CC_binary) $(AGESA_INC) $(AGESA_CFLAGS) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 00ace78..ee174bf 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -91,7 +91,10 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_binary := $(CC_binary) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### classes-y += libagesa diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 0e68895..4d497f1 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -98,5 +98,8 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_binary := $(CC_binary) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### diff --git a/src/vendorcode/amd/cimx/rd890/Makefile.inc b/src/vendorcode/amd/cimx/rd890/Makefile.inc index feeb2cd..491f810 100644 --- a/src/vendorcode/amd/cimx/rd890/Makefile.inc +++ b/src/vendorcode/amd/cimx/rd890/Makefile.inc @@ -113,7 +113,11 @@ NB_CIMX_CFLAGS = export CIMX_ROOT export NB_CIMX_INC export NB_CIMX_CFLAGS -CC := $(CC) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC) + +CC_bootblock := $(CC_bootblock) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC) +CC_romstage := $(CC_romstage) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC) +CC_ramstage := $(CC_ramstage) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC) +CC_binary := $(CC_binary) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC) ####################################################################### diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc index 10d03e6..24e7ce1 100644 --- a/src/vendorcode/amd/cimx/sb700/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc @@ -72,7 +72,10 @@ SB_CIMX_CFLAGS = export CIMX_ROOT export SB_CIMX_INC export SB_CIMX_CFLAGS -CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC) +CC_bootblock := $(CC_bootblock) $(SB_CIMX_INC) +CC_romstage := $(CC_romstage) $(SB_CIMX_INC) +CC_ramstage := $(CC_ramstage) $(SB_CIMX_INC) +CC_binary := $(CC_binary) $(SB_CIMX_INC) ####################################################################### diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc index 3fb1d54..553ebae 100644 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc @@ -79,7 +79,10 @@ CIMX_CFLAGS = export CIMX_ROOT export CIMX_INC export CIMX_CFLAGS -CC := $(CC) $(CIMX_INC) +CC_bootblock := $(CC_bootblock) $(CIMX_INC) +CC_romstage := $(CC_romstage) $(CIMX_INC) +CC_ramstage := $(CC_ramstage) $(CIMX_INC) +CC_binary := $(CC_binary) $(CIMX_INC) ####################################################################### diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc index 4a3417f..e26a0fe 100644 --- a/src/vendorcode/amd/cimx/sb900/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc @@ -82,7 +82,10 @@ CIMX_CFLAGS = export CIMX_ROOT export CIMX_INC export CIMX_CFLAGS -CC := $(CC) $(CIMX_INC) +CC_bootblock := $(CC_bootblock) $(CIMX_INC) +CC_romstage := $(CC_romstage) $(CIMX_INC) +CC_ramstage := $(CC_ramstage) $(CIMX_INC) +CC_binary := $(CC_binary) $(CIMX_INC) ####################################################################### diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 21e1750..9f4afa8 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -19,9 +19,9 @@ romstage-y += chromeos.c ramstage-y += chromeos.c -romstage-$(CONFIG_ARCH_X86) += vbnv.c -ramstage-$(CONFIG_ARCH_X86) += vbnv.c -romstage-$(CONFIG_ARCH_X86) += vboot.c +romstage-$(CONFIG_ARCH_BINARY_X86) += vbnv.c +ramstage-$(CONFIG_ARCH_BINARY_X86) += vbnv.c +romstage-$(CONFIG_ARCH_BINARY_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c @@ -33,9 +33,9 @@ romstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c endif ifeq ($(MOCK_TPM),1) -CFLAGS += -DMOCK_TPM=1 +CFLAGS_common += -DMOCK_TPM=1 else -CFLAGS += -DMOCK_TPM=0 +CFLAGS_common += -DMOCK_TPM=0 endif ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y) @@ -43,7 +43,7 @@ romstage-y += vboot_loader.c rmodules-y += vboot_wrapper.c VB_LIB = $(obj)/external/vboot_reference/vboot_fw.a -VB_FIRMWARE_ARCH := $(ARCHDIR-y) +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-BINARY-y)) VB_SOURCE := vboot_reference # Add the vboot include paths. @@ -62,11 +62,11 @@ VBOOT_STUB_DEPS += $(obj)/arch/x86/lib/memcpy.rmodules.o VBOOT_STUB_DEPS += $(VB_LIB) # Remove the '-include' option since that will break vboot's build and ensure # vboot_reference can get to coreboot's include files. -VBOOT_CFLAGS += $(patsubst -I%,-I../%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS))) +VBOOT_CFLAGS += $(patsubst -I%,-I../%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS_binary))) VBOOT_CFLAGS += -DVBOOT_DEBUG $(VBOOT_STUB_DOTO): $(VBOOT_STUB_DEPS) - $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ + $(CC_binary) $(LDFLAGS) -nostdlib -r -o $@ $^ # Link the vbootstub module with a 64KiB-byte heap. $(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000)) @@ -75,6 +75,7 @@ $(eval $(call rmodule_link,$(VBOOT_STUB_ELF), $(VBOOT_STUB_DOTO), 0x10000)) $(VB_LIB): @printf " MAKE $(subst $(obj)/,,$(@))\n" $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + CC="$(CC_binary)" \ CFLAGS="$(VBOOT_CFLAGS)" \ make -C $(VB_SOURCE) \ BUILD=../$(dir $(VB_LIB)) \ diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index 8569af0..79c648d 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -23,5 +23,8 @@ FSP_SRC_FILES := $(wildcard src/vendorcode/intel/$(FSP_PATH)srx/*.c) FSP_C_INPUTS := $(foreach file, $(FSP_SRC_FILES), $(FSP_PATH)srx/$(notdir $(file))) ramstage-y += $(FSP_C_INPUTS) -CC := $(CC) -Isrc/vendorcode/intel/$(FSP_PATH)include +CC_bootblock := $(CC_bootblock) -Isrc/vendorcode/intel/$(FSP_PATH)include +CC_romstage := $(CC_romstage) -Isrc/vendorcode/intel/$(FSP_PATH)include +CC_ramstage := $(CC_ramstage) -Isrc/vendorcode/intel/$(FSP_PATH)include +CC_binary := $(CC_binary) -Isrc/vendorcode/intel/$(FSP_PATH)include endif

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coreboot-gerrit April 2014