coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: acfc2ef superio/fintek/*: Fix header style
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5572 -gerrit commit acfc2efd908358164cce47bc74670799f4edd692 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 17:01:45 2014 +1000 superio/fintek/*: Fix header style Remove some redundant includes. Fix repetitiveness in include guards and strip some misplaced tabs for whitespaces. Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71805f/f71805f.h | 16 ++++++++-------- src/superio/fintek/f71859/f71859.h | 6 +++--- src/superio/fintek/f71863fg/chip.h | 1 - src/superio/fintek/f71863fg/f71863fg.h | 20 ++++++++++---------- src/superio/fintek/f71869ad/chip.h | 1 - src/superio/fintek/f71869ad/f71869ad.h | 6 +++--- src/superio/fintek/f71872/f71872.h | 6 +++--- src/superio/fintek/f71889/chip.h | 1 - src/superio/fintek/f71889/f71889.h | 6 +++--- src/superio/fintek/f81865f/f81865f.h | 22 +++++++++++----------- 10 files changed, 41 insertions(+), 44 deletions(-) diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 6aae58f..69b868d 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71805F_F71805F_H -#define SUPERIO_FINTEK_F71805F_F71805F_H +#ifndef SUPERIO_FINTEK_F71805F_H +#define SUPERIO_FINTEK_F71805F_H /* * Datasheet: @@ -31,13 +31,13 @@ /* Logical Device Numbers (LDN). */ #define F71805F_FDC 0x00 /* Floppy */ -#define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ +#define F71805F_SP1 0x01 /* UART1 */ +#define F71805F_SP2 0x02 /* UART2 */ #define F71805F_PP 0x03 /* Parallel port */ -#define F71805F_HWM 0x04 /* Hardware monitor */ -#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71805F_PME 0x0a /* Power Management Events (PME) */ +#define F71805F_HWM 0x04 /* Hardware monitor */ +#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71805F_PME 0x0a /* Power Management Events (PME) */ void f71805f_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71805F_F71805F_H */ +#endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index 580fa34..ab114a4 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -18,12 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71859_F71859_H -#define SUPERIO_FINTEK_F71859_F71859_H +#ifndef SUPERIO_FINTEK_F71859_H +#define SUPERIO_FINTEK_F71859_H /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ void f71859_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71859_F71859_H */ +#endif /* SUPERIO_FINTEK_F71859_H */ diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h index 4d2652e..a2c04d7 100644 --- a/src/superio/fintek/f71863fg/chip.h +++ b/src/superio/fintek/f71863fg/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71863FG_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71863fg_config { diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index 127a120..c29ddbe 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -18,21 +18,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71863FG_F71863FG_H -#define SUPERIO_FINTEK_F71863FG_F71863FG_H +#ifndef SUPERIO_FINTEK_F71863FG_H +#define SUPERIO_FINTEK_F71863FG_H /* Logical Device Numbers (LDN). */ #define F71863FG_FDC 0x00 /* Floppy */ #define F71863FG_SP1 0x01 /* UART1 */ -#define F71863FG_SP2 0x02 /* UART2 */ +#define F71863FG_SP2 0x02 /* UART2 */ #define F71863FG_PP 0x03 /* Parallel port */ -#define F71863FG_HWM 0x04 /* Hardware monitor */ -#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */ -#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71863FG_VID 0x07 /* VID */ -#define F71863FG_SPI 0x08 /* SPI */ -#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ +#define F71863FG_HWM 0x04 /* Hardware monitor */ +#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */ +#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71863FG_VID 0x07 /* VID */ +#define F71863FG_SPI 0x08 /* SPI */ +#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ void f71863fg_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71863FG_F71863FG_H */ +#endif /* SUPERIO_FINTEK_F71863FG_H */ diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..ea2ee6e 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index abc0260..43a4397 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71869AD_F71869AD_H -#define SUPERIO_FINTEK_F71869AD_F71869AD_H +#ifndef SUPERIO_FINTEK_F71869AD_H +#define SUPERIO_FINTEK_F71869AD_H /* Logical Device Numbers (LDN). */ #define F71869AD_FDC 0x00 /* Floppy */ @@ -34,4 +34,4 @@ void f71869ad_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71869AD_F71869AD_H */ +#endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index 577f8d1..fb80762 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71872_F71872_H -#define SUPERIO_FINTEK_F71872_F71872_H +#ifndef SUPERIO_FINTEK_F71872_H +#define SUPERIO_FINTEK_F71872_H /* Logical Device Numbers (LDN). */ #define F71872_FDC 0x00 /* Floppy */ @@ -34,4 +34,4 @@ void f71872_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71872_F71872_H */ +#endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h index 50312ad..e5a15d3 100644 --- a/src/superio/fintek/f71889/chip.h +++ b/src/superio/fintek/f71889/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71889_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71889_config { diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 6dc43b3..72148f4 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71889_F71889_H -#define SUPERIO_FINTEK_F71889_F71889_H +#ifndef SUPERIO_FINTEK_F71889_H +#define SUPERIO_FINTEK_F71889_H /* Logical Device Numbers (LDN). */ #define F71889_FDC 0x00 /* Floppy */ @@ -36,4 +36,4 @@ void f71889_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71889_F71889_H */ +#endif /* SUPERIO_FINTEK_F71889_H */ diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index ccf41af..99b7698 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -22,19 +22,19 @@ * Datasheet: * - Name: F81865F/F-I */ -#ifndef SUPERIO_FINTEK_F81865_F81865_H -#define SUPERIO_FINTEK_F81865_F81865_H +#ifndef SUPERIO_FINTEK_F81865_H +#define SUPERIO_FINTEK_F81865_H /* Logical Device Numbers (LDN). */ -#define F81865F_FDC 0x00 /* Floppy */ -#define F81865F_SP1 0x10 /* UART1 */ -#define F81865F_SP2 0x11 /* UART2 */ -#define F81865F_PP 0x03 /* Parallel Port */ -#define F81865F_HWM 0x04 /* Hardware Monitor */ -#define F81865F_KBC 0x05 /* Keyboard/Mouse */ -#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F81865F_PME 0x0a /* Power Management Events (PME) */ +#define F81865F_FDC 0x00 /* Floppy */ +#define F81865F_SP1 0x10 /* UART1 */ +#define F81865F_SP2 0x11 /* UART2 */ +#define F81865F_PP 0x03 /* Parallel Port */ +#define F81865F_HWM 0x04 /* Hardware Monitor */ +#define F81865F_KBC 0x05 /* Keyboard/Mouse */ +#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81865F_PME 0x0a /* Power Management Events (PME) */ void f81865f_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F81865_F81865_H */ +#endif /* SUPERIO_FINTEK_F81865_H */

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Patch merged into coreboot/master: 20f25dd Rename coreboot_ram stage to ramstage
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 20f25dd5c8a513ee136e9f6d8c67959591298617 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 22 10:41:05 2014 -0700 Rename coreboot_ram stage to ramstage Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5567 for details. -gerrit

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Patch merged into coreboot/master: 8171496 Get rid of HAVE_INIT_TIMER config option
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 817149643c27fca022cf526d6113a4aff898d511 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Apr 22 11:48:30 2014 -0700 Get rid of HAVE_INIT_TIMER config option There is redundancy in terms of use of init_timer. We have a Kconfig option to decide whether a board has init_timer as well as we use a stub for init_timer in places where we do not have any init_timer defined. Thus, remove the Kconfig option. Henceforth, all boards that do not have init_timer functionality can include a stub_timer if required. Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: http://review.coreboot.org/5569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5569 for details. -gerrit

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Patch merged into coreboot/master: ea2900b superio/ite/it8673f: Remove poor implementation
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit ea2900bd6c260bb8b06a8b9e3fc93a21bd87d2e6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 04:21:53 2014 +1000 superio/ite/it8673f: Remove poor implementation Following the reasoning of: HASH superio/ite/it8705f: Remove poor implementation Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5568 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5568 for details. -gerrit

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Patch merged into coreboot/master: 45b7b5a superio/ite/it8705f: Remove poor implementation
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 45b7b5af763c6b3ab385690891641103b41e4816 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 04:00:38 2014 +1000 superio/ite/it8705f: Remove poor implementation This super io support is poorly implemented and would not work for all boards since it hardcodes values. Since there are no users of it, remove for now pending a fresh reimplementation from scratch. Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5566 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5566 for details. -gerrit

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Patch merged into coreboot/master: 5c41ee6 superio/ite/it8716f: Rewrite from hardcoded base addr
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 5c41ee69ef27575f93441f487b1d9f4c2d97f8e0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 01:43:38 2014 +1000 superio/ite/it8716f: Rewrite from hardcoded base addr Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5565 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5565 for details. -gerrit

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Patch merged into coreboot/master: 03ad2a2 superio/ite/it8721f: Rewrite from hardcoded base addr
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 03ad2a26b07909a5c34a1ade30f905ae3de5b8a0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 21 17:34:38 2014 +1000 superio/ite/it8721f: Rewrite from hardcoded base addr Rewrite early_serial.c implementation to honour a passed base address in device_t, removing any hard coding of values. We also expose early sio init functions as romstage symbols to avoid falsely #including "early_serial.c" in romstage.c of board support. Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5561 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5561 for details. -gerrit

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Patch merged into coreboot/master: 392de45 mainboard/*: Remove DUMP_ACPI_TABLES from amd boards
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 392de45ae2d9550c3b95078bff7a52c9e5eed563 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 17 22:24:40 2014 +1000 mainboard/*: Remove DUMP_ACPI_TABLES from amd boards Dumping the ACPI tables in this way has limited use, is not likely to be used and is poorly implemented. There are much more sophisticated tools available on Linux for debugging ACPI as such this code is outside the scope of coreboots 'bring up the hardware only' philosophy. A more generic implemention could be done with hexdump() in coreboot proper following on from this cleanup. Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5530 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5530 for details. -gerrit

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Patch set updated for coreboot: 5641281 superio/fintek/f71869ad: Configure multi-func reg in devicetree
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5576 -gerrit commit 5641281d9d6d707244e9ed8cf6251a6ef22f47ac Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 24 02:58:11 2014 +1000 superio/fintek/f71869ad: Configure multi-func reg in devicetree Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 ++ src/superio/fintek/f71869ad/Makefile.inc | 1 + src/superio/fintek/f71869ad/chip.h | 9 +++- src/superio/fintek/f71869ad/f71869ad_multifunc.c | 60 ++++++++++++++++++++++++ src/superio/fintek/f71869ad/fintek_internal.h | 29 ++++++++++++ src/superio/fintek/f71869ad/superio.c | 4 ++ 6 files changed, 107 insertions(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 574bb8a..18722de 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 12efbeb..35e596d 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -19,4 +19,5 @@ ## romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..5011383 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,10 +22,17 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> +#include <stdint.h> struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; + + /* Member variables are defined in devicetree.cb. */ + uint8_t multi_function_register_1; + uint8_t multi_function_register_2; + uint8_t multi_function_register_3; + uint8_t multi_function_register_4; + uint8_t multi_function_register_5; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c new file mode 100644 index 0000000..46c4d2c --- /dev/null +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +#define MULTI_FUNC_SEL_REG1 0x28 +#define MULTI_FUNC_SEL_REG2 0x29 +#define MULTI_FUNC_SEL_REG3 0x2A +#define MULTI_FUNC_SEL_REG4 0x2B +#define MULTI_FUNC_SEL_REG5 0x2C + +void f71869ad_multifunc_init(device_t dev) +{ + struct superio_fintek_f71869ad_config *conf = dev->chip_info; + + pnp_enter_conf_mode(dev); + + /* multi-func select reg1 */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG1, + conf->multi_function_register_1); + + /* multi-func select reg2 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG2, + conf->multi_function_register_2); + + /* multi-func select reg3 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG3, + conf->multi_function_register_3); + + /* multi-func select reg4 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG4, + conf->multi_function_register_4); + + /* multi-func select reg5 (CLK_TUNE_EN=0) */ + pnp_write_config(dev, MULTI_FUNC_SEL_REG5, + conf->multi_function_register_5); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h new file mode 100644 index 0000000..86f5669 --- /dev/null +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_F71869AD_INTERNAL_H +#define SUPERIO_FINTEK_F71869AD_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> + +void f71869ad_multifunc_init(device_t dev); + +#endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..770a712 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <stdlib.h> +#include "fintek_internal.h" #include "chip.h" #include "f71869ad.h" @@ -40,6 +41,9 @@ static void f71869ad_init(device_t dev) case F71869AD_KBC: pc_keyboard_init(&conf->keyboard); break; + case F71869AD_HWM: + f71869ad_multifunc_init(dev); + break; } }

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Patch set updated for coreboot: e88d0a7 superio/fintek/f71869ad: Make hwm devicetree configurable
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5580 -gerrit commit e88d0a7928247c0b139c994644f73f76760b6bc2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Apr 26 15:21:45 2014 +1000 superio/fintek/f71869ad: Make hwm devicetree configurable Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 16 ++++ src/superio/fintek/f71869ad/Makefile.inc | 1 + src/superio/fintek/f71869ad/chip.h | 14 +++ src/superio/fintek/f71869ad/f71869ad_hwm.c | 119 ++++++++++++++++++++++++ src/superio/fintek/f71869ad/fintek_internal.h | 1 + src/superio/fintek/f71869ad/superio.c | 1 + 6 files changed, 152 insertions(+) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 18722de..04c1826 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -61,6 +61,22 @@ chip northbridge/amd/agesa/family14/root_complex register "multi_function_register_3" = "0x24" register "multi_function_register_4" = "0x00" register "multi_function_register_5" = "0x60" +# +# HWM configuration registers + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_smb_command_byte" = "0x01" + register "hwm_smb_status" = "0x01" + register "hwm_smb_protocal_sel" = "0x82" +# # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 35e596d..7ee2501 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -20,4 +20,5 @@ romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_hwm.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5011383..3b43ef4 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -33,6 +33,20 @@ struct superio_fintek_f71869ad_config { uint8_t multi_function_register_3; uint8_t multi_function_register_4; uint8_t multi_function_register_5; + /* HWM configuration registers */ + uint8_t hwm_smbus_address; + uint8_t hwm_smbus_control_reg; + uint8_t hwm_fan_type_sel_reg; + uint8_t hwm_fan1_temp_adj_rate_reg; + uint8_t hwm_fan_mode_sel_reg; + uint8_t hwm_fan1_idx_rpm_mode; + uint8_t hwm_fan1_seg1_speed_count; + uint8_t hwm_fan1_seg2_speed_count; + uint8_t hwm_fan1_seg3_speed_count; + uint8_t hwm_fan1_temp_map_sel; + uint8_t hwm_smb_command_byte; + uint8_t hwm_smb_status; + uint8_t hwm_smb_protocal_sel; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c new file mode 100644 index 0000000..ffa0b2f --- /dev/null +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "fintek_internal.h" + +/* + * The Fintek F71869AD Super I/O Hardware Monitor permits the configuration of + * three fans individually, where fan1 is typically taken as the CPU fan. Each + * fan is controlled by the relation: + * + * Tfan? = Tnow + (Ta - Tb)*Ct + * + * Parameters in this relation are specified in the devicetree.cb. + */ + +/* + * Register CR01 ~ CR03 -> Configuration Registers + * Register CR0A ~ CR0F -> PECI/TSI Control Register + * Register CR10 ~ CR37 -> Voltage Setting Register + * Register CR40 ~ CR4E -> PECI 3.0 Command and Register + * Register CR60 ~ CR8E -> Temperature Setting Register + * Register CR90 ~ CRDF -> Fan Control Setting Register + */ +#define HWM_SMBUS_ADDR 0x08 +#define HWM_SMBUS_CONTROL_REG 0x0A +#define HWM_FAN_TYPE_SEL_REG 0x94 +#define HWM_FAN1_TEMP_ADJ_RATE_REG 0x95 +#define HWM_FAN_MODE_SEL_REG 0x96 +#define HWM_FAN_FAULT_TIME_REG 0x9F /* bit7 FAN_PROG_SEL */ +#define HWM_FAN1_IDX_RPM_MODE 0xA3 +#define HWM_FAN1_SEG1_SPEED_COUNT 0xAA +#define HWM_FAN1_SEG2_SPEED_COUNT 0xAB +#define HWM_FAN1_SEG3_SPEED_COUNT 0xAC +#define HWM_FAN1_TEMP_MAP_SEL 0xAF +#define HWM_SMB_COMMAND_BYTE 0xED +#define HWM_SMB_STATUS 0xEE /* bit6 TSI_CMD_PROG */ +#define HWM_SMB_PROTOCAL_SEL 0xEF + +static void pnp_write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +/* note: multifunc registers need to be tweaked before here */ +void f71869ad_hwm_init(device_t dev) +{ + struct superio_fintek_f71869ad_config *conf = dev->chip_info; + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + u16 port = res->base; /* data-sheet default base = 0x229 */ + + printk(BIOS_INFO, + "Fintek F71869AD Super I/O HWM: Initializing Hardware Monitor..\n"); + printk(BIOS_DEBUG, + "Fintek F71869AD Super I/O HWM: Base Address at 0x%x\n", port); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* Fintek F71869AD HWM (ordered) programming sequence. */ + + /* SMBus Address p.53 */ + pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address); + /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ + pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg); + /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ + /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ + pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel); + /* set FAN_PROG_SEL = 1 */ + pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a); + /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ + pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg); + /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ + pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg); + /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = + 1, p.88 */ + pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg); + /* set FAN_PROG_SEL = 0 */ + pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a); + /* FAN1 RPM mode p.70 */ + pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode); + /* FAN1 Segment X Speed Count */ + pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); + pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); + pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count); + /* .. */ + pnp_write_index(port, HWM_SMB_STATUS, conf->hwm_smb_status); + pnp_write_index(port, HWM_SMB_COMMAND_BYTE, conf->hwm_smb_command_byte); + pnp_write_index(port, HWM_SMB_PROTOCAL_SEL, conf->hwm_smb_protocal_sel); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 86f5669..6856c01 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -25,5 +25,6 @@ #include <device/pnp.h> void f71869ad_multifunc_init(device_t dev); +void f71869ad_hwm_init(device_t dev); #endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 770a712..cc690ec 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -43,6 +43,7 @@ static void f71869ad_init(device_t dev) break; case F71869AD_HWM: f71869ad_multifunc_init(dev); + f71869ad_hwm_init(dev); break; } }

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coreboot-gerrit April 2014