coreboot-gerrit April 2014

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Patch set updated for coreboot: 6da1f8d superio/fintek/*: Factor out generic romstage component
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5575 -gerrit commit 6da1f8df5a88b91463329a1f7c7b991453ea586d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 21:52:25 2014 +1000 superio/fintek/*: Factor out generic romstage component The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/romstage.c | 3 +- src/mainboard/amd/south_station/romstage.c | 3 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 3 +- src/mainboard/jetway/j7f2/romstage.c | 3 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 +- src/mainboard/jetway/pa78vm5/romstage.c | 3 +- src/mainboard/via/epia-m850/romstage.c | 5 +- src/superio/fintek/Kconfig | 19 +++++++ src/superio/fintek/Makefile.inc | 3 ++ src/superio/fintek/common/early_serial.c | 72 ++++++++++++++++++++++++++ src/superio/fintek/common/fintek.h | 29 +++++++++++ src/superio/fintek/f71805f/Makefile.inc | 1 - src/superio/fintek/f71805f/early_serial.c | 48 ----------------- src/superio/fintek/f71805f/f71805f.h | 2 - src/superio/fintek/f71859/Makefile.inc | 1 - src/superio/fintek/f71859/early_serial.c | 48 ----------------- src/superio/fintek/f71859/f71859.h | 2 - src/superio/fintek/f71863fg/Makefile.inc | 1 - src/superio/fintek/f71863fg/early_serial.c | 48 ----------------- src/superio/fintek/f71863fg/f71863fg.h | 2 - src/superio/fintek/f71869ad/Makefile.inc | 1 - src/superio/fintek/f71869ad/early_serial.c | 68 ------------------------ src/superio/fintek/f71869ad/f71869ad.h | 2 - src/superio/fintek/f71872/Makefile.inc | 1 - src/superio/fintek/f71872/early_serial.c | 48 ----------------- src/superio/fintek/f71872/f71872.h | 2 - src/superio/fintek/f71889/Makefile.inc | 1 - src/superio/fintek/f71889/early_serial.c | 46 ---------------- src/superio/fintek/f71889/f71889.h | 2 - src/superio/fintek/f81865f/Makefile.inc | 1 - src/superio/fintek/f81865f/early_serial.c | 48 ----------------- src/superio/fintek/f81865f/f81865f.h | 2 - 32 files changed, 139 insertions(+), 384 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e082f60..81804a9 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,6 +31,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" @@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5614f88..5e70ecc 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,6 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> @@ -58,7 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 299ba61..612ff1a 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -41,6 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -97,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 37c3ab4..8455610 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -31,6 +31,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71805f/f71805f.h> #include <lib.h> #include <spd.h> @@ -90,7 +91,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3406edf..3e962d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -40,7 +40,8 @@ #include <cpu/amd/mtrr.h> #include <sb_cimx.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include "superio/fintek/f71869ad/f71869ad.h" +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f71869ad/f71869ad.h> /* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" @@ -75,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index c082a67..044d0d8 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -42,6 +42,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -102,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 22f5ed6..9368028 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -36,9 +36,10 @@ #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#define SERIAL_DEV PNP_DEV(0x4e, 0x10) +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ void main(unsigned long bist) @@ -52,7 +53,7 @@ void main(unsigned long bist) vx900_enable_pci_config_space(); /* Serial console is easy to take care of */ - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); print_debug("Console initialized. \n"); diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 938494a..f577898 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,17 +18,35 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic Fintek romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_FINTEK_COMMON_ROMSTAGE + bool + config SUPERIO_FINTEK_F71805F bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + config SUPERIO_FINTEK_F71859 bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + config SUPERIO_FINTEK_F71863FG bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + config SUPERIO_FINTEK_F71869AD bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + config SUPERIO_FINTEK_F71872 bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + config SUPERIO_FINTEK_F71889 bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + config SUPERIO_FINTEK_F81865F bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 541a893..1b11336 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic fintek pre-ram stage driver +romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += f71805f subdirs-y += f71859 subdirs-y += f71863fg diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c new file mode 100644 index 0000000..d74b786 --- /dev/null +++ b/src/superio/fintek/common/early_serial.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Fintek variant Super I/O chips. + * + * The following is derived directly from the vendor Fintek's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Fintek Super I/O's we are required to pass + * magic numbers `passwords keys`. + * + * FINTEK_ENTRY_KEY := enable configuration : 0x87 + * FINTEK_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "fintek.h" + +#define FINTEK_ENTRY_KEY 0x87 +#define FINTEK_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_ENTRY_KEY, port); + outb(FINTEK_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void fintek_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h new file mode 100644 index 0000000..a08cf92 --- /dev/null +++ b/src/superio/fintek/common/fintek.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_COMMON_ROMSTAGE_H +#define SUPERIO_FINTEK_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void fintek_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc index 22c01e0..4a13799 100644 --- a/src/superio/fintek/f71805f/Makefile.inc +++ b/src/superio/fintek/f71805f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c deleted file mode 100644 index b823a43..0000000 --- a/src/superio/fintek/f71805f/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71805f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71805f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 1033ea2..82f3869 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -38,6 +38,4 @@ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F71805F_PME 0x0a /* Power Management Events (PME) */ -void f71805f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71859/Makefile.inc b/src/superio/fintek/f71859/Makefile.inc index 8858811..fa63a1b 100644 --- a/src/superio/fintek/f71859/Makefile.inc +++ b/src/superio/fintek/f71859/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71859) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c deleted file mode 100644 index cb0d3de..0000000 --- a/src/superio/fintek/f71859/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71859.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71859_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index ab114a4..f0111bd 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -24,6 +24,4 @@ /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ -void f71859_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71859_H */ diff --git a/src/superio/fintek/f71863fg/Makefile.inc b/src/superio/fintek/f71863fg/Makefile.inc index 85ec530..e48b93a 100644 --- a/src/superio/fintek/f71863fg/Makefile.inc +++ b/src/superio/fintek/f71863fg/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.c diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c deleted file mode 100644 index 251f298..0000000 --- a/src/superio/fintek/f71863fg/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71863fg.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71863fg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index c29ddbe..a11e69f 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -33,6 +33,4 @@ #define F71863FG_SPI 0x08 /* SPI */ #define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ -void f71863fg_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71863FG_H */ diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 12efbeb..117239a 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/early_serial.c b/src/superio/fintek/f71869ad/early_serial.c deleted file mode 100644 index 8518400..0000000 --- a/src/superio/fintek/f71869ad/early_serial.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Pre-RAM driver for the Fintek F71869AD Super I/O chip. - * - * Derived from p.34 in vendor data-sheet: - * - * - default index port : 0x4E - * - default data port : 0x4F - * - * - enable configuration : 0x87 - * - disable configuration : 0xAA - * - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71869ad.h" - -/* - * Enable configuration: pass entry key '0x87' into index port dev. - */ -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -/* - * Disable configuration: pass exit key '0xAA' into index port dev. - */ -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/* - * Bring up early serial debugging output before the RAM is initialized. - */ -void f71869ad_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index 43a4397..3aeac56 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -32,6 +32,4 @@ #define F71869AD_BSEL 0x07 /* BSEL */ #define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ -void f71869ad_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc index 58ba5d5..ed40eb0 100644 --- a/src/superio/fintek/f71872/Makefile.inc +++ b/src/superio/fintek/f71872/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71872) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c deleted file mode 100644 index bbfc264..0000000 --- a/src/superio/fintek/f71872/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71872.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71872_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index fb80762..629d42d 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -32,6 +32,4 @@ #define F71872_VID 0x07 /* VID */ #define F71872_PM 0x0a /* ACPI/PME */ -void f71872_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71889/Makefile.inc b/src/superio/fintek/f71889/Makefile.inc index 9864140..5c39860 100644 --- a/src/superio/fintek/f71889/Makefile.inc +++ b/src/superio/fintek/f71889/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71889) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c deleted file mode 100644 index 5e11474..0000000 --- a/src/superio/fintek/f71889/early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71889.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71889_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 72148f4..e46ab99 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -34,6 +34,4 @@ #define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ #define F71889_VREF 0x0b /* Vref */ -void f71889_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71889_H */ diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index 8afb286..1700f7c 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c deleted file mode 100644 index 29b5f9d..0000000 --- a/src/superio/fintek/f81865f/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f81865f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f81865f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 99b7698..e3c204a 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -35,6 +35,4 @@ #define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F81865F_PME 0x0a /* Power Management Events (PME) */ -void f81865f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F81865_H */

1 0

New patch to review for coreboot: bb0f641 superio/ite/*: Factor out generic romstage component
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5585 -gerrit commit bb0f6417f7ebce25a803865aa4d27328fe0a5e5c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 00:41:50 2014 +1000 superio/ite/*: Factor out generic romstage component NOTFORMERGE Following the reasoning of: HASHHERE superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dbm690t/romstage.c | 8 ++- src/mainboard/asus/a8n_e/romstage.c | 10 +-- src/mainboard/asus/f2a85-m/romstage.c | 7 +- src/mainboard/asus/m2v-mx_se/romstage.c | 5 +- src/mainboard/asus/m2v/romstage.c | 8 ++- src/mainboard/asus/m4a78-em/romstage.c | 7 +- src/mainboard/asus/m4a785-m/romstage.c | 7 +- src/mainboard/asus/m5a88-v/romstage.c | 3 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 10 ++- src/mainboard/lippert/hurricane-lx/romstage.c | 7 +- src/mainboard/lippert/literunner-lx/romstage.c | 7 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 7 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 8 ++- src/mainboard/siemens/sitemp_g1p1/romstage.c | 8 ++- src/mainboard/technexion/tim5690/romstage.c | 8 ++- src/mainboard/technexion/tim8690/romstage.c | 8 ++- src/superio/ite/Kconfig | 22 +++++++ src/superio/ite/Makefile.inc | 3 + src/superio/ite/common/early_serial.c | 86 +++++++++++++++++++++++++ src/superio/ite/common/ite.h | 33 ++++++++++ src/superio/ite/it8712f/Makefile.inc | 2 +- src/superio/ite/it8712f/early_serial.c | 38 +---------- src/superio/ite/it8712f/it8712f.h | 9 ++- src/superio/ite/it8721f/Makefile.inc | 1 - src/superio/ite/it8721f/early_serial.c | 85 ------------------------ src/superio/ite/it8721f/it8721f.h | 6 -- 26 files changed, 230 insertions(+), 173 deletions(-) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 74b6d1b..a013420 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -35,7 +35,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -43,6 +44,8 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..b531f90 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -21,8 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Used by it8712f_enable_serial(). */ +/* Used by ite_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) #include <stdint.h> #include <string.h> @@ -33,7 +34,8 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -103,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index ee9983d..0a5b784 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -35,10 +35,11 @@ #include <southbridge/amd/agesa/hudson/smbus.h> #include <stdint.h> #include <string.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> /* TODO: remove .c includes */ #include <drivers/pc80/i8254.c> #include <drivers/pc80/i8259.c> -#include <superio/ite/it8712f/early_serial.c> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void disable_cache_as_ram(void); @@ -48,6 +49,8 @@ void disable_cache_as_ram(void); #define SB_MMIO 0xFED80000 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void sbxxx_enable_48mhzout(void) { /* most likely programming to 48MHz out signal */ @@ -97,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* enable SIO clock */ sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_enable_3vsbsw(); console_init(); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..0085bb4 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); console_init(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..871a706 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -46,6 +47,7 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) #define IT8712F_GPIO_BASE 0x0a20 @@ -225,8 +227,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 18c6f18..93810d2 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 660ab0f..b360636 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 94a1e4e..9fca93f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -41,6 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -100,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb800_clk_output_48Mhz(); - it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 1ebdedd..6fa4c56 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -30,13 +30,17 @@ #include "northbridge/intel/i82810/raminit.h" #include "drivers/pc80/udelay_io.c" #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <lib.h> +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) + void main(unsigned long bist) { - it8712f_24mhz_clkin(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 95ea27d..5d71f36 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -35,9 +35,12 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 @@ -126,7 +129,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6edcf37..9ace1fb 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -35,9 +35,12 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 @@ -169,7 +172,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 68dcfc0..06715cf 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -35,9 +35,12 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -101,7 +104,7 @@ void main(unsigned long bist) * Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 59bd618..c4cc1a9 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -35,9 +35,13 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + + /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 @@ -166,7 +170,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6d36524..660c39e 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -43,7 +43,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" @@ -53,6 +54,8 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -111,8 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 42c2599..c9cbdba 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -37,12 +37,15 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -90,8 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 22a1212..ce5698a 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -37,12 +37,15 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index 4c0f927..9c91017 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,24 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic Ite romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_ITE_COMMON_ROMSTAGE + bool config SUPERIO_ITE_IT8661F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8671F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8712F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8716F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL bool depends on SUPERIO_ITE_IT8716F default n + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8718F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8721F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8728F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8772F bool + select SUPERIO_ITE_COMMON_ROMSTAGE diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 2b71521..7e1c81b 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic ite pre-ram stage driver +romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += it8661f subdirs-y += it8671f subdirs-y += it8712f diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c new file mode 100644 index 0000000..34aec74 --- /dev/null +++ b/src/superio/ite/common/early_serial.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "ite.h" + +/* Global configuration registers. */ +#define ite_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define ite_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define ite_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define ite_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +/* Helper procedures */ +static void ite_sio_write(device_t dev, u8 index, u8 value) +{ + pnp_set_logical_device(dev); + pnp_write_config(dev, index, value); +} + +static void ite_reg_write(device_t dev, u8 index, u8 value) +{ + ite_enter_conf(dev); + ite_sio_write(dev, index, value); + ite_exit_conf(dev); +} + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + ite_sio_write(dev, ite_CONFIG_REG_CC, 0x02); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: CLKIN_DEV + * ITE_UART_CLK_PREDIVIDE_24 + * ITE_UART_CLK_PREDIVIDE_48 (default) + */ +void ite_conf_clkin(device_t dev, u8 predivide) +{ + ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void ite_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} + diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h new file mode 100644 index 0000000..fbb12a0 --- /dev/null +++ b/src/superio/ite/common/ite.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_COMMON_ROMSTAGE_H +#define SUPERIO_ITE_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define ITE_UART_CLK_PREDIVIDE_24 0x01 + +void ite_conf_clkin(device_t dev, u8 predivide); +void ite_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..ce75645 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..d678f3f 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ @@ -30,7 +32,6 @@ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ @@ -58,14 +59,6 @@ static void it8712f_exit_conf(void) it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz is the default). */ -void it8712f_24mhz_clkin(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); -} - /* * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! * @@ -88,30 +81,3 @@ void it8712f_kill_watchdog(void) it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); } - -/* Enable the serial port(s). */ -void it8712f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8712f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..b40e473 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8712F_IT8712F_H -#define SUPERIO_ITE_IT8712F_IT8712F_H +#ifndef SUPERIO_ITE_IT8712F_H +#define SUPERIO_ITE_IT8712F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ @@ -36,7 +36,6 @@ #define IT8712F_IR 0x0a /* Consumer IR */ void it8712f_kill_watchdog(void); -void it8712f_enable_serial(device_t dev, u16 iobase); -void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +#endif /* SUPERIO_ITE_IT8712F_H */ diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc index ef616f4..4b1aa96 100644 --- a/src/superio/ite/it8721f/Makefile.inc +++ b/src/superio/ite/it8721f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c deleted file mode 100644 index df66222..0000000 --- a/src/superio/ite/it8721f/early_serial.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8721f.h" - -/* Global configuration registers. */ -#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8721f_sio_write(device_t dev, u8 index, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, index, value); -} - -static void it8721f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8721f_exit_conf(device_t dev) -{ - it8721f_sio_write(dev, IT8721F_CONFIG_REG_CC, 0x02); -} - -static void it8721f_reg_write(device_t dev, u8 index, u8 value) -{ - it8721f_enter_conf(dev); - it8721f_sio_write(dev, index, value); - it8721f_exit_conf(dev); -} - - -/* - * in romstage.c - * #define CLKIN_DEV PNP_DEV(0x2e, IT8721F_GPIO) - * and pass: CLKIN_DEV - * IT8721F_UART_CLK_PREDIVIDE_24 - * IT8721F_UART_CLK_PREDIVIDE_48 (default) - */ -void it8721f_conf_clkin(device_t dev, u8 predivide) -{ - it8721f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); -} - - -/* Enable the serial port(s). */ -void it8721f_enable_serial(device_t dev, u16 iobase) -{ - it8721f_enter_conf(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - it8721f_exit_conf(dev); -} diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index 9d5a528..ce794cf 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -36,10 +36,4 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */ -#define IT8721F_UART_CLK_PREDIVIDE_24 0x01 - -void it8721f_conf_clkin(device_t dev, u8 predivide); -void it8721f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_ITE_IT8721F_H */

1 0

Patch set updated for coreboot: e377368 superio/fintek/*: Factor out generic romstage component
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5575 -gerrit commit e377368aefb09f82cea56259284af2a0a6e511d4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 21:52:25 2014 +1000 superio/fintek/*: Factor out generic romstage component The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/romstage.c | 3 +- src/mainboard/amd/south_station/romstage.c | 3 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 3 +- src/mainboard/jetway/j7f2/romstage.c | 3 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 +- src/mainboard/jetway/pa78vm5/romstage.c | 3 +- src/mainboard/via/epia-m850/romstage.c | 5 +- src/superio/fintek/Kconfig | 47 ++++++++++++++--- src/superio/fintek/Makefile.inc | 3 ++ src/superio/fintek/common/early_serial.c | 72 ++++++++++++++++++++++++++ src/superio/fintek/common/fintek.h | 29 +++++++++++ src/superio/fintek/f71805f/Makefile.inc | 1 - src/superio/fintek/f71805f/early_serial.c | 48 ----------------- src/superio/fintek/f71805f/f71805f.h | 2 - src/superio/fintek/f71859/Makefile.inc | 1 - src/superio/fintek/f71859/early_serial.c | 48 ----------------- src/superio/fintek/f71859/f71859.h | 2 - src/superio/fintek/f71863fg/Makefile.inc | 1 - src/superio/fintek/f71863fg/early_serial.c | 48 ----------------- src/superio/fintek/f71863fg/f71863fg.h | 2 - src/superio/fintek/f71869ad/Makefile.inc | 1 - src/superio/fintek/f71869ad/early_serial.c | 68 ------------------------ src/superio/fintek/f71869ad/f71869ad.h | 2 - src/superio/fintek/f71872/Makefile.inc | 1 - src/superio/fintek/f71872/early_serial.c | 48 ----------------- src/superio/fintek/f71872/f71872.h | 2 - src/superio/fintek/f71889/Makefile.inc | 1 - src/superio/fintek/f71889/early_serial.c | 46 ---------------- src/superio/fintek/f71889/f71889.h | 2 - src/superio/fintek/f81865f/Makefile.inc | 1 - src/superio/fintek/f81865f/early_serial.c | 48 ----------------- src/superio/fintek/f81865f/f81865f.h | 2 - 32 files changed, 160 insertions(+), 391 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e082f60..81804a9 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,6 +31,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" @@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5614f88..5e70ecc 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,6 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> @@ -58,7 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 299ba61..612ff1a 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -41,6 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -97,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 37c3ab4..8455610 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -31,6 +31,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71805f/f71805f.h> #include <lib.h> #include <spd.h> @@ -90,7 +91,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3406edf..3e962d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -40,7 +40,8 @@ #include <cpu/amd/mtrr.h> #include <sb_cimx.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include "superio/fintek/f71869ad/f71869ad.h" +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f71869ad/f71869ad.h> /* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" @@ -75,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index c082a67..044d0d8 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -42,6 +42,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -102,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 22f5ed6..9368028 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -36,9 +36,10 @@ #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#define SERIAL_DEV PNP_DEV(0x4e, 0x10) +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ void main(unsigned long bist) @@ -52,7 +53,7 @@ void main(unsigned long bist) vx900_enable_pci_config_space(); /* Serial console is easy to take care of */ - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); print_debug("Console initialized. \n"); diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 938494a..2d16cae 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,17 +18,49 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config SUPERIO_FINTEK_F71805F +# Generic Fintek romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_FINTEK_COMMON_ROMSTAGE bool + +config SUPERIO_FINTEK_F71805F + bool "Fintek F7105F" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F7105F ramstage driver. + config SUPERIO_FINTEK_F71859 - bool + bool "Fintek F71859" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71859 ramstage driver. + config SUPERIO_FINTEK_F71863FG - bool + bool "Fintek F71863FG" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71863FG ramstage driver. + config SUPERIO_FINTEK_F71869AD - bool + bool "Fintek F71869AD" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71869AD ramstage driver. + config SUPERIO_FINTEK_F71872 - bool + bool "Fintek F71872" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71872 ramstage driver. + config SUPERIO_FINTEK_F71889 - bool + bool "Fintek F71889" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71889 ramstage driver. + config SUPERIO_FINTEK_F81865F - bool + bool "Fintek F81865F" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F81865F ramstage driver. diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 541a893..1b11336 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic fintek pre-ram stage driver +romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += f71805f subdirs-y += f71859 subdirs-y += f71863fg diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c new file mode 100644 index 0000000..d74b786 --- /dev/null +++ b/src/superio/fintek/common/early_serial.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Fintek variant Super I/O chips. + * + * The following is derived directly from the vendor Fintek's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Fintek Super I/O's we are required to pass + * magic numbers `passwords keys`. + * + * FINTEK_ENTRY_KEY := enable configuration : 0x87 + * FINTEK_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "fintek.h" + +#define FINTEK_ENTRY_KEY 0x87 +#define FINTEK_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_ENTRY_KEY, port); + outb(FINTEK_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void fintek_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h new file mode 100644 index 0000000..a08cf92 --- /dev/null +++ b/src/superio/fintek/common/fintek.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_COMMON_ROMSTAGE_H +#define SUPERIO_FINTEK_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void fintek_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc index 22c01e0..4a13799 100644 --- a/src/superio/fintek/f71805f/Makefile.inc +++ b/src/superio/fintek/f71805f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c deleted file mode 100644 index b823a43..0000000 --- a/src/superio/fintek/f71805f/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71805f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71805f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 1033ea2..82f3869 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -38,6 +38,4 @@ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F71805F_PME 0x0a /* Power Management Events (PME) */ -void f71805f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71859/Makefile.inc b/src/superio/fintek/f71859/Makefile.inc index 8858811..fa63a1b 100644 --- a/src/superio/fintek/f71859/Makefile.inc +++ b/src/superio/fintek/f71859/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71859) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c deleted file mode 100644 index cb0d3de..0000000 --- a/src/superio/fintek/f71859/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71859.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71859_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index ab114a4..f0111bd 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -24,6 +24,4 @@ /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ -void f71859_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71859_H */ diff --git a/src/superio/fintek/f71863fg/Makefile.inc b/src/superio/fintek/f71863fg/Makefile.inc index 85ec530..e48b93a 100644 --- a/src/superio/fintek/f71863fg/Makefile.inc +++ b/src/superio/fintek/f71863fg/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.c diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c deleted file mode 100644 index 251f298..0000000 --- a/src/superio/fintek/f71863fg/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71863fg.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71863fg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index c29ddbe..a11e69f 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -33,6 +33,4 @@ #define F71863FG_SPI 0x08 /* SPI */ #define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ -void f71863fg_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71863FG_H */ diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 12efbeb..117239a 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/early_serial.c b/src/superio/fintek/f71869ad/early_serial.c deleted file mode 100644 index 8518400..0000000 --- a/src/superio/fintek/f71869ad/early_serial.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Pre-RAM driver for the Fintek F71869AD Super I/O chip. - * - * Derived from p.34 in vendor data-sheet: - * - * - default index port : 0x4E - * - default data port : 0x4F - * - * - enable configuration : 0x87 - * - disable configuration : 0xAA - * - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71869ad.h" - -/* - * Enable configuration: pass entry key '0x87' into index port dev. - */ -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -/* - * Disable configuration: pass exit key '0xAA' into index port dev. - */ -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/* - * Bring up early serial debugging output before the RAM is initialized. - */ -void f71869ad_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index 43a4397..3aeac56 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -32,6 +32,4 @@ #define F71869AD_BSEL 0x07 /* BSEL */ #define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ -void f71869ad_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc index 58ba5d5..ed40eb0 100644 --- a/src/superio/fintek/f71872/Makefile.inc +++ b/src/superio/fintek/f71872/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71872) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c deleted file mode 100644 index bbfc264..0000000 --- a/src/superio/fintek/f71872/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71872.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71872_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index fb80762..629d42d 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -32,6 +32,4 @@ #define F71872_VID 0x07 /* VID */ #define F71872_PM 0x0a /* ACPI/PME */ -void f71872_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71889/Makefile.inc b/src/superio/fintek/f71889/Makefile.inc index 9864140..5c39860 100644 --- a/src/superio/fintek/f71889/Makefile.inc +++ b/src/superio/fintek/f71889/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71889) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c deleted file mode 100644 index 5e11474..0000000 --- a/src/superio/fintek/f71889/early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71889.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71889_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 72148f4..e46ab99 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -34,6 +34,4 @@ #define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ #define F71889_VREF 0x0b /* Vref */ -void f71889_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71889_H */ diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index 8afb286..1700f7c 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c deleted file mode 100644 index 29b5f9d..0000000 --- a/src/superio/fintek/f81865f/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f81865f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f81865f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 99b7698..e3c204a 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -35,6 +35,4 @@ #define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F81865F_PME 0x0a /* Power Management Events (PME) */ -void f81865f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F81865_H */

1 0

New patch to review for coreboot: 86f602e build: allow building crossgcc when .config exists
by Patrick Georgi 26 Apr '14

26 Apr '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5584 -gerrit commit 86f602e30cd5e6a45243512e4dec0668ca6d922d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Apr 26 15:29:10 2014 +0200 build: allow building crossgcc when .config exists Under some circumstances the coreboot toolchain test prevented building crossgcc, which is counter-productive: If a .config file exists but no suitable .xcompile. Don't assume anything about the tree when building crossgcc or crosstools targets. Change-Id: I4d6e7a88908dc967342daf30df0fcbcc269ae63d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b709d14..8338161 100644 --- a/Makefile +++ b/Makefile @@ -97,7 +97,7 @@ ifeq ($(strip $(HAVE_DOTCONFIG)),) NOCOMPILE:=1 endif ifneq ($(MAKECMDGOALS),) -ifneq ($(filter %config %clean,$(MAKECMDGOALS)),) +ifneq ($(filter %config %clean cross%,$(MAKECMDGOALS)),) NOCOMPILE:=1 endif ifeq ($(MAKECMDGOALS), %clean)

1 0

Patch merged into coreboot/master: 4566d2e uart8250io: Fix build with DEBUG_SMI
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 4566d2e7cd32c1c2bdcc85a09c580e9f00f6b1dd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Apr 23 10:28:59 2014 +0300 uart8250io: Fix build with DEBUG_SMI Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/5574 for details. -gerrit

1 0

Patch merged into coreboot/master: 6bedc27 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 6bedc274266b8b326860c2ab35ce8cb9ec7ccbb0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5198 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/5198 for details. -gerrit

1 0

Patch merged into coreboot/master: f33782f lippert/hurricane-lx: Kconfig cleanup
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit f33782fb86ec2862a875843c19a923c19b90cd48 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Apr 18 15:07:56 2014 +0200 lippert/hurricane-lx: Kconfig cleanup A Kconfig option defined instead of selected that really comes from somewhere else. Change-Id: I8730d12ed053520b794655e943c93583c441f3f1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/5542 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5542 for details. -gerrit

1 0

Patch set updated for coreboot: a9feae5 superio/fintek/*: Factor out generic romstage component
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5575 -gerrit commit a9feae5d8f4856f6dd736e9ca96a61fe75e7dba7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 21:52:25 2014 +1000 superio/fintek/*: Factor out generic romstage component The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/romstage.c | 3 +- src/mainboard/amd/south_station/romstage.c | 3 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 3 +- src/mainboard/jetway/j7f2/romstage.c | 3 +- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 +- src/mainboard/jetway/pa78vm5/romstage.c | 3 +- src/mainboard/via/epia-m850/romstage.c | 5 +- src/superio/fintek/Kconfig | 47 ++++++++++++++--- src/superio/fintek/Makefile.inc | 3 ++ src/superio/fintek/common/early_serial.c | 72 ++++++++++++++++++++++++++ src/superio/fintek/common/fintek.h | 29 +++++++++++ src/superio/fintek/f71805f/Makefile.inc | 1 - src/superio/fintek/f71805f/early_serial.c | 48 ----------------- src/superio/fintek/f71805f/f71805f.h | 2 - src/superio/fintek/f71859/Makefile.inc | 1 - src/superio/fintek/f71859/early_serial.c | 48 ----------------- src/superio/fintek/f71859/f71859.h | 2 - src/superio/fintek/f71863fg/Makefile.inc | 1 - src/superio/fintek/f71863fg/early_serial.c | 48 ----------------- src/superio/fintek/f71863fg/f71863fg.h | 2 - src/superio/fintek/f71869ad/Makefile.inc | 1 - src/superio/fintek/f71869ad/early_serial.c | 68 ------------------------ src/superio/fintek/f71869ad/f71869ad.h | 2 - src/superio/fintek/f71872/Makefile.inc | 1 - src/superio/fintek/f71872/early_serial.c | 48 ----------------- src/superio/fintek/f71872/f71872.h | 2 - src/superio/fintek/f71889/Makefile.inc | 1 - src/superio/fintek/f71889/early_serial.c | 46 ---------------- src/superio/fintek/f71889/f71889.h | 2 - src/superio/fintek/f81865f/Makefile.inc | 1 - src/superio/fintek/f81865f/early_serial.c | 48 ----------------- src/superio/fintek/f81865f/f81865f.h | 2 - 32 files changed, 160 insertions(+), 391 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e082f60..81804a9 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,6 +31,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" @@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5614f88..5e70ecc 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,6 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> @@ -58,7 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 299ba61..612ff1a 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -41,6 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -97,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 37c3ab4..8455610 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -31,6 +31,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71805f/f71805f.h> #include <lib.h> #include <spd.h> @@ -90,7 +91,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - f71805f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3406edf..3e962d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -40,7 +40,8 @@ #include <cpu/amd/mtrr.h> #include <sb_cimx.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> -#include "superio/fintek/f71869ad/f71869ad.h" +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f71869ad/f71869ad.h> /* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" @@ -75,7 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index c082a67..044d0d8 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -42,6 +42,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -102,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 22f5ed6..9368028 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -36,9 +36,10 @@ #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" +#include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#define SERIAL_DEV PNP_DEV(0x4e, 0x10) +#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ void main(unsigned long bist) @@ -52,7 +53,7 @@ void main(unsigned long bist) vx900_enable_pci_config_space(); /* Serial console is easy to take care of */ - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); print_debug("Console initialized. \n"); diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index 938494a..2d16cae 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,17 +18,49 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config SUPERIO_FINTEK_F71805F +# Generic Fintek romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_FINTEK_COMMON_ROMSTAGE bool + +config SUPERIO_FINTEK_F71805F + bool "Fintek F7105F" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F7105F ramstage driver. + config SUPERIO_FINTEK_F71859 - bool + bool "Fintek F71859" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71859 ramstage driver. + config SUPERIO_FINTEK_F71863FG - bool + bool "Fintek F71863FG" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71863FG ramstage driver. + config SUPERIO_FINTEK_F71869AD - bool + bool "Fintek F71869AD" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71869AD ramstage driver. + config SUPERIO_FINTEK_F71872 - bool + bool "Fintek F71872" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71872 ramstage driver. + config SUPERIO_FINTEK_F71889 - bool + bool "Fintek F71889" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F71889 ramstage driver. + config SUPERIO_FINTEK_F81865F - bool + bool "Fintek F81865F" + select SUPERIO_FINTEK_COMMON_ROMSTAGE + help + Fintek F81865F ramstage driver. diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 541a893..1b11336 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic fintek pre-ram stage driver +romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += f71805f subdirs-y += f71859 subdirs-y += f71863fg diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c new file mode 100644 index 0000000..d74b786 --- /dev/null +++ b/src/superio/fintek/common/early_serial.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Fintek variant Super I/O chips. + * + * The following is derived directly from the vendor Fintek's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Fintek Super I/O's we are required to pass + * magic numbers `passwords keys`. + * + * FINTEK_ENTRY_KEY := enable configuration : 0x87 + * FINTEK_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "fintek.h" + +#define FINTEK_ENTRY_KEY 0x87 +#define FINTEK_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_ENTRY_KEY, port); + outb(FINTEK_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(FINTEK_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void fintek_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h new file mode 100644 index 0000000..a08cf92 --- /dev/null +++ b/src/superio/fintek/common/fintek.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_FINTEK_COMMON_ROMSTAGE_H +#define SUPERIO_FINTEK_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void fintek_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc index 22c01e0..4a13799 100644 --- a/src/superio/fintek/f71805f/Makefile.inc +++ b/src/superio/fintek/f71805f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c deleted file mode 100644 index b823a43..0000000 --- a/src/superio/fintek/f71805f/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71805f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71805f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 1033ea2..82f3869 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -38,6 +38,4 @@ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F71805F_PME 0x0a /* Power Management Events (PME) */ -void f71805f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71859/Makefile.inc b/src/superio/fintek/f71859/Makefile.inc index 8858811..fa63a1b 100644 --- a/src/superio/fintek/f71859/Makefile.inc +++ b/src/superio/fintek/f71859/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71859) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c deleted file mode 100644 index cb0d3de..0000000 --- a/src/superio/fintek/f71859/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones <marcj303(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71859.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71859_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index ab114a4..f0111bd 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -24,6 +24,4 @@ /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ -void f71859_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71859_H */ diff --git a/src/superio/fintek/f71863fg/Makefile.inc b/src/superio/fintek/f71863fg/Makefile.inc index 85ec530..e48b93a 100644 --- a/src/superio/fintek/f71863fg/Makefile.inc +++ b/src/superio/fintek/f71863fg/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.c diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c deleted file mode 100644 index 251f298..0000000 --- a/src/superio/fintek/f71863fg/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71863fg.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71863fg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index c29ddbe..a11e69f 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -33,6 +33,4 @@ #define F71863FG_SPI 0x08 /* SPI */ #define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ -void f71863fg_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71863FG_H */ diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 12efbeb..117239a 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/early_serial.c b/src/superio/fintek/f71869ad/early_serial.c deleted file mode 100644 index 8518400..0000000 --- a/src/superio/fintek/f71869ad/early_serial.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Pre-RAM driver for the Fintek F71869AD Super I/O chip. - * - * Derived from p.34 in vendor data-sheet: - * - * - default index port : 0x4E - * - default data port : 0x4F - * - * - enable configuration : 0x87 - * - disable configuration : 0xAA - * - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71869ad.h" - -/* - * Enable configuration: pass entry key '0x87' into index port dev. - */ -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -/* - * Disable configuration: pass exit key '0xAA' into index port dev. - */ -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/* - * Bring up early serial debugging output before the RAM is initialized. - */ -void f71869ad_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index 43a4397..3aeac56 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -32,6 +32,4 @@ #define F71869AD_BSEL 0x07 /* BSEL */ #define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ -void f71869ad_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc index 58ba5d5..ed40eb0 100644 --- a/src/superio/fintek/f71872/Makefile.inc +++ b/src/superio/fintek/f71872/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71872) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c deleted file mode 100644 index bbfc264..0000000 --- a/src/superio/fintek/f71872/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71872.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71872_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index fb80762..629d42d 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -32,6 +32,4 @@ #define F71872_VID 0x07 /* VID */ #define F71872_PM 0x0a /* ACPI/PME */ -void f71872_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71889/Makefile.inc b/src/superio/fintek/f71889/Makefile.inc index 9864140..5c39860 100644 --- a/src/superio/fintek/f71889/Makefile.inc +++ b/src/superio/fintek/f71889/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F71889) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c deleted file mode 100644 index 5e11474..0000000 --- a/src/superio/fintek/f71889/early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f71889.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f71889_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 72148f4..e46ab99 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -34,6 +34,4 @@ #define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ #define F71889_VREF 0x0b /* Vref */ -void f71889_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71889_H */ diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index 8afb286..1700f7c 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c deleted file mode 100644 index 29b5f9d..0000000 --- a/src/superio/fintek/f81865f/early_serial.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "f81865f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void f81865f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 99b7698..e3c204a 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -35,6 +35,4 @@ #define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F81865F_PME 0x0a /* Power Management Events (PME) */ -void f81865f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F81865_H */

1 0

Patch merged into coreboot/master: 6d51f6b superio/fintek/*: Fix header style
by gerrit＠coreboot.org 26 Apr '14

26 Apr '14

the following patch was just integrated into master: commit 6d51f6b2e8f4633a85d983b5bf8dcfc429df4c6c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 17:01:45 2014 +1000 superio/fintek/*: Fix header style Remove some redundant includes. Fix repetitiveness in include guards and strip some misplaced tabs for whitespaces. Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5572 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5572 for details. -gerrit

1 0

Patch set updated for coreboot: 57029d6 superio/fintek/*: Fix header style
by Edward O'Callaghan 26 Apr '14

26 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5572 -gerrit commit 57029d6e32c33335130d0fda567fd67f2cde0cb6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 17:01:45 2014 +1000 superio/fintek/*: Fix header style Remove some redundant includes. Fix repetitiveness in include guards and strip some misplaced tabs for whitespaces. Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71805f/f71805f.h | 14 +++++++------- src/superio/fintek/f71859/f71859.h | 6 +++--- src/superio/fintek/f71863fg/chip.h | 1 - src/superio/fintek/f71863fg/f71863fg.h | 20 ++++++++++---------- src/superio/fintek/f71869ad/chip.h | 1 - src/superio/fintek/f71869ad/f71869ad.h | 6 +++--- src/superio/fintek/f71872/f71872.h | 6 +++--- src/superio/fintek/f71889/chip.h | 1 - src/superio/fintek/f71889/f71889.h | 6 +++--- src/superio/fintek/f81865f/f81865f.h | 22 +++++++++++----------- 10 files changed, 40 insertions(+), 43 deletions(-) diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 6aae58f..1033ea2 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71805F_F71805F_H -#define SUPERIO_FINTEK_F71805F_F71805F_H +#ifndef SUPERIO_FINTEK_F71805F_H +#define SUPERIO_FINTEK_F71805F_H /* * Datasheet: @@ -32,12 +32,12 @@ /* Logical Device Numbers (LDN). */ #define F71805F_FDC 0x00 /* Floppy */ #define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ +#define F71805F_SP2 0x02 /* UART2 */ #define F71805F_PP 0x03 /* Parallel port */ -#define F71805F_HWM 0x04 /* Hardware monitor */ -#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71805F_PME 0x0a /* Power Management Events (PME) */ +#define F71805F_HWM 0x04 /* Hardware monitor */ +#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71805F_PME 0x0a /* Power Management Events (PME) */ void f71805f_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71805F_F71805F_H */ +#endif /* SUPERIO_FINTEK_F71805F_H */ diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index 580fa34..ab114a4 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -18,12 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71859_F71859_H -#define SUPERIO_FINTEK_F71859_F71859_H +#ifndef SUPERIO_FINTEK_F71859_H +#define SUPERIO_FINTEK_F71859_H /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ void f71859_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71859_F71859_H */ +#endif /* SUPERIO_FINTEK_F71859_H */ diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h index 4d2652e..a2c04d7 100644 --- a/src/superio/fintek/f71863fg/chip.h +++ b/src/superio/fintek/f71863fg/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71863FG_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71863fg_config { diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index 127a120..c29ddbe 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -18,21 +18,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71863FG_F71863FG_H -#define SUPERIO_FINTEK_F71863FG_F71863FG_H +#ifndef SUPERIO_FINTEK_F71863FG_H +#define SUPERIO_FINTEK_F71863FG_H /* Logical Device Numbers (LDN). */ #define F71863FG_FDC 0x00 /* Floppy */ #define F71863FG_SP1 0x01 /* UART1 */ -#define F71863FG_SP2 0x02 /* UART2 */ +#define F71863FG_SP2 0x02 /* UART2 */ #define F71863FG_PP 0x03 /* Parallel port */ -#define F71863FG_HWM 0x04 /* Hardware monitor */ -#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */ -#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71863FG_VID 0x07 /* VID */ -#define F71863FG_SPI 0x08 /* SPI */ -#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ +#define F71863FG_HWM 0x04 /* Hardware monitor */ +#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */ +#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71863FG_VID 0x07 /* VID */ +#define F71863FG_SPI 0x08 /* SPI */ +#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ void f71863fg_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71863FG_F71863FG_H */ +#endif /* SUPERIO_FINTEK_F71863FG_H */ diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..ea2ee6e 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index abc0260..43a4397 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71869AD_F71869AD_H -#define SUPERIO_FINTEK_F71869AD_F71869AD_H +#ifndef SUPERIO_FINTEK_F71869AD_H +#define SUPERIO_FINTEK_F71869AD_H /* Logical Device Numbers (LDN). */ #define F71869AD_FDC 0x00 /* Floppy */ @@ -34,4 +34,4 @@ void f71869ad_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71869AD_F71869AD_H */ +#endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index 577f8d1..fb80762 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71872_F71872_H -#define SUPERIO_FINTEK_F71872_F71872_H +#ifndef SUPERIO_FINTEK_F71872_H +#define SUPERIO_FINTEK_F71872_H /* Logical Device Numbers (LDN). */ #define F71872_FDC 0x00 /* Floppy */ @@ -34,4 +34,4 @@ void f71872_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71872_F71872_H */ +#endif /* SUPERIO_FINTEK_F71872_H */ diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h index 50312ad..e5a15d3 100644 --- a/src/superio/fintek/f71889/chip.h +++ b/src/superio/fintek/f71889/chip.h @@ -22,7 +22,6 @@ #define SUPERIO_FINTEK_F71889_CHIP_H #include <pc80/keyboard.h> -#include <device/device.h> struct superio_fintek_f71889_config { diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 6dc43b3..72148f4 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_FINTEK_F71889_F71889_H -#define SUPERIO_FINTEK_F71889_F71889_H +#ifndef SUPERIO_FINTEK_F71889_H +#define SUPERIO_FINTEK_F71889_H /* Logical Device Numbers (LDN). */ #define F71889_FDC 0x00 /* Floppy */ @@ -36,4 +36,4 @@ void f71889_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F71889_F71889_H */ +#endif /* SUPERIO_FINTEK_F71889_H */ diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index ccf41af..99b7698 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -22,19 +22,19 @@ * Datasheet: * - Name: F81865F/F-I */ -#ifndef SUPERIO_FINTEK_F81865_F81865_H -#define SUPERIO_FINTEK_F81865_F81865_H +#ifndef SUPERIO_FINTEK_F81865_H +#define SUPERIO_FINTEK_F81865_H /* Logical Device Numbers (LDN). */ -#define F81865F_FDC 0x00 /* Floppy */ -#define F81865F_SP1 0x10 /* UART1 */ -#define F81865F_SP2 0x11 /* UART2 */ -#define F81865F_PP 0x03 /* Parallel Port */ -#define F81865F_HWM 0x04 /* Hardware Monitor */ -#define F81865F_KBC 0x05 /* Keyboard/Mouse */ -#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F81865F_PME 0x0a /* Power Management Events (PME) */ +#define F81865F_FDC 0x00 /* Floppy */ +#define F81865F_SP1 0x10 /* UART1 */ +#define F81865F_SP2 0x11 /* UART2 */ +#define F81865F_PP 0x03 /* Parallel Port */ +#define F81865F_HWM 0x04 /* Hardware Monitor */ +#define F81865F_KBC 0x05 /* Keyboard/Mouse */ +#define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81865F_PME 0x0a /* Power Management Events (PME) */ void f81865f_enable_serial(device_t dev, u16 iobase); -#endif /* SUPERIO_FINTEK_F81865_F81865_H */ +#endif /* SUPERIO_FINTEK_F81865_H */

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coreboot-gerrit April 2014