coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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779 discussions

New patch to review for coreboot: 401f42e towiki.sh Move vendor link to the first column.
by Rudolf Marek 27 Apr '14

27 Apr '14

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5593 -gerrit commit 401f42efe5302f371829f047ae2e928764a9228f Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Apr 27 20:29:10 2014 +0200 towiki.sh Move vendor link to the first column. It is not easy to see that there are two links, one to coreboot wiki and second to the vendor page. This change moves the vendor page link to the vendor column, separating it nicely. Change-Id: I3063be476231d04f833350043010a6e0001697e7 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- util/board_status/to-wiki/towiki.sh | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 5244843..1778061 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -379,13 +379,14 @@ EOF esac echo "|- bgcolor=\"#$color\"" - echo "| $vendor_nice" - echo -n "| [[Board:$vendor/$board|$board_nice]]" + if [ -z "$board_url" ]; then - echo + echo "| $vendor_nice" else - echo " [$board_url vendor page]" + echo "| [$board_url $vendor_nice]" fi + echo "| [[Board:$vendor/$board|$board_nice]]" + if [ -z "$lastgood" ]; then echo "| style=\"background:red\" | Unknown" else

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New patch to review for coreboot: d86e54d mainboard/asrock/e350m1: Add Winbond SIO ACPI methods
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5592 -gerrit commit d86e54d483d4d102b0cf088d319d6ca1d95d680d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 02:30:43 2014 +1000 mainboard/asrock/e350m1: Add Winbond SIO ACPI methods Change-Id: Ic4bdf0ff6f91139b2fd89d3444284187cc6405c9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/acpi/superio.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asrock/e350m1/acpi/superio.asl b/src/mainboard/asrock/e350m1/acpi/superio.asl index 7d8d9df..cfb3d7d 100644 --- a/src/mainboard/asrock/e350m1/acpi/superio.asl +++ b/src/mainboard/asrock/e350m1/acpi/superio.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,4 +17,4 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* No SuperIO device or functionality yet */ +#include "../../../../superio/winbond/w83627hf/acpi/superio.asl"

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New patch to review for coreboot: a8f7d02 mainboard/asrock/e350m1: Avoid including early_serial.c
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5591 -gerrit commit a8f7d02b33732814e90d223c907a71c6fbec63ed Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 02:07:32 2014 +1000 mainboard/asrock/e350m1: Avoid including early_serial.c Using generic winbond romstage serial init symbols instead of model specific implementation. We do this on a case by case basis as some boards are ROMCC and so need to #include .c files. This is a step to migrating non-romcc boards to a more generic superio framework. Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf850a3..7bf5359 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,7 +31,8 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -61,7 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }

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New patch to review for coreboot: 70f83e6 mainboard/asrock/e350m1: Enable PS/2 ACPI SIO methods
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5590 -gerrit commit 70f83e6c410ae16e382fbcd463df26da440f07f5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 01:31:11 2014 +1000 mainboard/asrock/e350m1: Enable PS/2 ACPI SIO methods Change-Id: I93358f38cfef4550a4d545c72305120a0e4fded8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/acpi/superio.asl | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asrock/e350m1/acpi/superio.asl b/src/mainboard/asrock/e350m1/acpi/superio.asl index 7d8d9df..6dcb877 100644 --- a/src/mainboard/asrock/e350m1/acpi/superio.asl +++ b/src/mainboard/asrock/e350m1/acpi/superio.asl @@ -1,7 +1,9 @@ /* + * Super I/O devices + * * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,4 +19,4 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* No SuperIO device or functionality yet */ +#include "../../../../drivers/pc80/ps2_controller.asl"

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Patch set updated for coreboot: f2352d3 superio/winbond/w83627ehg: Convert romstage to generic component
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5589 -gerrit commit f2352d3947103291afc6a0331b49653c197dc806 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 23:28:31 2014 +1000 superio/winbond/w83627ehg: Convert romstage to generic component Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 5 +++-- src/mainboard/asus/a8v-e_se/romstage.c | 10 ++-------- src/mainboard/ibase/mb899/romstage.c | 1 + src/mainboard/iei/pm-lx-800-r11/romstage.c | 3 ++- src/mainboard/msi/ms7260/romstage.c | 3 ++- src/mainboard/msi/ms9282/romstage.c | 3 ++- src/mainboard/msi/ms9652_fam10/romstage.c | 3 ++- src/superio/winbond/w83627ehg/early_serial.c | 10 ---------- src/superio/winbond/w83627ehg/w83627ehg.h | 7 +++---- 9 files changed, 17 insertions(+), 28 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index efc4ac7..223a230 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -167,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 19f5686..abe5f84 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -166,13 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); } - // FIXME why is this executed again? ---> - sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_rom_decode(); - // <--- FIXME why is this executed again? - print_info("now booting... real_main\n"); if (bist == 0) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 64df82e..d50f8c6 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <superio/winbond/common/winbond.h> #include "superio/winbond/w83627ehg/w83627ehg.h" #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f996301..bf34e9a 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -32,6 +32,7 @@ #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> #include <southbridge/amd/cs5536/early_setup.c> +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> @@ -63,7 +64,7 @@ void main(unsigned long bist) cs5536_early_setup(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 68feb3b..fd8fbfb 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -37,6 +37,7 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 19592f3..3048542 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -37,6 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include <spd.h> @@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ad7dcde..3993bae 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -39,6 +39,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); pnp_exit_ext_func_mode(SERIAL_DEV); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 84eb127..346d6cf 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -35,13 +35,3 @@ void pnp_exit_ext_func_mode(device_t dev) u16 port = dev >> 8; outb(0xaa, port); } - -void w83627ehg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index e574cf3..02041fc 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H -#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H +#ifndef SUPERIO_WINBOND_W83627EHG_H +#define SUPERIO_WINBOND_W83627EHG_H #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel port */ @@ -57,10 +57,9 @@ #if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); -void w83627ehg_enable_serial(device_t dev, u16 iobase); #endif void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev); -#endif /* SUPERIO_WINBOND_W83627EHG_W83627EHG_H */ +#endif /* SUPERIO_WINBOND_W83627EHG_H */

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Patch set updated for coreboot: 74e0feb superio/winbond/*: Provide common romstage component
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5587 -gerrit commit 74e0febecac494c47d3a7a7500d25c7a2212ae22 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 22:41:31 2014 +1000 superio/winbond/*: Provide common romstage component Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/winbond/Kconfig | 21 +++++++++ src/superio/winbond/Makefile.inc | 3 ++ src/superio/winbond/common/early_serial.c | 72 +++++++++++++++++++++++++++++++ src/superio/winbond/common/winbond.h | 29 +++++++++++++ 4 files changed, 125 insertions(+) diff --git a/src/superio/winbond/Kconfig b/src/superio/winbond/Kconfig index 364b57c..1a0e6a8 100644 --- a/src/superio/winbond/Kconfig +++ b/src/superio/winbond/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,19 +18,39 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic Winbond romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_WINBOND_COMMON_ROMSTAGE + bool + config SUPERIO_WINBOND_W83627DHG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627EHG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627HF bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627THG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627UHG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83697HF bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83977F bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83977TF bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index 9701baf..6d14f33 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic winbond pre-ram stage driver +romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += w83627dhg subdirs-y += w83627ehg subdirs-y += w83627hf diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c new file mode 100644 index 0000000..ab6ac14 --- /dev/null +++ b/src/superio/winbond/common/early_serial.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips. + * + * The following is derived directly from the vendor Winbond's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Winbond Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * WINBOUND_ENTRY_KEY := enable configuration : 0x87 + * WINBOUND_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then writing to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "winbond.h" + +#define WINBOND_ENTRY_KEY 0x87 +#define WINBOND_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(WINBOND_ENTRY_KEY, port); + outb(WINBOND_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(WINBOND_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void winbond_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h new file mode 100644 index 0000000..20eefc8 --- /dev/null +++ b/src/superio/winbond/common/winbond.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_WINBOND_COMMON_ROMSTAGE_H +#define SUPERIO_WINBOND_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void winbond_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_COMMON_ROMSTAGE_H */

1 0

Patch set updated for coreboot: e61a918 superio/winbond/w83627dhg: Convert romstage to generic component
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5588 -gerrit commit e61a918ec31ea8d77c73bf6b0cce4fbb6f956320 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 22:51:40 2014 +1000 superio/winbond/w83627dhg: Convert romstage to generic component Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/939a785gmh/romstage.c | 5 +++-- src/mainboard/kontron/kt690/romstage.c | 5 +++-- src/mainboard/lippert/toucan-af/romstage.c | 5 +++-- src/mainboard/supermicro/h8qgi/romstage.c | 3 ++- src/mainboard/supermicro/h8scm/romstage.c | 3 ++- src/mainboard/tyan/s8226/romstage.c | 5 +++-- src/superio/winbond/w83627dhg/early_serial.c | 10 ---------- src/superio/winbond/w83627dhg/w83627dhg.h | 7 +++---- 8 files changed, 19 insertions(+), 24 deletions(-) diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index edc5830..ce0a6ac 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -37,7 +37,8 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); sio_init(); - w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 52e54d4..4e45dc4 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -38,7 +38,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/amd/mtrr.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 4f62268..751dedb 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -31,7 +31,8 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ea4ed8e..4d066b7 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -31,7 +31,8 @@ #include <nb_cimx.h> #include <sb_cimx.h> #include "superio/nuvoton/wpcm450/wpcm450.h" -#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 9ee1dfa..e1e8799 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -33,7 +33,8 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" #include "superio/nuvoton/wpcm450/wpcm450.h" -#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a6c33e8..9483876 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -31,7 +31,8 @@ #include <nb_cimx.h> #include <sb_cimx.h> #include "superio/nuvoton/wpcm450/wpcm450.h" -#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" @@ -54,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ w83627dhg_set_clksel_48(DUMMY_DEV); - w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index ec9e81e..67aaa93 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -37,16 +37,6 @@ void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -void w83627dhg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - /** * Select Pin 89, Pin 90 function as I2C interface SDA, SCL. * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 9e83d34..08ea04f 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627DHG_W83627DHG_H -#define SUPERIO_WINBOND_W83627DHG_W83627DHG_H +#ifndef SUPERIO_WINBOND_W83627DHG_H +#define SUPERIO_WINBOND_W83627DHG_H #define W83627DHG_FDC 0 /* Floppy */ #define W83627DHG_PP 1 /* Parallel port */ @@ -54,8 +54,7 @@ void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev); -void w83627dhg_enable_serial(device_t dev, u16 iobase); void w83627dhg_enable_i2c(device_t dev); void w83627dhg_set_clksel_48(device_t dev); -#endif +#endif /* SUPERIO_WINBOND_W83627DHG_H */

1 0

Patch set updated for coreboot: d9ff58e superio/winbond/w83627ehg: Convert romstage to generic component
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5589 -gerrit commit d9ff58eb72fdcf756f4558180086aee63584a109 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 23:28:31 2014 +1000 superio/winbond/w83627ehg: Convert romstage to generic component Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 3 ++- src/mainboard/asus/a8v-e_se/romstage.c | 10 ++-------- src/mainboard/ibase/mb899/romstage.c | 1 + src/mainboard/iei/pm-lx-800-r11/romstage.c | 3 ++- src/mainboard/msi/ms7260/romstage.c | 3 ++- src/mainboard/msi/ms9282/romstage.c | 3 ++- src/mainboard/msi/ms9652_fam10/romstage.c | 3 ++- src/superio/winbond/w83627ehg/early_serial.c | 10 ---------- src/superio/winbond/w83627ehg/w83627ehg.h | 7 +++---- 9 files changed, 16 insertions(+), 27 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index efc4ac7..6a90fc1 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 19f5686..abe5f84 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -166,13 +167,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); } - // FIXME why is this executed again? ---> - sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_rom_decode(); - // <--- FIXME why is this executed again? - print_info("now booting... real_main\n"); if (bist == 0) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 64df82e..d50f8c6 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <superio/winbond/common/winbond.h> #include "superio/winbond/w83627ehg/w83627ehg.h" #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f996301..bf34e9a 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -32,6 +32,7 @@ #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> #include <southbridge/amd/cs5536/early_setup.c> +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> @@ -63,7 +64,7 @@ void main(unsigned long bist) cs5536_early_setup(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 68feb3b..737f6d9 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -37,6 +37,7 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 19592f3..3048542 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -37,6 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include <spd.h> @@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ad7dcde..3993bae 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -39,6 +39,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); pnp_exit_ext_func_mode(SERIAL_DEV); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 84eb127..346d6cf 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -35,13 +35,3 @@ void pnp_exit_ext_func_mode(device_t dev) u16 port = dev >> 8; outb(0xaa, port); } - -void w83627ehg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index e574cf3..02041fc 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H -#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H +#ifndef SUPERIO_WINBOND_W83627EHG_H +#define SUPERIO_WINBOND_W83627EHG_H #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel port */ @@ -57,10 +57,9 @@ #if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); -void w83627ehg_enable_serial(device_t dev, u16 iobase); #endif void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev); -#endif /* SUPERIO_WINBOND_W83627EHG_W83627EHG_H */ +#endif /* SUPERIO_WINBOND_W83627EHG_H */

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Patch set updated for coreboot: 780f431 superio/winbond/w83627ehg: Convert romstage to generic component
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5589 -gerrit commit 780f431ab134ef5b3480260bb5bdaf691551b5ea Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 23:28:31 2014 +1000 superio/winbond/w83627ehg: Convert romstage to generic component Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 3 ++- src/mainboard/asus/a8v-e_se/romstage.c | 3 ++- src/mainboard/ibase/mb899/romstage.c | 1 + src/mainboard/iei/pm-lx-800-r11/romstage.c | 3 ++- src/mainboard/msi/ms7260/romstage.c | 3 ++- src/mainboard/msi/ms9282/romstage.c | 3 ++- src/mainboard/msi/ms9652_fam10/romstage.c | 3 ++- src/superio/winbond/common/winbond.h | 29 ++++++++++++++++++++++++++++ src/superio/winbond/common/winbound.h | 29 ---------------------------- src/superio/winbond/w83627ehg/early_serial.c | 10 ---------- src/superio/winbond/w83627ehg/w83627ehg.h | 7 +++---- 11 files changed, 45 insertions(+), 49 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index efc4ac7..6a90fc1 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 19f5686..0ea9aa6 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 64df82e..d50f8c6 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <superio/winbond/common/winbond.h> #include "superio/winbond/w83627ehg/w83627ehg.h" #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f996301..bf34e9a 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -32,6 +32,7 @@ #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> #include <southbridge/amd/cs5536/early_setup.c> +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> @@ -63,7 +64,7 @@ void main(unsigned long bist) cs5536_early_setup(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 68feb3b..3c5331f 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -37,6 +37,7 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 19592f3..513ac77 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -37,6 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include <spd.h> @@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ad7dcde..44bfea5 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -39,6 +39,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); pnp_exit_ext_func_mode(SERIAL_DEV); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h new file mode 100644 index 0000000..71def7f --- /dev/null +++ b/src/superio/winbond/common/winbond.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_WINBOUND_COMMON_ROMSTAGE_H +#define SUPERIO_WINBOUND_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void winbound_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOUND_COMMON_ROMSTAGE_H */ diff --git a/src/superio/winbond/common/winbound.h b/src/superio/winbond/common/winbound.h deleted file mode 100644 index 71def7f..0000000 --- a/src/superio/winbond/common/winbound.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_WINBOUND_COMMON_ROMSTAGE_H -#define SUPERIO_WINBOUND_COMMON_ROMSTAGE_H - -#include <arch/io.h> -#include <stdint.h> - -void winbound_enable_serial(device_t dev, u16 iobase); - -#endif /* SUPERIO_WINBOUND_COMMON_ROMSTAGE_H */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 84eb127..346d6cf 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -35,13 +35,3 @@ void pnp_exit_ext_func_mode(device_t dev) u16 port = dev >> 8; outb(0xaa, port); } - -void w83627ehg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index e574cf3..02041fc 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H -#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H +#ifndef SUPERIO_WINBOND_W83627EHG_H +#define SUPERIO_WINBOND_W83627EHG_H #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel port */ @@ -57,10 +57,9 @@ #if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); -void w83627ehg_enable_serial(device_t dev, u16 iobase); #endif void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev); -#endif /* SUPERIO_WINBOND_W83627EHG_W83627EHG_H */ +#endif /* SUPERIO_WINBOND_W83627EHG_H */

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New patch to review for coreboot: ac14bd7 superio/winbond/w83627ehg: Convert romstage to generic component
by Edward O'Callaghan 27 Apr '14

27 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5589 -gerrit commit ac14bd78ae74bbff9d83caf800d72131a3dd7e80 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 23:28:31 2014 +1000 superio/winbond/w83627ehg: Convert romstage to generic component Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_se/romstage.c | 3 ++- src/mainboard/ibase/mb899/romstage.c | 1 + src/mainboard/iei/pm-lx-800-r11/romstage.c | 3 ++- src/mainboard/msi/ms7260/romstage.c | 3 ++- src/mainboard/msi/ms9282/romstage.c | 3 ++- src/mainboard/msi/ms9652_fam10/romstage.c | 3 ++- src/superio/winbond/w83627ehg/early_serial.c | 10 ---------- src/superio/winbond/w83627ehg/w83627ehg.h | 7 +++---- 8 files changed, 14 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 19f5686..0ea9aa6 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,6 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ @@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 64df82e..d50f8c6 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <cbmem.h> +#include <superio/winbond/common/winbond.h> #include "superio/winbond/w83627ehg/w83627ehg.h" #include <pc80/mc146818rtc.h> #include <console/console.h> diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f996301..bf34e9a 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -32,6 +32,7 @@ #include <southbridge/amd/cs5536/cs5536.h> #include <southbridge/amd/cs5536/early_smbus.c> #include <southbridge/amd/cs5536/early_setup.c> +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <northbridge/amd/lx/raminit.h> @@ -63,7 +64,7 @@ void main(unsigned long bist) cs5536_early_setup(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 68feb3b..3c5331f 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -37,6 +37,7 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -122,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 19592f3..513ac77 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -37,6 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include <spd.h> @@ -139,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ad7dcde..44bfea5 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -39,6 +39,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -126,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); pnp_exit_ext_func_mode(SERIAL_DEV); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbound_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 84eb127..346d6cf 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -35,13 +35,3 @@ void pnp_exit_ext_func_mode(device_t dev) u16 port = dev >> 8; outb(0xaa, port); } - -void w83627ehg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index e574cf3..02041fc 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H -#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H +#ifndef SUPERIO_WINBOND_W83627EHG_H +#define SUPERIO_WINBOND_W83627EHG_H #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel port */ @@ -57,10 +57,9 @@ #if defined(__PRE_RAM__) void w83627ehg_enable_dev(device_t dev, u16 iobase); void w83627ehg_disable_dev(device_t dev); -void w83627ehg_enable_serial(device_t dev, u16 iobase); #endif void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev); -#endif /* SUPERIO_WINBOND_W83627EHG_W83627EHG_H */ +#endif /* SUPERIO_WINBOND_W83627EHG_H */

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coreboot-gerrit April 2014