April 2014 - coreboot-gerrit - mail.coreboot.org

Patch merged into coreboot/master: 2458f42 AMD: Add common header file for CAR setup
by gerrit＠coreboot.org April 28, 2014

April 28, 2014

the following patch was just integrated into master: commit 2458f42b27e6525f4131899ef36f21d0f7dace1a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 22 16:46:31 2014 +0300 AMD: Add common header file for CAR setup Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4683 for details. -gerrit

1 0

Patch set updated for coreboot: 762d3e0 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments
by Ronald G. Minnich April 28, 2014

April 28, 2014

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5388 -gerrit commit 762d3e055bd8099f1f9de98499fb2ed39c93a290 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 16 00:15:57 2014 +0100 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments cbfstool fails to built under 32-bit platforms since commit aa2f739a cbfs: fix issues with word size and endianness. due to the use of '%ld' format specifier on size_t, which on these platforms is only 32-bit. Use the length modifier `z` for size_t arguments, and cast to size_t where appropriate. Change-Id: Id84a20fbf237376a31f7e4816bd139463800c977 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/cbfs-mkstage.c | 4 ++-- util/cbfstool/elfheaders.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 6aa3746..2a92c9f 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -132,8 +132,8 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, continue; if (input->size < (phdr[i].p_offset + phdr[i].p_filesz)){ ERROR("Underflow copying out the segment." - "File has %ld bytes left, segment end is %ld\n", - input->size, phdr[i].p_offset + phdr[i].p_filesz); + "File has %zu bytes left, segment end is %zu\n", + input->size, (size_t)(phdr[i].p_offset + phdr[i].p_filesz)); return -1; } memcpy(buffer + (l_start - data_start), diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index d217aac..5b5cf94 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -147,7 +147,7 @@ check_size(const struct buffer *b, size_t offset, size_t size, const char *desc) if (offset >= buffer_size(b) || (offset + size) > buffer_size(b)) { ERROR("The file is not large enough for the '%s'. " - "%ld bytes @ offset %zu, input %zu bytes.\n", + "%zu bytes @ offset %zu, input %zu bytes.\n", desc, size, offset, buffer_size(b)); return -1; }

1 0

Patch set updated for coreboot: ac3d691 AMD: Add common header file for CAR setup
by Kyösti Mälkki April 28, 2014

April 28, 2014

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4683 -gerrit commit ac3d69153a3c229bf7b18bbad655bea4b21d5d39 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 22 16:46:31 2014 +0300 AMD: Add common header file for CAR setup Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 6 +----- src/include/cpu/amd/car.h | 15 +++++++++++++++ src/include/lib.h | 8 -------- src/mainboard/amd/dinar/romstage.c | 3 +-- src/mainboard/amd/inagua/romstage.c | 1 + src/mainboard/amd/olivehill/romstage.c | 3 +-- src/mainboard/amd/parmer/romstage.c | 3 +-- src/mainboard/amd/persimmon/romstage.c | 3 +-- src/mainboard/amd/south_station/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 3 +-- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 1 + src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 3 +-- src/mainboard/asus/f2a85-m/romstage.c | 4 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo/romstage.c | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 5 +---- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 4 +--- src/mainboard/lippert/frontrunner-af/romstage.c | 3 +-- src/mainboard/lippert/toucan-af/romstage.c | 3 +-- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- 26 files changed, 39 insertions(+), 49 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 9712785..51caec5 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -5,6 +5,7 @@ #include <arch/stages.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/car.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -75,8 +76,6 @@ static void vErrata343(void) #endif } -void cache_as_ram_switch_stack(void *resume_backup_memory); - void post_cache_as_ram(void) { void *resume_backup_memory = NULL; @@ -113,9 +112,6 @@ void post_cache_as_ram(void) } void -cache_as_ram_new_stack (void *resume_backup_memory); - -void cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) { /* We can put data to stack again */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h new file mode 100644 index 0000000..a001c93 --- /dev/null +++ b/src/include/cpu/amd/car.h @@ -0,0 +1,15 @@ +#ifndef _CPU_AMD_CAR_H +#define _CPU_AMD_CAR_H + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void done_cache_as_ram_main(void); +void post_cache_as_ram(void); + +void cache_as_ram_switch_stack(void *resume_backup_memory); +void cache_as_ram_new_stack(void *resume_backup_memory); + +#if CONFIG_CPU_AMD_AGESA +void disable_cache_as_ram(void); +#endif + +#endif diff --git a/src/include/lib.h b/src/include/lib.h index db2e9c7..c272eb5 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -50,14 +50,6 @@ int checkstack(void *top_of_stack, int core); extern unsigned char _estack[]; #endif -/* Defined in romstage.c */ -#if CONFIG_CPU_AMD_GEODE_LX -void cache_as_ram_main(void); -#else -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#endif -void post_cache_as_ram(void); - /* Defined in src/lib/hexdump.c */ void hexdump(const void *memory, size_t length); void hexdump32(char LEVEL, const void *d, int len); diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 91b385f..776ecd5 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 718d2b2..98c74d6 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9431d4a..6422393 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 202442c..a5d041f 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 81804a9..47c03ec 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> @@ -43,8 +44,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5e70ecc..be340aa 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 6bf8ac6..9c3cf5b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index f6204b9..58b88d0 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" @@ -38,7 +39,6 @@ #include <arch/cpu.h> #include "platform_cfg.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 6868755..0a7ef7c 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf850a3..cbfa743 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627hf/early_serial.c" @@ -38,7 +39,6 @@ #include <sb_cimx.h> #include "SBPLATFORM.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1) diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 9b069b7..59d95f9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index ee9983d..4aa4b04 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -26,6 +26,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/amd/agesa/s3_resume.h> +#include "cpu/amd/car.h" #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> @@ -40,9 +41,6 @@ #include <drivers/pc80/i8259.c> #include <superio/ite/it8712f/early_serial.c> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index cc2fc4b..b96f8ae 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -8,6 +8,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -75,6 +76,5 @@ void main(unsigned long bist) /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 705d429..f639d1f 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "drivers/pc80/i8254.c" @@ -45,8 +46,6 @@ #define MSR_MTRR_VARIABLE_MASK6 0x020D #define MSR_PSTATE_CONTROL 0xC0010062 -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index dd19679..24751f4 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -27,6 +27,7 @@ #include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> +#include <cpu/amd/car.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <stdint.h> @@ -36,10 +37,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3e962d3..848faf7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -38,6 +38,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/car.h> #include <sb_cimx.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <superio/fintek/common/fintek.h> @@ -47,9 +48,6 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 9ecd087..16fb8ab 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 4f62268..9f8cf1a 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627dhg/w83627dhg.h" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index c3f964d..1c4ae09 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -162,6 +163,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 6946900..18453ac 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -186,6 +187,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ea4ed8e..acb05ab 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -33,7 +34,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 9ee1dfa..8801c45 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a6c33e8..49361a8 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0)

1 0

Patch set updated for coreboot: 9615fd2 crossgcc: Support OSX 10.9 built-in tar utility program.
by Andrew Wu April 28, 2014

April 28, 2014

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5598 -gerrit commit 9615fd295c53143093ffd2277ff11fa4b7bed891 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Mon Apr 28 18:13:44 2014 +0800 crossgcc: Support OSX 10.9 built-in tar utility program. Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in tar program is bsdtar 2.8.3. bsdtar can build crossgcc toolchain. Modify buildgcc to support tar in OSX 10.9 (uname = Darwin). Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- util/crossgcc/buildgcc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c6d7183..5aa98d5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -105,8 +105,9 @@ searchgnu() fi fi done - # A workaround for XxxBSD, whose nongnu patch and tar also work. - if [ $UNAME = "FreeBSD" -o $UNAME = "NetBSD" ]; then + # A workaround for OSX 10.9 and some BSDs, whose nongnu + # patch and tar also work. + if [ $UNAME = "Darwin" -o $UNAME = "FreeBSD" -o $UNAME = "NetBSD" ]; then if [ $1 != "make" ]; then if test -x "`which $1 2>/dev/null`"; then echo $1

1 0

Patch set updated for coreboot: 8d9c5c3 crossgcc: Support OSX 10.9 built-in tar utility program.
by Andrew Wu April 28, 2014

April 28, 2014

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5598 -gerrit commit 8d9c5c3f88ba322691b47805261060dec4713275 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Mon Apr 28 18:13:44 2014 +0800 crossgcc: Support OSX 10.9 built-in tar utility program. Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in tar program is bsdtar 2.8.3. bsdtar can building crossgcc toolchain. Modify buildgcc to support tar in OSX 10.9 (uname = Darwin). Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- util/crossgcc/buildgcc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c6d7183..5aa98d5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -105,8 +105,9 @@ searchgnu() fi fi done - # A workaround for XxxBSD, whose nongnu patch and tar also work. - if [ $UNAME = "FreeBSD" -o $UNAME = "NetBSD" ]; then + # A workaround for OSX 10.9 and some BSDs, whose nongnu + # patch and tar also work. + if [ $UNAME = "Darwin" -o $UNAME = "FreeBSD" -o $UNAME = "NetBSD" ]; then if [ $1 != "make" ]; then if test -x "`which $1 2>/dev/null`"; then echo $1

1 0

New patch to review for coreboot: 302665b crossgcc: Support OSX 10.9 built-in tar utility program.
by Andrew Wu April 28, 2014

April 28, 2014

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5598 -gerrit commit 302665be8d4627e3f164a6bfb11e9a7a84d4eb6b Author: Andrew Wu <arw(a)dmp.com.tw> Date: Mon Apr 28 18:13:44 2014 +0800 crossgcc: Support OSX 10.9 built-in tar utility program. Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in tar program is bsdtar 2.8.3. bsdtar can building crossgcc toolchain. Modify buildgcc to support tar in OSX 10.9 (uname = Darwin). Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c6d7183..1ffbfa2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -106,7 +106,7 @@ searchgnu() fi done # A workaround for XxxBSD, whose nongnu patch and tar also work. - if [ $UNAME = "FreeBSD" -o $UNAME = "NetBSD" ]; then + if [ $UNAME = "FreeBSD" -o $UNAME = "NetBSD" -o $UNAME = "Darwin" ]; then if [ $1 != "make" ]; then if test -x "`which $1 2>/dev/null`"; then echo $1

1 0

Patch set updated for coreboot: a516948 superio/winbond/*: Provide common romstage component
by Edward O'Callaghan April 28, 2014

April 28, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5587 -gerrit commit a516948e4db4e24574ad72564857040bdb9ba612 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 22:41:31 2014 +1000 superio/winbond/*: Provide common romstage component Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/winbond/Kconfig | 21 +++++++++ src/superio/winbond/Makefile.inc | 3 ++ src/superio/winbond/common/early_serial.c | 72 +++++++++++++++++++++++++++++++ src/superio/winbond/common/winbond.h | 29 +++++++++++++ 4 files changed, 125 insertions(+) diff --git a/src/superio/winbond/Kconfig b/src/superio/winbond/Kconfig index 364b57c..1a0e6a8 100644 --- a/src/superio/winbond/Kconfig +++ b/src/superio/winbond/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,19 +18,39 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic Winbond romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_WINBOND_COMMON_ROMSTAGE + bool + config SUPERIO_WINBOND_W83627DHG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627EHG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627HF bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627THG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83627UHG bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83697HF bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83977F bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83977TF bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index 9701baf..6d14f33 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic winbond pre-ram stage driver +romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += w83627dhg subdirs-y += w83627ehg subdirs-y += w83627hf diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c new file mode 100644 index 0000000..747cc45 --- /dev/null +++ b/src/superio/winbond/common/early_serial.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips. + * + * The following is derived directly from the vendor Winbond's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Winbond Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * WINBOUND_ENTRY_KEY := enable configuration : 0x87 + * WINBOUND_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then write to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "winbond.h" + +#define WINBOND_ENTRY_KEY 0x87 +#define WINBOND_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(WINBOND_ENTRY_KEY, port); + outb(WINBOND_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(WINBOND_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void winbond_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h new file mode 100644 index 0000000..20eefc8 --- /dev/null +++ b/src/superio/winbond/common/winbond.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_WINBOND_COMMON_ROMSTAGE_H +#define SUPERIO_WINBOND_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +void winbond_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_COMMON_ROMSTAGE_H */

1 0

New patch to review for coreboot: 4771d61 mainboard/*: Avoid including early_serial.c
by Edward O'Callaghan April 28, 2014

April 28, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5597 -gerrit commit 4771d6131c974580a490701669839f34fffb5281 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 18:07:33 2014 +1000 mainboard/*: Avoid including early_serial.c NOTFORMERGE Following the reasoning of: HASHHERE mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/rumba/romstage.c | 5 +++-- src/mainboard/asus/dsbf/romstage.c | 5 +++-- src/mainboard/lippert/frontrunner/romstage.c | 5 +++-- src/mainboard/newisys/khepri/romstage.c | 7 ++++--- src/mainboard/tyan/s2735/romstage.c | 7 ++++--- src/mainboard/tyan/s2850/romstage.c | 7 ++++--- src/mainboard/tyan/s2875/romstage.c | 7 ++++--- src/mainboard/tyan/s2880/romstage.c | 7 ++++--- src/mainboard/tyan/s2881/romstage.c | 7 ++++--- src/mainboard/tyan/s2882/romstage.c | 7 ++++--- src/mainboard/tyan/s2885/romstage.c | 7 ++++--- src/mainboard/tyan/s2891/romstage.c | 5 +++-- src/mainboard/tyan/s2892/romstage.c | 5 +++-- src/mainboard/tyan/s4880/romstage.c | 7 ++++--- src/mainboard/tyan/s4882/romstage.c | 7 ++++--- 15 files changed, 55 insertions(+), 40 deletions(-) diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index cec7c36..c5a3fc3 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -4,7 +4,8 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> @@ -38,7 +39,7 @@ void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5536_early_setup(); diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index f4e65cb..e013371 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -29,7 +29,8 @@ #include <lib.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <superio/winbond/w83627hf/early_serial.c> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" @@ -116,7 +117,7 @@ void main(unsigned long bist) i5000_lpc_config(); - w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); + winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index bdbf059..92a3a99 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -5,7 +5,8 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> @@ -80,7 +81,7 @@ void main(unsigned long bist) SystemPreInit(); msr_init(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5535_early_setup(); diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 652104a..b34882e 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -20,7 +20,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 4e71559..600d806 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -11,7 +11,8 @@ #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "northbridge/intel/e7501/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -47,8 +48,8 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 301f81c..952b19d 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -75,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 7c9f93a..8f87257 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 13cc01e..873652b 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index dad2b6b..c020f3e 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -73,8 +74,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 13cc01e..873652b 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index a2dc990..df602ea 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -71,8 +72,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index aa0385b..e97b026 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -16,7 +16,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -94,7 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 5d6ff2a..57da072 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -16,7 +16,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 2b6470c..543fcf0 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -131,8 +132,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 60dbdf8..b4100fb 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -13,7 +13,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -110,8 +111,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

1 0

Patch set updated for coreboot: 4687ca1 mainboard/asrock/e350m1: Avoid including early_serial.c
by Edward O'Callaghan April 28, 2014

April 28, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5591 -gerrit commit 4687ca1f6108643295a30b8c742464c425104e75 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 02:07:32 2014 +1000 mainboard/asrock/e350m1: Avoid including early_serial.c Use generic winbond romstage serial init symbols instead of model specific implementation. We do this on a case by case basis as some boards are ROMCC and so need to #include .c files. This is a step to migrate non-romcc boards to a more generic superio framework. Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/romstage.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf850a3..7bf5359 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,7 +31,8 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -61,7 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }

1 0

Patch set updated for coreboot: 1728a75 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4
by Paul Menzel April 28, 2014

April 28, 2014

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit 1728a75e7bdf63d0f7890dbc7aed0fb2b8c8a0b5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4 SeaBIOS 1.7.4 was released in December 2013 [1] and, besides other things, supports writing debug messages to CBMEM console. The new SeaBIOS Kconfig option `DEBUG_COREBOOT` has to be added to the SeaBIOS configuration file `.config` as otherwise the SeaBIOS build from within coreboot (`PAYLOAD_SEABIOS`) is interrupted as it is detected as a new option. This option was already added and enabled in commit 7c1a49bc [1] SeaBIOS: have coreboot pass the choice to run optionroms in parallel so SeaBIOS messages are now written to the CBMEM console. Successfully tested on the Asus M2V-MX SE. [1] http://seabios.org/Releases [2] http://review.coreboot.org/5443 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..291b166 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -617,7 +617,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

1 0