coreboot-gerrit April 2014

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Patch set updated for coreboot: abc6e96 Declare recovery and developer modes outside ChromeOS
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4308 -gerrit commit abc6e96927bdebc6be4f6f7ad8a0ed13936333e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 28 18:11:49 2013 +0200 Declare recovery and developer modes outside ChromeOS Move the implementation for recovery and developer modes from vendorcode/google/chromes to lib/. Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ++ src/ec/google/chromeec/ec.c | 2 +- src/include/bootmode.h | 34 ++++++++++++++++ src/lib/Makefile.inc | 3 ++ src/lib/bootmode.c | 63 +++++++++++++++++++++++++++++ src/northbridge/intel/haswell/raminit.c | 7 +--- src/northbridge/intel/sandybridge/raminit.c | 6 +-- src/vendorcode/google/chromeos/Kconfig | 1 + src/vendorcode/google/chromeos/chromeos.c | 36 ++--------------- src/vendorcode/google/chromeos/chromeos.h | 9 ++--- 10 files changed, 115 insertions(+), 50 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6356b19..cc80b43 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -300,6 +300,10 @@ config MMCONF_SUPPORT bool default n +config BOOTMODE_STRAPS + bool + default n + source src/console/Kconfig config HAVE_ACPI_RESUME diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index f1cefae..c57e18b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <console/console.h> +#include <bootmode.h> #include <arch/io.h> #include <delay.h> #include <arch/hlt.h> @@ -31,7 +32,6 @@ #endif #include "ec.h" #include "ec_commands.h" -#include <vendorcode/google/chromeos/chromeos.h> uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) { diff --git a/src/include/bootmode.h b/src/include/bootmode.h new file mode 100644 index 0000000..d64bf93 --- /dev/null +++ b/src/include/bootmode.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __BOOTMODE_H__ +#define __BOOTMODE_H__ + +int get_developer_mode_switch(void); +int get_recovery_mode_switch(void); + +#if CONFIG_BOOTMODE_STRAPS +int developer_mode_enabled(void); +int recovery_mode_enabled(void); +#else +static inline int recovery_mode_enabled(void) { return 0; } +static inline int developer_mode_enabled(void) { return 0; } +#endif + +#endif /* __BOOTMODE_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f8cf3b1..8a82058 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -128,6 +128,9 @@ smm-y += gcc.c $(obj)/lib/version.ramstage.o : $(obj)/build.h +romstage-y += bootmode.c +ramstage-y += bootmode.c + ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c new file mode 100644 index 0000000..156321f --- /dev/null +++ b/src/lib/bootmode.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootmode.h> +#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE +#include <vendorcode/google/chromeos/chromeos.h> +#endif + +#if CONFIG_BOOTMODE_STRAPS +int developer_mode_enabled(void) +{ + if (get_developer_mode_switch()) + return 1; +#if CONFIG_VBOOT_VERIFY_FIRMWARE + if (vboot_enable_developer()) + return 1; +#endif + return 0; +} + +/* + * This is called in multiple places and has to detect + * recovery mode triggered from the EC and via shared + * recovery reason set with crossystem. + * + * If shared recovery reason is set: + * - before VbInit then get_recovery_mode_from_vbnv() is true + * - after VbInit then vboot_enable_recovery() is true + * + * Otherwise the mainboard handler for get_recovery_mode_switch() + * will detect recovery mode initiated by the EC. + */ +int recovery_mode_enabled(void) +{ + if (get_recovery_mode_switch()) + return 1; +#if CONFIG_CHROMEOS + if (get_recovery_mode_from_vbnv()) + return 1; +#endif +#if CONFIG_VBOOT_VERIFY_FIRMWARE + if (vboot_enable_recovery()) + return 1; +#endif + return 0; +} +#endif /* CONFIG_BOOTMODE_STRAPS */ diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 1e020f9..4138c5f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <bootmode.h> #include <string.h> #include <arch/hlt.h> #include <arch/io.h> @@ -31,12 +32,6 @@ #include "pei_data.h" #include "haswell.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#else -#define recovery_mode_enabled(x) 0 -#endif - void save_mrc_data(struct pei_data *pei_data) { struct mrc_data_container *mrcdata; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 61e1545..5384996 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <console/usb.h> +#include <bootmode.h> #include <string.h> #include <arch/hlt.h> #include <arch/io.h> @@ -34,11 +35,6 @@ /* Management Engine is in the southbridge */ #include "southbridge/intel/bd82x6x/me.h" -#if CONFIG_CHROMEOS -#include <vendorcode/google/chromeos/chromeos.h> -#else -#define recovery_mode_enabled(x) 0 -#endif /* * MRC scrambler seed offsets should be reserved in diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index ed358f8..b4838fd 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -26,6 +26,7 @@ config CHROMEOS bool "Build for ChromeOS" default y select TPM + select BOOTMODE_STRAPS help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index e917ba1..f8dd7dc 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -27,7 +27,9 @@ #include <console/console.h> #if CONFIG_VBOOT_VERIFY_FIRMWARE -static int vboot_enable_developer(void) +#include <payload_loader.h> + +int vboot_enable_developer(void) { struct vboot_handoff *vbho; @@ -42,7 +44,7 @@ static int vboot_enable_developer(void) return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER); } -static int vboot_enable_recovery(void) +int vboot_enable_recovery(void) { struct vboot_handoff *vbho; @@ -53,36 +55,6 @@ static int vboot_enable_recovery(void) return !!(vbho->init_params.out_flags & VB_INIT_OUT_ENABLE_RECOVERY); } -#else -static inline int vboot_enable_developer(void) { return 0; } -static inline int vboot_enable_recovery(void) { return 0; } -#endif - -int developer_mode_enabled(void) -{ - return get_developer_mode_switch() || vboot_enable_developer(); -} - -int recovery_mode_enabled(void) -{ - /* - * This is called in multiple places and has to detect - * recovery mode triggered from the EC and via shared - * recovery reason set with crossystem. - * - * If shared recovery reason is set: - * - before VbInit then get_recovery_mode_from_vbnv() is true - * - after VbInit then vboot_enable_recovery() is true - * - * Otherwise the mainboard handler for get_recovery_mode_switch() - * will detect recovery mode initiated by the EC. - */ - return get_recovery_mode_switch() || get_recovery_mode_from_vbnv() || - vboot_enable_recovery(); -} - -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <payload_loader.h> static void *vboot_get_payload(size_t *len) { diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 0af26dc..9430276 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -22,10 +22,9 @@ #include <stddef.h> #include <stdint.h> +#include <bootmode.h> /* functions implemented per mainboard: */ -int get_developer_mode_switch(void); -int get_recovery_mode_switch(void); int get_write_protect_state(void); #ifdef __PRE_RAM__ void save_chromeos_gpios(void); @@ -39,16 +38,14 @@ extern int oprom_is_loaded; void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy); -/* functions implemented in chromeos.c: */ -int developer_mode_enabled(void); -int recovery_mode_enabled(void); - /* functions implemented in vboot.c */ void init_chromeos(int bootmode); #if CONFIG_VBOOT_VERIFY_FIRMWARE /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); +int vboot_enable_developer(void); +int vboot_enable_recovery(void); #endif #include "gnvs.h"

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Patch set updated for coreboot: 5ac4415 ChromeOS: Remove oprom_is_loaded
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4309 -gerrit commit 5ac441586ab342ae2b687a5b83b4dd2d1a475809 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 28 16:44:51 2013 +0200 ChromeOS: Remove oprom_is_loaded A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 11 +++-------- src/include/bootmode.h | 3 +++ src/lib/bootmode.c | 17 +++++++++++++++++ src/mainboard/google/bolt/chromeos.c | 2 +- src/mainboard/google/butterfly/chromeos.c | 2 +- src/mainboard/google/falco/chromeos.c | 2 +- src/mainboard/google/link/chromeos.c | 2 +- src/mainboard/google/link/i915.c | 4 +--- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/peppy/chromeos.c | 2 +- src/mainboard/google/rambi/chromeos.c | 2 +- src/mainboard/google/slippy/chromeos.c | 2 +- src/mainboard/google/slippy/gma.c | 4 +--- src/mainboard/google/stout/chromeos.c | 2 +- src/mainboard/google/stout/i915.c | 4 +--- src/mainboard/intel/baskingridge/chromeos.c | 2 +- src/mainboard/intel/emeraldlake2/chromeos.c | 2 +- src/mainboard/intel/wtm2/chromeos.c | 2 +- src/mainboard/intel/wtm2/i915.c | 4 +--- src/mainboard/lenovo/x60/i915.c | 2 +- src/mainboard/samsung/lumpy/chromeos.c | 2 +- src/mainboard/samsung/stumpy/chromeos.c | 2 +- src/northbridge/intel/haswell/gma.c | 3 +++ src/northbridge/intel/i945/gma.c | 5 ++++- src/northbridge/intel/sandybridge/gma.c | 5 ++++- src/vendorcode/google/chromeos/chromeos.h | 1 - 26 files changed, 53 insertions(+), 38 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index ca36046..dfc0898 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -32,6 +32,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <bootmode.h> #include <delay.h> #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT #include <device/hypertransport.h> @@ -660,10 +661,6 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } -#if CONFIG_CHROMEOS -int oprom_is_loaded = 0; -#endif - #if CONFIG_VGA_ROM_RUN static int should_run_oprom(struct device *dev) { @@ -733,10 +730,8 @@ void pci_dev_init(struct device *dev) return; run_bios(dev, (unsigned long)ram); -#if CONFIG_CHROMEOS - oprom_is_loaded = 1; - printk(BIOS_DEBUG, "VGA Option ROM has been loaded\n"); -#endif + gfx_set_init_done(1); + printk(BIOS_DEBUG, "VGA Option ROM was run\n"); #endif /* CONFIG_VGA_ROM_RUN */ } diff --git a/src/include/bootmode.h b/src/include/bootmode.h index d64bf93..a2c3411 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -23,6 +23,9 @@ int get_developer_mode_switch(void); int get_recovery_mode_switch(void); +int gfx_get_init_done(void); +void gfx_set_init_done(int done); + #if CONFIG_BOOTMODE_STRAPS int developer_mode_enabled(void); int recovery_mode_enabled(void); diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 156321f..9818490 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <rules.h> #include <bootmode.h> #if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> @@ -61,3 +62,19 @@ int recovery_mode_enabled(void) return 0; } #endif /* CONFIG_BOOTMODE_STRAPS */ + +#if ENV_RAMSTAGE +static int gfx_init_done = -1; + +int gfx_get_init_done(void) +{ + if (gfx_init_done < 0) + return 0; + return gfx_init_done; +} + +void gfx_set_init_done(int done) +{ + gfx_init_done = done; +} +#endif diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c index 76f2c31..5724101 100644 --- a/src/mainboard/google/bolt/chromeos.c +++ b/src/mainboard/google/bolt/chromeos.c @@ -79,7 +79,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index b5a645f..397679a 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -93,7 +93,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Was VGA Option ROM loaded? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 51d625b..780e58f 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -76,7 +76,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index dd1606f..33069b1 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -88,7 +88,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Did we load the VGA Option ROM? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index a38760b..2b62bf4 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -58,7 +58,6 @@ static unsigned int graphics; static unsigned short addrport; static unsigned short dataport; static unsigned int physbase; -extern int oprom_is_loaded; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; const u32 link_edid_data[] = { @@ -379,6 +378,5 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); set_vbe_mode_info_valid(&edid, graphics); i915_init_done = 1; - oprom_is_loaded = 1; - return 0; + return i915_init_done; } diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 6f50a79..1e79e4b 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -84,7 +84,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Did we load the VGA Option ROM? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index 51d625b..780e58f 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -76,7 +76,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index f6f13ed..636aae1 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -78,7 +78,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) get_developer_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 51d625b..780e58f 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -76,7 +76,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c index e698fc9..f2f93b1 100644 --- a/src/mainboard/google/slippy/gma.c +++ b/src/mainboard/google/slippy/gma.c @@ -89,7 +89,6 @@ static unsigned int graphics; static unsigned short addrport; static unsigned short dataport; static unsigned int physbase; -extern int oprom_is_loaded; static int ioread = 0, iowrite = 0; @@ -462,10 +461,9 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, set_vbe_mode_info_valid(&dp->edid, graphics); i915_init_done = 1; - oprom_is_loaded = 1; //io_i915_write32( 0x80000000,BLC_PWM_CPU_CTL2); //io_i915_write32( 0x80000000,BLC_PWM_PCH_CTL1); - return 1; + return i915_init_done; fail: printk(BIOS_SPEW, "Graphics could not be started;"); diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 0e43250..297626c 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -82,7 +82,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Was VGA Option ROM loaded? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); /* EC is in RW mode when it isn't in recovery mode. */ diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 8085de6..4ebd567 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -41,7 +41,6 @@ static unsigned int graphics; static unsigned short addrport; static unsigned short dataport; static unsigned int physbase; -extern int oprom_is_loaded; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,6 +277,5 @@ int i915lightup(unsigned int pphysbase, memset((void *)graphics, 0, 4520*4096); printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); i915_init_done = 1; - oprom_is_loaded = 1; - return 0; + return i915_init_done; } diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6bf5116..7b64f10 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -81,7 +81,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Did we load the VGA option ROM? */ gpios->gpios[5].port = -1; gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 4d998ec..2194973 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -80,7 +80,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Did we load the VGA option ROM? */ gpios->gpios[5].port = -1; gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 594b4a7..a5ca4eb 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -61,7 +61,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", DEV_MODE_SETTING); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c index b664c35..64fa6b1 100644 --- a/src/mainboard/intel/wtm2/i915.c +++ b/src/mainboard/intel/wtm2/i915.c @@ -70,7 +70,6 @@ static unsigned int graphics; static unsigned short addrport; static unsigned short dataport; static unsigned int physbase; -extern int oprom_is_loaded; const u32 link_edid_data[] = { 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000, @@ -220,8 +219,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, */ i915_init_done = 1; - oprom_is_loaded = 1; - return 1; + return i915_init_done; fail: printk(BIOS_SPEW, "Graphics could not be started;"); diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..b41a0ba 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -369,5 +369,5 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, set_vbe_mode_info_valid(&edid, graphics); - return 0; + return 1; } diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index afbdeeb..c9fa1d9 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -86,7 +86,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Did we load the VGA Option ROM? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index e639fd3..be18370 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -83,7 +83,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Did we load the VGA Option ROM? */ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = oprom_is_loaded; + gpios->gpios[5].value = gfx_get_init_done(); strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); } #endif diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 2ceffe4..0c56f76 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <console/console.h> +#include <bootmode.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -408,6 +409,8 @@ static void gma_func0_init(struct device *dev) int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base); + if (lightup_ok) + gfx_set_init_done(1); #endif if (! lightup_ok) { printk(BIOS_SPEW, "FUI did not run; using VBIOS\n"); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..453e9c8 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <bootmode.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -63,7 +64,9 @@ static void gma_func0_init(struct device *dev) ); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); + if (lightup_ok) + gfx_set_init_done(1); #endif } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..2d8bd77 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <console/console.h> +#include <bootmode.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -649,7 +650,9 @@ static void gma_func0_init(struct device *dev) graphics_base = dev->resource_list[1].base; int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(physbase, iobase, mmiobase, graphics_base); + int lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base); + if (lightup_ok) + gfx_set_init_done(1); #endif } diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 9430276..e501427 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -33,7 +33,6 @@ void save_chromeos_gpios(void); /* functions implemented in vbnv.c: */ int get_recovery_mode_from_vbnv(void); int vboot_wants_oprom(void); -extern int oprom_is_loaded; void read_vbnv(uint8_t *vbnv_copy); void save_vbnv(const uint8_t *vbnv_copy);

1 0

Patch set updated for coreboot: 40c33ac ChromeOS: Use common fill_lb_gpio()
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5586 -gerrit commit 40c33acd1897addb738d591bf38b847f563b5295 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 03:12:38 2013 +0200 ChromeOS: Use common fill_lb_gpio() Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/boot/coreboot_tables.h | 4 ++++ src/lib/coreboot_table.c | 11 +++++++++++ src/mainboard/google/bolt/chromeos.c | 15 --------------- src/mainboard/google/butterfly/chromeos.c | 2 -- src/mainboard/google/falco/chromeos.c | 15 --------------- src/mainboard/google/link/chromeos.c | 2 -- src/mainboard/google/parrot/chromeos.c | 2 -- src/mainboard/google/peppy/chromeos.c | 15 --------------- src/mainboard/google/pit/chromeos.c | 5 ----- src/mainboard/google/rambi/chromeos.c | 13 ------------- src/mainboard/google/slippy/chromeos.c | 15 --------------- src/mainboard/google/snow/chromeos.c | 5 ----- src/mainboard/google/stout/chromeos.c | 2 -- src/mainboard/intel/baskingridge/chromeos.c | 2 -- src/mainboard/intel/emeraldlake2/chromeos.c | 2 -- src/mainboard/intel/wtm2/chromeos.c | 15 --------------- src/mainboard/samsung/lumpy/chromeos.c | 2 -- src/mainboard/samsung/stumpy/chromeos.c | 2 -- 18 files changed, 15 insertions(+), 114 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 08a89bc..f8f8022 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -200,6 +200,8 @@ struct lb_framebuffer { struct lb_gpio { uint32_t port; uint32_t polarity; +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 uint32_t value; #define GPIO_MAX_NAME_LENGTH 16 uint8_t name[GPIO_MAX_NAME_LENGTH]; @@ -339,6 +341,8 @@ unsigned long write_coreboot_table( unsigned long rom_table_start, unsigned long rom_table_end); void fill_lb_gpios(struct lb_gpios *gpios); +void fill_lb_gpio(struct lb_gpio *gpio, int num, + int polarity, const char *name, int value); void uart_fill_lb(void *data); void lb_add_serial(struct lb_serial *serial, void *data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8e7f85d..fbc1902 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -145,6 +145,17 @@ static void lb_framebuffer(struct lb_header *header) } #if CONFIG_CHROMEOS +void fill_lb_gpio(struct lb_gpio *gpio, int num, + int polarity, const char *name, int value) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = num; + gpio->polarity = polarity; + if (value >= 0) + gpio->value = value; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + static void lb_gpios(struct lb_header *header) { struct lb_gpios *gpios; diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c index 5724101..f003f42 100644 --- a/src/mainboard/google/bolt/chromeos.c +++ b/src/mainboard/google/bolt/chromeos.c @@ -36,8 +36,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 static int get_lid_switch(void) { @@ -50,19 +48,6 @@ static int get_lid_switch(void) #endif } -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio *gpio; diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 397679a..8f249c6 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -28,8 +28,6 @@ #include <ec/quanta/ene_kb3940q/ec.h> #include "ec.h" -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 #define WP_GPIO 6 #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 780e58f..0056dfd 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -33,8 +33,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 static int get_lid_switch(void) { @@ -47,19 +45,6 @@ static int get_lid_switch(void) #endif } -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio *gpio; diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index 33069b1..bf6d428 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -30,8 +30,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 static int get_lid_switch(void) { diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 1e79e4b..fcf6374 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -28,8 +28,6 @@ #include <ec/compal/ene932/ec.h> #include "ec.h" -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index 780e58f..0056dfd 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -33,8 +33,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 static int get_lid_switch(void) { @@ -47,19 +45,6 @@ static int get_lid_switch(void) #endif } -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio *gpio; diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c index ae219bb..08b4e99 100644 --- a/src/mainboard/google/pit/chromeos.c +++ b/src/mainboard/google/pit/chromeos.c @@ -26,11 +26,6 @@ #include <cpu/samsung/exynos5420/cpu.h> #include <cpu/samsung/exynos5420/gpio.h> -enum { - ACTIVE_LOW = 0, - ACTIVE_HIGH = 1 -}; - void fill_lb_gpios(struct lb_gpios *gpios) { int count = 0; diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 636aae1..9223858 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -36,8 +36,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 static int get_lid_switch(void) { @@ -51,17 +49,6 @@ static int get_lid_switch(void) #endif } -static void fill_lb_gpio(struct lb_gpio *gpio, int port, int polarity, - const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = port; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio *gpio; diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 780e58f..0056dfd 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -33,8 +33,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 static int get_lid_switch(void) { @@ -47,19 +45,6 @@ static int get_lid_switch(void) #endif } -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio *gpio; diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 2b830a1..c525a81 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -26,11 +26,6 @@ #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/gpio.h> -enum { - ACTIVE_LOW = 0, - ACTIVE_HIGH = 1 -}; - void fill_lb_gpios(struct lb_gpios *gpios) { int count = 0; diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 297626c..74955de 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -32,8 +32,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 7 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 7b64f10..7efd065 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -29,8 +29,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 2194973..72adaf7 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -28,8 +28,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index a5ca4eb..9c4c3b4 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -32,21 +32,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 - -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index c9fa1d9..bdc0148 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -39,8 +39,6 @@ #include <ec/smsc/mec1308/ec.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) { diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index be18370..731126c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -36,8 +36,6 @@ #include <boot/coreboot_tables.h> #define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 void fill_lb_gpios(struct lb_gpios *gpios) {

1 0

New patch to review for coreboot: 01a7049 AGESA SPI: Fix Kconfig options
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5606 -gerrit commit 01a70491c69df3b552d47938ddca0d7c2a3c2c93 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 29 07:15:26 2014 +0300 AGESA SPI: Fix Kconfig options Option AMD_SB_SPI_LEN leaked to non-AMD configs. Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME. Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Kconfig | 1 + src/southbridge/amd/Kconfig | 8 +++++--- src/southbridge/amd/agesa/hudson/Kconfig | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index a73c5ce..15ed861 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -29,6 +29,7 @@ config CPU_AMD_AGESA select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER + select SPI_FLASH if HAVE_ACPI_RESUME if CPU_AMD_AGESA diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 42209ce..39aeb09 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -15,9 +15,11 @@ source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig -config SPI_FLASH - bool - default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA +if CPU_AMD_AGESA + config AMD_SB_SPI_TX_LEN int default 4 + depends on SPI_FLASH + +endif diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index dd5120d..9e21b84 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -243,6 +243,7 @@ if SOUTHBRIDGE_AMD_AGESA_YANGTZE config AMD_SB_SPI_TX_LEN int default 64 + depends on SPI_FLASH config AZ_PIN hex

1 0

New patch to review for coreboot: e1eadfa SPI: Use common dependency in Kconfig
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5605 -gerrit commit e1eadfad524fda2bbab7d37fe0b8ee905105b071 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 29 07:11:39 2014 +0300 SPI: Use common dependency in Kconfig Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/spi/Kconfig | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 8ce6def..5135dfb 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -24,17 +24,18 @@ config SPI_FLASH Select this option if your chipset driver needs to store certain data in the SPI flash. +if SPI_FLASH + config SPI_FLASH_SMM bool "SPI flash driver support in SMM" default n - depends on SPI_FLASH && HAVE_SMI_HANDLER + depends on HAVE_SMI_HANDLER help Select this option if you want SPI flash support in SMM. config SPI_FLASH_AMIC bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by AMIC. @@ -42,7 +43,6 @@ config SPI_FLASH_AMIC config SPI_FLASH_EON bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON. @@ -50,7 +50,6 @@ config SPI_FLASH_EON config SPI_FLASH_MACRONIX bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix. @@ -58,7 +57,6 @@ config SPI_FLASH_MACRONIX config SPI_FLASH_SPANSION bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion. @@ -66,7 +64,6 @@ config SPI_FLASH_SPANSION config SPI_FLASH_SST bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST. @@ -74,7 +71,6 @@ config SPI_FLASH_SST config SPI_FLASH_STMICRO bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO. @@ -82,7 +78,6 @@ config SPI_FLASH_STMICRO config SPI_FLASH_WINBOND bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. @@ -90,7 +85,6 @@ config SPI_FLASH_WINBOND config SPI_FLASH_NO_FAST_READ bool "Disable Fast Read command" default n - depends on SPI_FLASH help Select this option if your setup requires to avoid "fast read"s from the SPI flash parts. @@ -98,7 +92,6 @@ config SPI_FLASH_NO_FAST_READ config SPI_FLASH_GIGADEVICE bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice. @@ -106,7 +99,8 @@ config SPI_FLASH_GIGADEVICE config SPI_FLASH_ADESTO bool default y - depends on SPI_FLASH help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Adesto Technologies. + +endif # SPI_FLASH

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New patch to review for coreboot: 3a5e269 superio/winbond/w83627thg: Remove w83627thg_enable_serial symbol
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5604 -gerrit commit 3a5e2690675c186e33980038c0b3e078ed999a86 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 14:05:02 2014 +1000 superio/winbond/w83627thg: Remove w83627thg_enable_serial symbol Remove model specific implementation, w83627thg_enable_serial, from romstage component of sio support. Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/winbond/w83627thg/early_serial.c | 10 ---------- src/superio/winbond/w83627thg/w83627thg.h | 1 - 2 files changed, 11 deletions(-) diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c index cc84738..6ab178b 100644 --- a/src/superio/winbond/w83627thg/early_serial.c +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -37,16 +37,6 @@ void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -void w83627thg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - #ifndef __ROMCC__ void w83627thg_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index a5cc450..ec857d3 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -38,6 +38,5 @@ void pnp_enter_ext_func_mode(device_t dev); void pnp_exit_ext_func_mode(device_t dev); void w83627thg_set_clksel_48(device_t dev); -void w83627thg_enable_serial(device_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83627THG_W83627THG_H */

1 0

New patch to review for coreboot: bb5ea7b mainboard/*: Use generic winbond romstage in place of w83627thg
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5603 -gerrit commit bb5ea7bbc710ddfd0537f9632de1dd386b57b917 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 13:59:54 2014 +1000 mainboard/*: Use generic winbond romstage in place of w83627thg Use the generic implementation of winbond in place of the model specific w83627thg_enable_serial() as so that it maybe removed later. Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lanner/em8510/romstage.c | 5 +++-- src/mainboard/msi/ms7135/romstage.c | 3 ++- src/mainboard/winent/mb6047/romstage.c | 3 ++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 335f9ec..4ae5c12 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -34,6 +34,7 @@ #include "southbridge/intel/i82801dx/i82801dx.h" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include "cpu/x86/bist.h" @@ -56,8 +57,8 @@ void main(unsigned long bist) #endif } - w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index ccb420a..15c02f5 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -31,6 +31,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> @@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 07f235c..a725beb 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -16,6 +16,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" +#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -84,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */

1 0

New patch to review for coreboot: 9c97468 mainboard/kontron/986lcd-m: Remove a duplicate header
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5602 -gerrit commit 9c97468c269f9d6b0293e32eed23c16d62ce2277 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 13:53:35 2014 +1000 mainboard/kontron/986lcd-m: Remove a duplicate header Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/kontron/986lcd-m/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index ba18720..9126889 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include "superio/winbond/w83627thg/w83627thg.h" #include <pc80/mc146818rtc.h> #include "option_table.h" #include <console/console.h>

1 0

New patch to review for coreboot: 12a63ac superio/winbond/w83627hf: Avoid .c includes
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5601 -gerrit commit 12a63ac87fdd6b4a67536acfe3e180a336f2f49d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 13:09:50 2014 +1000 superio/winbond/w83627hf: Avoid .c includes NOTFORMERGE Remove superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match. Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/romstage.c | 7 +++-- src/mainboard/avalue/eax-785e/romstage.c | 7 +++-- src/mainboard/msi/ms6178/romstage.c | 5 ++-- src/mainboard/pcengines/alix1c/romstage.c | 5 ++-- src/mainboard/supermicro/h8dme/romstage.c | 6 ++-- src/mainboard/supermicro/h8dmr/romstage.c | 8 +++--- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 6 ++-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 8 +++--- src/mainboard/supermicro/x6dai_g/romstage.c | 6 ++-- src/mainboard/supermicro/x6dhe_g/romstage.c | 6 ++-- src/mainboard/supermicro/x6dhr_ig/romstage.c | 6 ++-- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 6 ++-- src/mainboard/winent/pl6064/romstage.c | 5 ++-- src/superio/winbond/w83627hf/Makefile.inc | 2 +- src/superio/winbond/w83627hf/early_init.c | 38 ------------------------- src/superio/winbond/w83627hf/early_serial.c | 11 +------ src/superio/winbond/w83627hf/w83627hf.h | 13 ++++----- 17 files changed, 52 insertions(+), 93 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 490d146..2402798 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 69cefd9..f6a10dc 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 518944f..fa78a82 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -25,7 +25,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax.h" @@ -38,7 +39,7 @@ void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 1c4ae09..204f0bd 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -39,7 +39,8 @@ static void cs5536_enable_smbus(void) { } #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> /* The part is a Hynix hy5du121622ctp-d43. * @@ -121,7 +122,7 @@ void main(unsigned long bist) * It is counting on some early MSR setup for the CS5536. */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index df5e2c8..47f5806 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -33,8 +33,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 8ed7e6d..7d1f834 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -36,8 +36,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -114,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 3f6ea70..cd185f3 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index cca464c..1bb6873 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -172,8 +172,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); write_GPIO(); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index f57adaf..687fcdd 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -9,13 +9,13 @@ #include "lib/delay.c" #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7525/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/esb6300/reset.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> @@ -64,7 +64,7 @@ static void main(unsigned long bist) } w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* MOVE ME TO A BETTER LOCATION !!! */ diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 071bb35..476fb0f 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -9,13 +9,13 @@ #include "lib/delay.c" #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/esb6300/reset.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> @@ -64,7 +64,7 @@ static void main(unsigned long bist) } w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 9c61d60..e91a88a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -7,13 +7,13 @@ #include <console/console.h> #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/i82801ex/reset.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> @@ -63,7 +63,7 @@ static void main(unsigned long bist) } w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 4690a0c..c59340b 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -7,13 +7,13 @@ #include <console/console.h> #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/i82801ex/reset.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> @@ -63,7 +63,7 @@ static void main(unsigned long bist) } w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 124183c..6a38355 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -34,7 +34,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -66,7 +67,7 @@ void main(unsigned long bist) * early MSR setup for CS5536. */ w83627hf_set_clksel_48(SERIAL_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627hf/Makefile.inc b/src/superio/winbond/w83627hf/Makefile.inc index be5ec48..d6a8869 100644 --- a/src/superio/winbond/w83627hf/Makefile.inc +++ b/src/superio/winbond/w83627hf/Makefile.inc @@ -20,5 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c - diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c deleted file mode 100644 index 66b4098..0000000 --- a/src/superio/winbond/w83627hf/early_init.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "w83627hf.h" - -void w83627hf_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void w83627hf_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index db2827b..ef46a69 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -22,6 +22,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "w83627hf.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -37,16 +38,6 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -void w83627hf_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - void w83627hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 468cb55..cdfc77b 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627HF_W83627HF_H -#define SUPERIO_WINBOND_W83627HF_W83627HF_H +#ifndef SUPERIO_WINBOND_W83627HF_H +#define SUPERIO_WINBOND_W83627HF_H #define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel port */ @@ -113,11 +113,8 @@ #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 -#if defined(__PRE_RAM__) -void w83627hf_disable_dev(device_t dev); -void w83627hf_enable_dev(device_t dev, u16 iobase); -void w83627hf_enable_serial(device_t dev, u16 iobase); +#include <arch/io.h> + void w83627hf_set_clksel_48(device_t dev); -#endif -#endif +#endif /* SUPERIO_WINBOND_W83627HF_H */

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Patch set updated for coreboot: a782af1 mainboard/*: Avoid including early_serial.c from w83627hf
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5597 -gerrit commit a782af1599b62d7547975f67a7b5a3f6112707ce Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 18:07:33 2014 +1000 mainboard/*: Avoid including early_serial.c from w83627hf Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6240/romstage.c | 5 +++-- src/mainboard/amd/db800/romstage.c | 5 +++-- src/mainboard/amd/rumba/Kconfig | 1 + src/mainboard/amd/rumba/romstage.c | 5 +++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 7 ++++--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 5 +++-- src/mainboard/asus/dsbf/romstage.c | 5 +++-- src/mainboard/digitallogic/adl855pc/romstage.c | 7 ++++--- src/mainboard/digitallogic/msm800sev/romstage.c | 5 +++-- src/mainboard/hp/dl145_g1/romstage.c | 5 +++-- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 5 +++-- src/mainboard/iwill/dk8_htx/romstage.c | 7 ++++--- src/mainboard/iwill/dk8s2/romstage.c | 7 ++++--- src/mainboard/iwill/dk8x/romstage.c | 7 ++++--- src/mainboard/lippert/frontrunner/Kconfig | 1 + src/mainboard/lippert/frontrunner/romstage.c | 5 +++-- src/mainboard/newisys/khepri/romstage.c | 7 ++++--- src/mainboard/supermicro/x7db8/romstage.c | 8 +++++--- src/mainboard/tyan/s2735/romstage.c | 7 ++++--- src/mainboard/tyan/s2850/romstage.c | 7 ++++--- src/mainboard/tyan/s2875/romstage.c | 7 ++++--- src/mainboard/tyan/s2880/romstage.c | 7 ++++--- src/mainboard/tyan/s2881/romstage.c | 7 ++++--- src/mainboard/tyan/s2882/romstage.c | 7 ++++--- src/mainboard/tyan/s2885/romstage.c | 7 ++++--- src/mainboard/tyan/s2891/romstage.c | 5 +++-- src/mainboard/tyan/s2892/romstage.c | 5 +++-- src/mainboard/tyan/s2912/romstage.c | 6 +++--- src/mainboard/tyan/s2912_fam10/romstage.c | 6 +++--- src/mainboard/tyan/s4880/romstage.c | 7 ++++--- src/mainboard/tyan/s4882/romstage.c | 7 ++++--- 31 files changed, 106 insertions(+), 76 deletions(-) diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 9e4b35b..41d5d2a 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 93fc0e5..564380e 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -32,7 +32,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -63,7 +64,7 @@ void main(unsigned long bist) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index d600a58..1d60d0c 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF select UDELAY_TSC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index cec7c36..c5a3fc3 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -4,7 +4,8 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> @@ -38,7 +39,7 @@ void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5536_early_setup(); diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index b103389..14320a5 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -113,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index bb7d5d3..09b86bb 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -44,7 +44,8 @@ #include <console/loglevel.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -204,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index f4e65cb..e013371 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -29,7 +29,8 @@ #include <lib.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <superio/winbond/w83627hf/early_serial.c> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" @@ -116,7 +117,7 @@ void main(unsigned long bist) i5000_lpc_config(); - w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); + winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 7eefedd..5935af2 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -11,7 +11,8 @@ #include "southbridge/intel/i82801dx/i82801dx.h" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include <spd.h> @@ -34,8 +35,8 @@ void main(unsigned long bist) #endif } - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index b96f8ae..986e918 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -13,7 +13,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -46,7 +47,7 @@ void main(unsigned long bist) * for cs5536 */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index a5df58d..2b42e73 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -17,7 +17,8 @@ #include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -113,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 1cbe32d..a75691c 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -32,7 +32,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -63,7 +64,7 @@ void main(unsigned long bist) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 070fb07..a429568 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -13,7 +13,8 @@ #include "cpu/x86/bist.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 7c8d4a5..d2371b5 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -13,7 +13,8 @@ #include "cpu/x86/bist.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -83,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index b5a1d71..50869f7 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -13,7 +13,8 @@ #include "cpu/x86/bist.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -83,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig index ba1d5f1..422cded 100644 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ b/src/mainboard/lippert/frontrunner/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 + select SUPERIO_WINBOND_W83627HF select HAVE_DEBUG_SMBUS select UDELAY_TSC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index bdbf059..92a3a99 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -5,7 +5,8 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> @@ -80,7 +81,7 @@ void main(unsigned long bist) SystemPreInit(); msr_init(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5535_early_setup(); diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 652104a..b34882e 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -20,7 +20,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index bc54ed7..791028e 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -29,7 +29,8 @@ #include <lib.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <superio/winbond/w83627hf/early_serial.c> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" @@ -43,6 +44,8 @@ #define RCBA_GCS 0x3410 /* 32 bit */ #define RCBA_FD 0x3418 /* 32 bit */ +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void early_config(void) { u32 gcs, rpc, fd; @@ -115,8 +118,7 @@ void main(unsigned long bist) i5000_lpc_config(); - w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); - + winbond_enable_serial(SERIAL_DEV, 0x3f8); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 4e71559..600d806 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -11,7 +11,8 @@ #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "northbridge/intel/e7501/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -47,8 +48,8 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 301f81c..952b19d 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -75,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 7c9f93a..8f87257 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 13cc01e..873652b 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index dad2b6b..c020f3e 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -73,8 +74,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 13cc01e..873652b 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index a2dc990..df602ea 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -71,8 +72,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index aa0385b..e97b026 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -16,7 +16,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -94,7 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 5d6ff2a..57da072 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -16,7 +16,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index e4a1c65..55cb95e 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -36,8 +36,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 9c86157..6dae693 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 2b6470c..543fcf0 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -131,8 +132,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 60dbdf8..b4100fb 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -13,7 +13,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -110,8 +111,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

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coreboot-gerrit April 2014