coreboot-gerrit April 2014

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Patch set updated for coreboot: 4fe642a mainboard/: Avoid including early_serial.c from w83627hf
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5597 -gerrit commit 4fe642ac92acdffb83964187ae990223c3371b29 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 28 18:07:33 2014 +1000 mainboard/: Avoid including early_serial.c from w83627hf Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6240/romstage.c | 5 +++-- src/mainboard/amd/db800/romstage.c | 5 +++-- src/mainboard/amd/rumba/Kconfig | 1 + src/mainboard/amd/rumba/romstage.c | 5 +++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 7 ++++--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 5 +++-- src/mainboard/asus/dsbf/romstage.c | 5 +++-- src/mainboard/digitallogic/adl855pc/romstage.c | 7 ++++--- src/mainboard/digitallogic/msm800sev/romstage.c | 5 +++-- src/mainboard/hp/dl145_g1/romstage.c | 5 +++-- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 5 +++-- src/mainboard/iwill/dk8_htx/romstage.c | 7 ++++--- src/mainboard/iwill/dk8s2/romstage.c | 7 ++++--- src/mainboard/iwill/dk8x/romstage.c | 7 ++++--- src/mainboard/lippert/frontrunner/Kconfig | 1 + src/mainboard/lippert/frontrunner/romstage.c | 5 +++-- src/mainboard/newisys/khepri/romstage.c | 7 ++++--- src/mainboard/supermicro/x7db8/romstage.c | 8 +++++--- src/mainboard/tyan/s2735/romstage.c | 7 ++++--- src/mainboard/tyan/s2850/romstage.c | 7 ++++--- src/mainboard/tyan/s2875/romstage.c | 7 ++++--- src/mainboard/tyan/s2880/romstage.c | 7 ++++--- src/mainboard/tyan/s2881/romstage.c | 7 ++++--- src/mainboard/tyan/s2882/romstage.c | 7 ++++--- src/mainboard/tyan/s2885/romstage.c | 7 ++++--- src/mainboard/tyan/s2891/romstage.c | 5 +++-- src/mainboard/tyan/s2892/romstage.c | 5 +++-- src/mainboard/tyan/s2912/romstage.c | 6 +++--- src/mainboard/tyan/s2912_fam10/romstage.c | 6 +++--- src/mainboard/tyan/s4880/romstage.c | 7 ++++--- src/mainboard/tyan/s4882/romstage.c | 7 ++++--- 31 files changed, 106 insertions(+), 76 deletions(-) diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 9e4b35b..41d5d2a 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -30,7 +30,8 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1) @@ -42,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) void main(unsigned long bist) { - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 93fc0e5..564380e 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -32,7 +32,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -63,7 +64,7 @@ void main(unsigned long bist) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index d600a58..1d60d0c 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF select UDELAY_TSC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index cec7c36..c5a3fc3 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -4,7 +4,8 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> @@ -38,7 +39,7 @@ void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5536_early_setup(); diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index b103389..14320a5 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -113,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index bb7d5d3..09b86bb 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -44,7 +44,8 @@ #include <console/loglevel.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -204,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index f4e65cb..e013371 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -29,7 +29,8 @@ #include <lib.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <superio/winbond/w83627hf/early_serial.c> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" @@ -116,7 +117,7 @@ void main(unsigned long bist) i5000_lpc_config(); - w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); + winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 7eefedd..5935af2 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -11,7 +11,8 @@ #include "southbridge/intel/i82801dx/i82801dx.h" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include <spd.h> @@ -34,8 +35,8 @@ void main(unsigned long bist) #endif } - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index b96f8ae..986e918 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -13,7 +13,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -46,7 +47,7 @@ void main(unsigned long bist) * for cs5536 */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index a5df58d..2b42e73 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -17,7 +17,8 @@ #include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -113,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 1cbe32d..a75691c 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -32,7 +32,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -63,7 +64,7 @@ void main(unsigned long bist) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 070fb07..a429568 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -13,7 +13,8 @@ #include "cpu/x86/bist.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 7c8d4a5..d2371b5 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -13,7 +13,8 @@ #include "cpu/x86/bist.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -83,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index b5a1d71..50869f7 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -13,7 +13,8 @@ #include "cpu/x86/bist.h" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -83,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig index ba1d5f1..422cded 100644 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ b/src/mainboard/lippert/frontrunner/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 + select SUPERIO_WINBOND_W83627HF select HAVE_DEBUG_SMBUS select UDELAY_TSC select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index bdbf059..92a3a99 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -5,7 +5,8 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> @@ -80,7 +81,7 @@ void main(unsigned long bist) SystemPreInit(); msr_init(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5535_early_setup(); diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 652104a..b34882e 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -20,7 +20,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -82,8 +83,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index bc54ed7..791028e 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -29,7 +29,8 @@ #include <lib.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <superio/winbond/w83627hf/early_serial.c> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" @@ -43,6 +44,8 @@ #define RCBA_GCS 0x3410 /* 32 bit */ #define RCBA_FD 0x3418 /* 32 bit */ +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void early_config(void) { u32 gcs, rpc, fd; @@ -115,8 +118,7 @@ void main(unsigned long bist) i5000_lpc_config(); - w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); - + winbond_enable_serial(SERIAL_DEV, 0x3f8); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 4e71559..600d806 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -11,7 +11,8 @@ #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "northbridge/intel/e7501/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -47,8 +48,8 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 301f81c..952b19d 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -75,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 7c9f93a..8f87257 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 13cc01e..873652b 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index dad2b6b..c020f3e 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -73,8 +74,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 13cc01e..873652b 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -84,8 +85,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index a2dc990..df602ea 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -71,8 +72,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index aa0385b..e97b026 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -16,7 +16,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -94,7 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 5d6ff2a..57da072 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -16,7 +16,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index e4a1c65..55cb95e 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -36,8 +36,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 9c86157..6dae693 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 2b6470c..543fcf0 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -14,7 +14,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -131,8 +132,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 60dbdf8..b4100fb 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -13,7 +13,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -110,8 +111,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

1 0

Patch set updated for coreboot: b5af981 superio/winbond/w83627hf: Avoid .c includes in mainboards
by Edward O'Callaghan 29 Apr '14

29 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5601 -gerrit commit b5af981733fa5ace95bec51a1447e458377921fa Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 13:09:50 2014 +1000 superio/winbond/w83627hf: Avoid .c includes in mainboards Move towards the removal od rhw superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match. The following mainboards remain unconverted as they are ROMCC: - mainboard/supermicro/x6dai_g - mainboard/supermicro/x6dhe_g - mainboard/supermicro/x6dhr_ig - mainboard/supermicro/x6dhr_ig2 and so block the final removal of w83627hf_serial_enable(). Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/romstage.c | 7 +++-- src/mainboard/avalue/eax-785e/romstage.c | 7 +++-- src/mainboard/msi/ms6178/romstage.c | 5 ++-- src/mainboard/pcengines/alix1c/romstage.c | 5 ++-- src/mainboard/supermicro/h8dme/romstage.c | 6 ++-- src/mainboard/supermicro/h8dmr/romstage.c | 8 +++--- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 6 ++-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 8 +++--- src/mainboard/supermicro/x6dai_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 5 ++-- src/superio/winbond/w83627hf/Makefile.inc | 2 +- src/superio/winbond/w83627hf/early_init.c | 38 ------------------------- src/superio/winbond/w83627hf/early_serial.c | 10 +++++++ src/superio/winbond/w83627hf/w83627hf.h | 14 ++++----- 17 files changed, 54 insertions(+), 75 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 490d146..2402798 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 69cefd9..f6a10dc 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 518944f..fa78a82 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -25,7 +25,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax.h" @@ -38,7 +39,7 @@ void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 1c4ae09..204f0bd 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -39,7 +39,8 @@ static void cs5536_enable_smbus(void) { } #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> /* The part is a Hynix hy5du121622ctp-d43. * @@ -121,7 +122,7 @@ void main(unsigned long bist) * It is counting on some early MSR setup for the CS5536. */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index df5e2c8..47f5806 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -33,8 +33,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 8ed7e6d..7d1f834 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -36,8 +36,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -114,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 3f6ea70..cd185f3 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index b8bac59..9898a25 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -186,8 +186,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); write_GPIO(); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index f57adaf..c998466 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -9,13 +9,13 @@ #include "lib/delay.c" #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7525/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/esb6300/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 071bb35..b1c3cfa 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -9,13 +9,13 @@ #include "lib/delay.c" #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/esb6300/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 9c61d60..2dc96c1 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -7,13 +7,13 @@ #include <console/console.h> #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/i82801ex/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 4690a0c..0f2a644 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -7,13 +7,13 @@ #include <console/console.h> #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/i82801ex/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 124183c..6a38355 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -34,7 +34,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -66,7 +67,7 @@ void main(unsigned long bist) * early MSR setup for CS5536. */ w83627hf_set_clksel_48(SERIAL_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627hf/Makefile.inc b/src/superio/winbond/w83627hf/Makefile.inc index be5ec48..d6a8869 100644 --- a/src/superio/winbond/w83627hf/Makefile.inc +++ b/src/superio/winbond/w83627hf/Makefile.inc @@ -20,5 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c - diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c deleted file mode 100644 index 66b4098..0000000 --- a/src/superio/winbond/w83627hf/early_init.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "w83627hf.h" - -void w83627hf_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void w83627hf_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index db2827b..35c0b86 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -22,6 +22,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "w83627hf.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -37,6 +38,15 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } +/* + * FIXME: The following ROMCC boards are blocking the removal this superio's + * model specific w83627hf_enable_serial() symbol. + * + * mainboard/supermicro/x6dai_g + * mainboard/supermicro/x6dhe_g + * mainboard/supermicro/x6dhr_ig + * mainboard/supermicro/x6dhr_ig2 + */ void w83627hf_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 468cb55..bf7186e 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83627HF_W83627HF_H -#define SUPERIO_WINBOND_W83627HF_W83627HF_H +#ifndef SUPERIO_WINBOND_W83627HF_H +#define SUPERIO_WINBOND_W83627HF_H #define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel port */ @@ -113,11 +113,9 @@ #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 -#if defined(__PRE_RAM__) -void w83627hf_disable_dev(device_t dev); -void w83627hf_enable_dev(device_t dev, u16 iobase); -void w83627hf_enable_serial(device_t dev, u16 iobase); +#include <arch/io.h> + void w83627hf_set_clksel_48(device_t dev); -#endif +void w83627hf_enable_serial(device_t dev, u16 iobase); -#endif +#endif /* SUPERIO_WINBOND_W83627HF_H */

1 0

New patch to review for coreboot: 1565bf9 console: Drop EARLY_CONSOLE option
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5607 -gerrit commit 1565bf99e45b16eb346723c6e2fe66f6675a3c24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 15 18:19:48 2014 +0300 console: Drop EARLY_CONSOLE option We have means to easily disable a specific console in romstage if necessary, so this global option makes little sense. The option was initially introduced as a work-around for build issues around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs. Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 8 -------- src/console/Makefile.inc | 4 ++-- src/cpu/allwinner/a10/Kconfig | 1 - src/cpu/armltd/cortex-a9/Kconfig | 1 - src/cpu/samsung/exynos5250/Kconfig | 1 - src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/cpu/samsung/exynos5420/Kconfig | 1 - src/cpu/samsung/exynos5420/Makefile.inc | 2 +- src/cpu/ti/am335x/Kconfig | 1 - src/drivers/uart/Makefile.inc | 2 +- src/drivers/usb/Kconfig | 2 +- src/include/console/console.h | 3 +-- src/mainboard/aopen/dxplplusu/romstage.c | 2 +- src/mainboard/dmp/vortex86ex/Kconfig | 1 - 14 files changed, 8 insertions(+), 23 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 703e5c7..887c1e2 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -7,17 +7,9 @@ config BOOTBLOCK_CONSOLE help Use console during the bootblock if supported -config EARLY_CONSOLE - bool "Enable early (pre-RAM) console output." - default y if CACHE_AS_RAM - default n - help - Use console during early (pre-RAM) boot stages - config SQUELCH_EARLY_SMP bool "Squelch AP CPUs from early console." default y - depends on EARLY_CONSOLE help When selected only the BSP CPU will output to early console. diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index e3b3780..435d704 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -6,8 +6,8 @@ ramstage-y += die.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c -romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c printk.c -romstage-$(CONFIG_EARLY_CONSOLE) += init.c console.c +romstage-y += vtxprintf.c printk.c +romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 63c4462..fbb95a1 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -9,7 +9,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index 04861a6..9a81db6 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -1,7 +1,6 @@ config CPU_ARMLTD_CORTEX_A9 depends on ARCH_ARMV7 bool - select EARLY_CONSOLE default n if CPU_ARMLTD_CORTEX_A9 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 2fda9b3..4adc000 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -2,7 +2,6 @@ config CPU_SAMSUNG_EXYNOS5250 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select EARLY_CONSOLE select DYNAMIC_CBMEM bool default n diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 3d5b5b4..a5e3456 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c ifeq ($(CONFIG_DRIVERS_UART),y) -romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +romstage-y += uart.c endif romstage-y += wakeup.c romstage-y += gpio.c diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index e46d889..3bc7486 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -2,7 +2,6 @@ config CPU_SAMSUNG_EXYNOS5420 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select EARLY_CONSOLE select DYNAMIC_CBMEM bool default n diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 844b835..279e803 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c ifeq ($(CONFIG_DRIVERS_UART),y) -romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +romstage-y += uart.c endif romstage-y += wakeup.c romstage-y += gpio.c diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index fdc5824..3eb4950 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -3,7 +3,6 @@ config CPU_TI_AM335X select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select EARLY_CONSOLE bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 5164282..c4feb9a 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -25,6 +25,6 @@ endif ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c -romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c +romstage-y += pl011.c ramstage-y += pl011.c endif diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig index f225ac1..b0baa42 100644 --- a/src/drivers/usb/Kconfig +++ b/src/drivers/usb/Kconfig @@ -35,7 +35,7 @@ if USBDEBUG config USBDEBUG_IN_ROMSTAGE bool "Enable early (pre-RAM) usbdebug" default y - depends on EARLY_CBMEM_INIT && EARLY_CONSOLE + depends on EARLY_CBMEM_INIT help Configuring USB controllers in system-agent binary may cause problems to usbdebug. Disabling this option delays usbdebug to diff --git a/src/include/console/console.h b/src/include/console/console.h index 78426b2..9e98bfc 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -42,8 +42,7 @@ void __attribute__ ((noreturn)) die(const char *msg); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \ - (ENV_ROMSTAGE && CONFIG_EARLY_CONSOLE) || \ - ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) + ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_ENABLE__ void console_init(void); diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 98701f9..94546b1 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -70,7 +70,7 @@ void main(unsigned long bist) * scrub_ecc() are recovered to stack via xmm0-xmm3. */ #if CONFIG_HW_SCRUBBER -#if ! ( CONFIG_USBDEBUG && CONFIG_EARLY_CONSOLE ) +#if !CONFIG_USBDEBUG_IN_ROMSTAGE unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1); e7505_mch_scrub_ecc(ret_addr); #endif diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index 4b130b8..e70d51d 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select ROMCC - select DEFAULT_EARLY_CONSOLE select HAVE_DEBUG_RAM_SETUP config MAINBOARD_DIR

1 0

Patch set updated for coreboot: 46a2522 uart: Support multiple ports
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5342 -gerrit commit 46a2522b9e5f711523d49de92c7dd069a80b9277 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 14 22:28:29 2014 +0200 uart: Support multiple ports The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 6 +-- src/console/Kconfig | 38 +++++------------- src/cpu/allwinner/a10/Kconfig | 49 ++---------------------- src/cpu/allwinner/a10/uart_console.c | 48 +++++++---------------- src/cpu/samsung/exynos5250/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5250/uart.c | 23 ++++++----- src/cpu/samsung/exynos5420/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5420/uart.c | 21 +++++----- src/cpu/ti/am335x/uart.c | 25 +++++++----- src/drivers/uart/oxpcie_early.c | 2 +- src/drivers/uart/pl011.c | 17 +++------ src/drivers/uart/uart8250io.c | 28 +++++++------- src/drivers/uart/uart8250mem.c | 16 ++++---- src/include/console/uart.h | 14 +++---- src/mainboard/emulation/qemu-armv7/Kconfig | 5 --- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 ++ src/mainboard/emulation/qemu-armv7/mmio.c | 21 ++++++++++ src/mainboard/ti/beaglebone/Kconfig | 51 ++----------------------- src/mainboard/ti/beaglebone/bootblock.c | 12 +++--- 19 files changed, 147 insertions(+), 311 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 6c7f050..62490fc 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -32,7 +32,7 @@ void console_hw_init(void) { #if CONFIG_CONSOLE_SERIAL - uart_init(); + uart_init(CONFIG_UART_FOR_CONSOLE); #endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); @@ -42,7 +42,7 @@ void console_hw_init(void) void console_tx_byte(unsigned char byte) { #if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); + uart_tx_byte(CONFIG_UART_FOR_CONSOLE, byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -52,7 +52,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); + uart_tx_flush(CONFIG_UART_FOR_CONSOLE); #endif #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/console/Kconfig b/src/console/Kconfig index 65fc1aa..703e5c7 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -48,39 +48,21 @@ if CONSOLE_SERIAL comment "device-specific UART" depends on HAVE_UART_SPECIAL -choice - prompt "Serial port for 8250" - default CONSOLE_SERIAL_COM1 - depends on DRIVERS_UART_8250IO - -config CONSOLE_SERIAL_COM1 - bool "COM1/ttyS0, I/O port 0x3f8" - help - Serial console on COM1/ttyS0 at I/O port 0x3f8. -config CONSOLE_SERIAL_COM2 - bool "COM2/ttyS1, I/O port 0x2f8" - help - Serial console on COM2/ttyS1 at I/O port 0x2f8. -config CONSOLE_SERIAL_COM3 - bool "COM3/ttyS2, I/O port 0x3e8" - help - Serial console on COM3/ttyS2 at I/O port 0x3e8. -config CONSOLE_SERIAL_COM4 - bool "COM4/ttyS3, I/O port 0x2e8" - help - Serial console on COM4/ttyS3 at I/O port 0x2e8. - -endchoice +config UART_FOR_CONSOLE + prompt "Index for UART port to use for console" + default 0 +# FIXME: Early programming in romstage is incorrect as we should +# program different LDN to actually change the physical port. config TTYS0_BASE hex depends on DRIVERS_UART_8250IO - default 0x3f8 if CONSOLE_SERIAL_COM1 - default 0x2f8 if CONSOLE_SERIAL_COM2 - default 0x3e8 if CONSOLE_SERIAL_COM3 - default 0x2e8 if CONSOLE_SERIAL_COM4 + default 0x3f8 if UART_FOR_CONSOLE = 0 + default 0x2f8 if UART_FOR_CONSOLE = 1 + default 0x3e8 if UART_FOR_CONSOLE = 2 + default 0x2e8 if UART_FOR_CONSOLE = 3 help - Map the COM port names to the respective I/O port. + Map the COM port number to the respective I/O port. choice prompt "Baud rate" diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 267e1f4..63c4462 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -72,51 +72,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -config CONSOLE_SERIAL_UART6 - bool "UART6" - help - Serial console on UART6 - -config CONSOLE_SERIAL_UART7 - bool "UART7" - help - Serial console on UART7 - -endchoice +config UART_FOR_CONSOLE + int + default 0 endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index d6b91e7..bb5f41c 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -14,28 +14,13 @@ #include <cpu/allwinner/a10/uart.h> -static void *get_console_uart_base_addr(void) +unsigned int uart_platform_base(int idx) { - /* This big block gets compiled to a constant, not a function call */ - if (CONFIG_CONSOLE_SERIAL_UART0) - return (void *)A1X_UART0_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART1) - return (void *)A1X_UART1_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART2) - return (void *)A1X_UART2_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART3) - return (void *)A1X_UART3_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART4) - return (void *)A1X_UART4_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART5) - return (void *)A1X_UART5_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART6) - return (void *)A1X_UART6_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART7) - return (void *)A1X_UART7_BASE; - - /* If selection is invalid, default to UART0 */ - return (void *)A1X_UART0_BASE; + /* UART blocks are mapped 0x400 bytes apart */ + if (idx < 8) + return A1X_UART0_BASE + 0x400 * idx; + else + return 0; } /* FIXME: We assume clock is 24MHz, which may not be the case. */ @@ -44,14 +29,9 @@ unsigned int uart_platform_refclk(void) return 24000000; } -unsigned int uart_platform_base(int idx) -{ - return (unsigned int)get_console_uart_base_addr(); -} - -void uart_init(void) +void uart_init(int idx) { - void *uart_base = get_console_uart_base_addr(); + void *uart_base = uart_platform_baseptr(idx); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -59,17 +39,17 @@ void uart_init(void) a10_uart_enable_fifos(uart_base); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return a10_uart_rx_blocking(get_console_uart_base_addr()); + return a10_uart_rx_blocking(uart_platform_baseptr(idx)); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - a10_uart_tx_blocking(get_console_uart_base_addr(), data); + a10_uart_tx_blocking(uart_platform_baseptr(idx), data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -78,7 +58,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 9320184..2fda9b3 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -88,41 +88,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 3 endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 1dabc09..a73a01a 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -157,30 +157,33 @@ static void exynos5_uart_tx_flush(struct s5p_uart *uart) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + if (idx < 4) + return 0x12c00000 + idx * 0x10000; + else + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_flush(uart); } @@ -189,7 +192,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 5f78cc5..e46d889 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -90,41 +90,8 @@ config SYS_SDRAM_BASE hex default 0x20000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 3 endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 290eb35..8fd4dea 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -149,28 +149,31 @@ static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + if (idx < 4) + return 0x12c00000 + idx * 0x10000; + else + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { /* Exynos5250 implements this too. */ } @@ -180,7 +183,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 858926b..d398d9a 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <stdlib.h> #include <config.h> #include <types.h> #include <console/uart.h> @@ -154,30 +155,36 @@ unsigned int uart_platform_refclk(void) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + const unsigned int bases[] = { + 0x44e09000, 0x48022000, 0x48024000, + 0x481a6000, 0x481a8000, 0x481aa000 + }; + if (idx < ARRAY_SIZE(bases)) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); return am335x_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); am335x_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -186,7 +193,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b81fa89..fd37806 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -97,7 +97,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 41e66fa..e2db877 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -21,26 +21,21 @@ static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) *uart_base = (unsigned int)data; } -unsigned int uart_platform_base(int idx) +void uart_init(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -void uart_init(void) +void uart_tx_byte(int idx, unsigned char data) { -} - -void uart_tx_byte(unsigned char data) -{ - unsigned int *uart_base = uart_platform_baseptr(0); + unsigned int *uart_base = uart_platform_baseptr(idx); pl011_uart_tx_byte(uart_base, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { return 0; } @@ -50,7 +45,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index b2f234b..f4a7b0a 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -19,6 +19,7 @@ */ #include <rules.h> +#include <stdlib.h> #include <arch/io.h> #include <console/uart.h> #include <trace.h> @@ -102,37 +103,36 @@ static void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } -/* FIXME: Needs uart index from Kconfig. - * Already use array as a work-around for ROMCC. - */ -static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; +static const unsigned bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; unsigned int uart_platform_base(int idx) { - return bases[idx]; + if (idx < ARRAY_SIZE(bases)) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, BAUDRATE_OVERSAMPLE); - uart8250_init(bases[0], div); + uart8250_init(uart_platform_base(idx), div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - uart8250_tx_byte(bases[0], data); + uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return uart8250_rx_byte(bases[0]); + return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - uart8250_tx_flush(bases[0]); + uart8250_tx_flush(uart_platform_base(idx)); } #if ENV_RAMSTAGE @@ -140,7 +140,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5a186f0..976bcb6 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -89,9 +89,9 @@ static void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -void uart_init(void) +void uart_init(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; @@ -100,25 +100,25 @@ void uart_init(void) uart8250_mem_init(base, div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return 0xff; return uart8250_mem_rx_byte(base); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_flush(base); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 5866ca4..b08cd9b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -40,10 +40,10 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); -void uart_init(void); -void uart_tx_byte(unsigned char data); -void uart_tx_flush(void); -unsigned char uart_rx_byte(void); +void uart_init(int idx); +void uart_tx_byte(int idx, unsigned char data); +void uart_tx_flush(int idx); +unsigned char uart_rx_byte(int idx); unsigned int uart_platform_base(int idx); @@ -60,9 +60,9 @@ void oxford_remap(unsigned int new_base); (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_SERIAL_ENABLE__ -static inline void __uart_init(void) { uart_init(); } -static inline void __uart_tx_byte(u8 data) { uart_tx_byte(data); } -static inline void __uart_tx_flush(void) { uart_tx_flush(); } +static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } +static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } +static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 040ed9c..6d04216 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -48,11 +48,6 @@ config DRAM_SIZE_MB int default 1024 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x10009000 - # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index d15495f..e088da6 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,3 +21,7 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c diff --git a/src/mainboard/emulation/qemu-armv7/mmio.c b/src/mainboard/emulation/qemu-armv7/mmio.c new file mode 100644 index 0000000..02473e4 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/mmio.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> + +#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) + +unsigned int uart_platform_base(int idx) +{ + return VEXPRESS_UART0_IO_ADDRESS; +} diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index c842a5d..a24fcde 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -61,54 +61,9 @@ config CBFS_HEADER_ROM_OFFSET hex default 0x10 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x44e09000 if CONSOLE_SERIAL_UART0 - default 0x48022000 if CONSOLE_SERIAL_UART1 - default 0x48024000 if CONSOLE_SERIAL_UART2 - default 0x481a6000 if CONSOLE_SERIAL_UART3 - default 0x481a8000 if CONSOLE_SERIAL_UART4 - default 0x481aa000 if CONSOLE_SERIAL_UART5 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 0 ################################################################# # stuff from smdk5250.h # diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 9e0a62e..6cc7a8c 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -42,22 +42,22 @@ void bootblock_mainboard_init(void) setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); /* Set up the UART we're going to use */ - if (CONFIG_CONSOLE_SERIAL_UART0) { + if (CONFIG_UART_FOR_CONSOLE == 0) { am335x_pinmux_uart0(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); - } else if (CONFIG_CONSOLE_SERIAL_UART1) { + } else if (CONFIG_UART_FOR_CONSOLE == 1) { am335x_pinmux_uart1(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); - } else if (CONFIG_CONSOLE_SERIAL_UART2) { + } else if (CONFIG_UART_FOR_CONSOLE == 2) { am335x_pinmux_uart2(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); - } else if (CONFIG_CONSOLE_SERIAL_UART3) { + } else if (CONFIG_UART_FOR_CONSOLE == 3) { am335x_pinmux_uart3(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); - } else if (CONFIG_CONSOLE_SERIAL_UART4) { + } else if (CONFIG_UART_FOR_CONSOLE == 4) { am335x_pinmux_uart4(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); - } else if (CONFIG_CONSOLE_SERIAL_UART5) { + } else if (CONFIG_UART_FOR_CONSOLE == 5) { am335x_pinmux_uart5(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); }

1 0

Patch set updated for coreboot: 540116c console: Add console for GDB
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5343 -gerrit commit 540116c3c519fb260f292d9f108ab616089b1062 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 15:05:28 2014 +0300 console: Add console for GDB Connection of UARTs to GDB stub got lost in the console transition process, bring it back. In theory, GDB stub should work also over usbdebug, but that solution is not really tested at all yet. Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/c_start.S | 1 + src/arch/x86/lib/exception.c | 13 +++++++++++-- src/console/console.c | 24 ++++++++++++++++++++++++ src/include/console/streams.h | 6 ++++++ src/include/console/uart.h | 8 ++++++++ src/include/console/usb.h | 16 ++++++++++++++-- 6 files changed, 64 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index faea22d..675a09c 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -86,6 +86,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT + call gdb_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..f64b2e7 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <console/streams.h> #include <string.h> #if CONFIG_GDB_STUB @@ -217,12 +218,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - console_tx_byte(ch); + gdb_tx_byte(ch); +} + +static inline void stub_flush(void) +{ + gdb_tx_flush(); } static inline int stub_getc(void) { - return console_rx_byte(); + return gdb_rx_byte(); } static int hex(char ch) @@ -322,9 +328,11 @@ static int get_packet(char *buffer) if (checksum != xmitcsum) { stub_putc('-'); /* failed checksum */ + stub_flush(); } else { stub_putc('+'); /* successful transfer */ + stub_flush(); } } } while(checksum != xmitcsum); @@ -353,6 +361,7 @@ static void put_packet(char *buffer) stub_putc('#'); stub_putc(hexchars[checksum >> 4]); stub_putc(hexchars[checksum % 16]); + stub_flush(); } while ((stub_getc() & 0x7f) != '+'); diff --git a/src/console/console.c b/src/console/console.c index 9b1c255..bd03144 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <rules.h> #include <console/streams.h> #include <console/cbmem_console.h> #include <console/uart.h> @@ -53,3 +54,26 @@ void console_tx_flush(void) __ne2k_tx_flush(); __usb_tx_flush(); } + + +#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) +void gdb_hw_init(void) +{ + __gdb_hw_init(); +} + +void gdb_tx_byte(unsigned char byte) +{ + __gdb_tx_byte(byte); +} + +void gdb_tx_flush(void) +{ + __gdb_tx_flush(); +} + +unsigned char gdb_rx_byte(void) +{ + return __gdb_rx_byte(); +} +#endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 9d4d3fc..fb168da 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -22,6 +22,12 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* For remote GDB debugging. */ +void gdb_hw_init(void); +void gdb_tx_byte(unsigned char byte); +void gdb_tx_flush(void); +unsigned char gdb_rx_byte(void); + /* Helpers for ROMCC console. */ void console_tx_nibble(unsigned nibble); void console_tx_hex8(unsigned char value); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index b08cd9b..d4020c3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -69,6 +69,14 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif +#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE +static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +#endif + #endif /* __ROMCC__ */ #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 57ea4eb..b5aab66 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -34,14 +34,26 @@ int usb_can_rx_byte(int idx); #define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +#define USB_PIPE_FOR_CONSOLE 0 +#define USB_PIPE_FOR_GDB 0 + #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } -static inline void __usb_tx_byte(u8 data) { usb_tx_byte(0, data); } -static inline void __usb_tx_flush(void) { usb_tx_flush(0); } +static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } +static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} #endif +/* */ +#if 0 && CONFIG_GDB_STUB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +#endif + #endif /* _CONSOLE_USB_H_ */

1 0

Patch set updated for coreboot: ed5f5a4 allwinner/a10: Hide SoC specific UART functions
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5469 -gerrit commit ed5f5a4fb26d565d0c19c7fa29a10da798248d24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 20:32:59 2014 +0300 allwinner/a10: Hide SoC specific UART functions If platform has a component coreboot has to communicate with using one of the UARTs, that device would not be part of the SoC and must not use functions specific to a10 UART. Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 40 ++++++++++++++++++++++++++---------- src/cpu/allwinner/a10/uart.h | 7 ------- src/cpu/allwinner/a10/uart_console.c | 28 +------------------------ 3 files changed, 30 insertions(+), 45 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 1885ace..feccc82 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -13,12 +13,11 @@ /** * \brief Configure line control settings for UART */ -void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, +static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits, enum uart_parity parity, u8 stop_bits) { u32 reg32; u16 div; - struct a10_uart *uart = uart_base; div = (u16) uart_baudrate_divisor(baud_rate, uart_platform_refclk(), 16); @@ -44,10 +43,8 @@ void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, write32(reg32, &uart->lcr); } -void a10_uart_enable_fifos(void *uart_base) +static void a10_uart_enable_fifos(struct a10_uart *uart) { - struct a10_uart *uart = uart_base; - write32(UART_FCR_FIFO_EN, &uart->fcr); } @@ -70,10 +67,8 @@ static int rx_fifo_empty(struct a10_uart *uart) * * Blocks until at least a byte is available. */ -u8 a10_uart_rx_blocking(void *uart_base) +static u8 a10_uart_rx_blocking(struct a10_uart *uart) { - struct a10_uart *uart = uart_base; - while (rx_fifo_empty(uart)) ; return read32(&uart->rbr); @@ -84,11 +79,34 @@ u8 a10_uart_rx_blocking(void *uart_base) * * Blocks until there is space in the FIFO. */ -void a10_uart_tx_blocking(void *uart_base, u8 data) +static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { - struct a10_uart *uart = uart_base; - while (tx_fifo_full(uart)) ; return write32(data, &uart->thr); } + + +void uart_init(int idx) +{ + struct a10_uart *uart_base = uart_platform_baseptr(idx); + + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, default_baudrate(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +unsigned char uart_rx_byte(int idx) +{ + return a10_uart_rx_blocking(uart_platform_baseptr(idx)); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + a10_uart_tx_blocking(uart_platform_baseptr(idx), data); +} + +void uart_tx_flush(int idx) +{ +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h index 86ab487..aa94362 100644 --- a/src/cpu/allwinner/a10/uart.h +++ b/src/cpu/allwinner/a10/uart.h @@ -13,7 +13,6 @@ #ifndef CPU_ALLWINNER_A10_UART_H #define CPU_ALLWINNER_A10_UART_H -#include "memmap.h" #include <types.h> struct a10_uart { @@ -68,10 +67,4 @@ enum uart_parity { UART_PARITY_ODD, }; -void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, - enum uart_parity parity, u8 stop_bits); -void a10_uart_enable_fifos(void *uart_base); -u8 a10_uart_rx_blocking(void *uart_base); -void a10_uart_tx_blocking(void *uart_base, u8 data); - #endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index bb5f41c..b787961 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -6,13 +6,11 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -#include <config.h> #include <types.h> #include <console/uart.h> -#include <arch/io.h> #include <boot/coreboot_tables.h> -#include <cpu/allwinner/a10/uart.h> +#include "memmap.h" unsigned int uart_platform_base(int idx) { @@ -29,30 +27,6 @@ unsigned int uart_platform_refclk(void) return 24000000; } -void uart_init(int idx) -{ - void *uart_base = uart_platform_baseptr(idx); - - /* Use default 8N1 encoding */ - a10_uart_configure(uart_base, default_baudrate(), - 8, UART_PARITY_NONE, 1); - a10_uart_enable_fifos(uart_base); -} - -unsigned char uart_rx_byte(int idx) -{ - return a10_uart_rx_blocking(uart_platform_baseptr(idx)); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - a10_uart_tx_blocking(uart_platform_baseptr(idx), data); -} - -void uart_tx_flush(int idx) -{ -} - #ifndef __PRE_RAM__ void uart_fill_lb(void *data) {

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Patch set updated for coreboot: df50e3b device: provide option to always load PCI option roms
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5594 -gerrit commit df50e3b56ede96d8a4b55135aa9fc4097c9b5fc2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 4 10:21:31 2014 -0600 device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 12 ++++++++++++ src/device/pci_device.c | 50 +++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 52 insertions(+), 10 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 932b4de..ab7a577 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -70,6 +70,18 @@ config S3_VGA_ROM_RUN If unsure, say N when using SeaBIOS as payload, Y otherwise. +config ALWAYS_LOAD_OPROM + def_bool n + depends on VGA_ROM_RUN + help + Always load option roms if any are found. The decision to run + the rom is still determined at runtime, but the distinction + between loading and not running comes into play for CHROMEOS. + + An example where this is required is that VBT (video bios tables) + are needed for the kernel's display driver to know how a piece of + hardware is configured to be used. + config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_device.c b/src/device/pci_device.c index aa0d954..ca36046 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -23,6 +23,7 @@ * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ +#include <kconfig.h> #include <console/console.h> #include <stdlib.h> #include <stdint.h> @@ -663,15 +664,13 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) int oprom_is_loaded = 0; #endif -/** Default handler: only runs the relevant PCI BIOS. */ -void pci_dev_init(struct device *dev) -{ #if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; +static int should_run_oprom(struct device *dev) +{ + static int should_run = -1; - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; + if (should_run >= 0) + return should_run; #if CONFIG_CHROMEOS /* In ChromeOS we want to boot blazingly fast. Therefore @@ -680,19 +679,47 @@ void pci_dev_init(struct device *dev) */ if (!developer_mode_enabled() && !recovery_mode_enabled() && !vboot_wants_oprom()) { - printk(BIOS_DEBUG, "Not loading VGA Option ROM\n"); - return; + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + should_run = 0; + return should_run; } #endif + should_run = 1; + + return should_run; +} +static int should_load_oprom(struct device *dev) +{ #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. */ if ((acpi_slp_type == 3) && ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return; + return 0; #endif + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (should_run_oprom(dev)) + return 1; + + return 0; +} +#endif /* CONFIG_VGA_ROM_RUN */ + +/** Default handler: only runs the relevant PCI BIOS. */ +void pci_dev_init(struct device *dev) +{ +#if CONFIG_VGA_ROM_RUN + struct rom_header *rom, *ram; + + /* Only execute VGA ROMs. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + if (!should_load_oprom(dev)) + return; rom = pci_rom_probe(dev); if (rom == NULL) @@ -702,6 +729,9 @@ void pci_dev_init(struct device *dev) if (ram == NULL) return; + if (!should_run_oprom(dev)) + return; + run_bios(dev, (unsigned long)ram); #if CONFIG_CHROMEOS oprom_is_loaded = 1;

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Patch set updated for coreboot: ad6f030 Build without ChromeOS
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3978 -gerrit commit ad6f030bddcaeb07aac1b4c218a3c97b53f9641e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:56 2013 +0300 Build without ChromeOS Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/google/chromeos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index b4838fd..a1a9d9a 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -24,7 +24,7 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" - default y + default n select TPM select BOOTMODE_STRAPS help

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Patch set updated for coreboot: ea32468 device: Conditionally bypass oprom execution
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5595 -gerrit commit ea324684e812c63eabc4c93594e91e5130be4967 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 00:22:49 2013 +0200 device: Conditionally bypass oprom execution Builds with CHROMEOS can bypass VGA oprom when boot is not in developer or recovery modes. Have the same functionality available without CHROMEOS but with BOOTMODE_STRAPS. Change-Id: I97644364305dc05aad78a744599476ccc58db163 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index dfc0898..f09fcaa 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -669,20 +669,18 @@ static int should_run_oprom(struct device *dev) if (should_run >= 0) return should_run; -#if CONFIG_CHROMEOS - /* In ChromeOS we want to boot blazingly fast. Therefore - * we don't run (VGA) option ROMs, unless we have to print + /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. */ - if (!developer_mode_enabled() && !recovery_mode_enabled() && - !vboot_wants_oprom()) { - printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); - should_run = 0; - return should_run; - } -#endif - should_run = 1; + should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || + developer_mode_enabled() || recovery_mode_enabled(); +#if CONFIG_CHROMEOS + if (!should_run) + should_run = vboot_wants_oprom(); +#endif + if (!should_run) + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); return should_run; }

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Patch set updated for coreboot: c2166ce google/stout: Fix build without ChromeOS
by Kyösti Mälkki 29 Apr '14

29 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5596 -gerrit commit c2166ced644a10423255d35feb285ed6569c0436 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 27 22:17:22 2014 +0300 google/stout: Fix build without ChromeOS Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/stout/chromeos.c | 5 ++--- src/mainboard/google/stout/ec.c | 5 +++-- src/mainboard/google/stout/romstage.c | 4 +++- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 7a861ec..0e43250 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -35,9 +35,6 @@ #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 -static int ec_in_rec_mode; -static int ec_rec_flag_good; - void fill_lb_gpios(struct lb_gpios *gpios) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); @@ -115,6 +112,8 @@ int get_recovery_mode_switch(void) #ifdef __PRE_RAM__ device_t dev = PCI_DEV(0, 0x1f, 0); #else + static int ec_in_rec_mode = 0; + static int ec_rec_flag_good = 0; device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 474d96f..69b5bef 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -19,7 +19,7 @@ #include <arch/acpi.h> #include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <types.h> #include <console/console.h> #include <ec/quanta/it8518/ec.h> @@ -43,7 +43,8 @@ void stout_ec_init(void) /* * Important: get_recovery_mode_switch() must be called in EC init. */ - get_recovery_mode_switch(); + if (IS_ENABLED(CONFIG_BOOTMODE_STRAPS)) + get_recovery_mode_switch(); /* Unmute */ ec_kbc_write_cmd(EC_KBD_CMD_UNMUTE); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 0ea53e7..f53c07d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -38,6 +38,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" +#include <bootmode.h> #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -131,7 +132,8 @@ static void early_pch_init(void) static void early_ec_init(void) { u8 ec_status = ec_read(EC_STATUS_REG); - int rec_mode = get_recovery_mode_switch(); + int rec_mode = IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && + get_recovery_mode_switch(); if (((ec_status & 0x3) == EC_IN_RO_MODE) || ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {

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coreboot-gerrit April 2014