coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a66a5ae payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4
by Paul Menzel 27 Apr '14

27 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit a66a5ae1c42bbf2a406eb49e939d3bd4c3d73a03 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4 SeaBIOS 1.7.4 was released in December 2013 [1] and, besides other things, supports writing debug messages to CBMEM console. The new SeaBIOS Kconfig option `DEBUG_COREBOOT` has to be added to the SeaBIOS configuration file `.config` as otherwise the SeaBIOS build from within coreboot (`PAYLOAD_SEABIOS`) is interrupted as it is detected as a new option. This option was already added and enabled in commit 7c1a49bc [1] SeaBIOS: have coreboot pass the choice to run optionroms in parallel so SeaBIOS messages are now written to the CBMEM console. Successfully tested on the Asus M2V-MX SE. [1] http://seabios.org/Releases [2] http://review.coreboot.org/5443 Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..291b166 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -617,7 +617,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

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Patch set updated for coreboot: 6abc872 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments
by Paul Menzel 27 Apr '14

27 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5388 -gerrit commit 6abc872d3cb4a9dbbdb24db9df3e598fbe8132e8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 16 00:15:57 2014 +0100 util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments cbfstool fails to built under 32-bit platforms since commit aa2f739a cbfs: fix issues with word size and endianness. due to the use of '%ld' format specifier on size_t, which on these platforms is only 32-bit. No error is seen when building a coreboot image which indirectly builds cbfstool at `build/cbfstool` too. Use the length modifier `z` for size_t arguments, and cast to size_t where apropriate. [1] http://review.coreboot.org/4817 Change-Id: Id84a20fbf237376a31f7e4816bd139463800c977 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/cbfs-mkstage.c | 4 ++-- util/cbfstool/elfheaders.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 6aa3746..2a92c9f 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -132,8 +132,8 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, continue; if (input->size < (phdr[i].p_offset + phdr[i].p_filesz)){ ERROR("Underflow copying out the segment." - "File has %ld bytes left, segment end is %ld\n", - input->size, phdr[i].p_offset + phdr[i].p_filesz); + "File has %zu bytes left, segment end is %zu\n", + input->size, (size_t)(phdr[i].p_offset + phdr[i].p_filesz)); return -1; } memcpy(buffer + (l_start - data_start), diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index d217aac..5b5cf94 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -147,7 +147,7 @@ check_size(const struct buffer *b, size_t offset, size_t size, const char *desc) if (offset >= buffer_size(b) || (offset + size) > buffer_size(b)) { ERROR("The file is not large enough for the '%s'. " - "%ld bytes @ offset %zu, input %zu bytes.\n", + "%zu bytes @ offset %zu, input %zu bytes.\n", desc, size, offset, buffer_size(b)); return -1; }

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Patch set updated for coreboot: df7c924 lenovo/{t60, x60}/devicetree.cb: Fix typo in Controller in comment
by Paul Menzel 27 Apr '14

27 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5325 -gerrit commit df7c924fe2979814b074e12205e6bdfb347dcb16 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Mar 3 09:18:18 2014 +0100 lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in comment $ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g' Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/t60/devicetree.cb | 2 +- src/mainboard/lenovo/x60/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..f092380 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -71,7 +71,7 @@ chip northbridge/intel/i945 register "c4onc3_enable" = "1" - device pci 1b.0 on # Audio Cnotroller + device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 end device pci 1c.0 on # Ethernet diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..fbef3bf 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -63,7 +63,7 @@ chip northbridge/intel/i945 register "alt_gp_smi_en" = "0x1000" register "c4onc3_enable" = "1" - device pci 1b.0 on # Audio Cnotroller + device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x2010 end device pci 1c.0 on end # Ethernet

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Patch set updated for coreboot: dee9d4a Build without ChromeOS
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3978 -gerrit commit dee9d4a5e254a0a06c89f59efc7e22ef1deca7e0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:56 2013 +0300 Build without ChromeOS Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/google/chromeos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index b4838fd..a1a9d9a 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -24,7 +24,7 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" - default y + default n select TPM select BOOTMODE_STRAPS help

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Patch set updated for coreboot: a64fb6f device: Conditionally bypass oprom execution
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5595 -gerrit commit a64fb6fd43beb7d7b069975a7f9b2afddebeccd4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 00:22:49 2013 +0200 device: Conditionally bypass oprom execution Builds with CHROMEOS can bypass VGA oprom when boot is not in developer or recovery modes. Have the same functionality available without CHROMEOS but with BOOTMODE_STRAPS. Change-Id: I97644364305dc05aad78a744599476ccc58db163 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index d5f150c..0641ab8 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -33,6 +33,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <bootmode.h> #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT #include <device/hypertransport.h> #endif @@ -668,20 +669,18 @@ static int should_run_oprom(struct device *dev) if (should_run >= 0) return should_run; -#if CONFIG_CHROMEOS - /* In ChromeOS we want to boot blazingly fast. Therefore - * we don't run (VGA) option ROMs, unless we have to print + /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. */ - if (!developer_mode_enabled() && !recovery_mode_enabled() && - !vboot_wants_oprom()) { - printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); - should_run = 0; - return should_run; - } -#endif - should_run = 1; + should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || + developer_mode_enabled() || recovery_mode_enabled(); +#if CONFIG_CHROMEOS + if (!should_run) + should_run = vboot_wants_oprom(); +#endif + if (!should_run) + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); return should_run; }

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Patch set updated for coreboot: 4d7616b google/stout: Fix build without ChromeOS
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5596 -gerrit commit 4d7616bd96fd04aa60cb9add2482684b8a348a95 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 27 22:17:22 2014 +0300 google/stout: Fix build without ChromeOS Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/stout/chromeos.c | 5 ++--- src/mainboard/google/stout/ec.c | 5 +++-- src/mainboard/google/stout/romstage.c | 4 +++- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 0fef6e7..e8c5752 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -33,9 +33,6 @@ #define GPIO_COUNT 7 -static int ec_in_rec_mode; -static int ec_rec_flag_good; - void fill_lb_gpios(struct lb_gpios *gpios) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); @@ -113,6 +110,8 @@ int get_recovery_mode_switch(void) #ifdef __PRE_RAM__ device_t dev = PCI_DEV(0, 0x1f, 0); #else + static int ec_in_rec_mode = 0; + static int ec_rec_flag_good = 0; device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 474d96f..69b5bef 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -19,7 +19,7 @@ #include <arch/acpi.h> #include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <types.h> #include <console/console.h> #include <ec/quanta/it8518/ec.h> @@ -43,7 +43,8 @@ void stout_ec_init(void) /* * Important: get_recovery_mode_switch() must be called in EC init. */ - get_recovery_mode_switch(); + if (IS_ENABLED(CONFIG_BOOTMODE_STRAPS)) + get_recovery_mode_switch(); /* Unmute */ ec_kbc_write_cmd(EC_KBD_CMD_UNMUTE); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 0ea53e7..f53c07d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -38,6 +38,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" +#include <bootmode.h> #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -131,7 +132,8 @@ static void early_pch_init(void) static void early_ec_init(void) { u8 ec_status = ec_read(EC_STATUS_REG); - int rec_mode = get_recovery_mode_switch(); + int rec_mode = IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && + get_recovery_mode_switch(); if (((ec_status & 0x3) == EC_IN_RO_MODE) || ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {

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New patch to review for coreboot: 8e6b180 google/stout: Fix build without ChromeOS
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5596 -gerrit commit 8e6b180dcc5b0802951c25afc42935ae78e4a15e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 27 22:17:22 2014 +0300 google/stout: Fix build without ChromeOS Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/stout/chromeos.c | 5 ++--- src/mainboard/google/stout/ec.c | 5 +++-- src/mainboard/google/stout/romstage.c | 4 +++- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 0fef6e7..e8c5752 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -33,9 +33,6 @@ #define GPIO_COUNT 7 -static int ec_in_rec_mode; -static int ec_rec_flag_good; - void fill_lb_gpios(struct lb_gpios *gpios) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); @@ -113,6 +110,8 @@ int get_recovery_mode_switch(void) #ifdef __PRE_RAM__ device_t dev = PCI_DEV(0, 0x1f, 0); #else + static int ec_in_rec_mode = 0; + static int ec_rec_flag_good = 0; device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); #endif diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 474d96f..69b5bef 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -19,7 +19,7 @@ #include <arch/acpi.h> #include <arch/io.h> -#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> #include <types.h> #include <console/console.h> #include <ec/quanta/it8518/ec.h> @@ -43,7 +43,8 @@ void stout_ec_init(void) /* * Important: get_recovery_mode_switch() must be called in EC init. */ - get_recovery_mode_switch(); + if (IS_ENABLED(CONFIG_BOOTMODE_STRAPS)) + get_recovery_mode_switch(); /* Unmute */ ec_kbc_write_cmd(EC_KBD_CMD_UNMUTE); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 0ea53e7..f53c07d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -38,6 +38,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" +#include <bootmode.h> #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -131,7 +132,8 @@ static void early_pch_init(void) static void early_ec_init(void) { u8 ec_status = ec_read(EC_STATUS_REG); - int rec_mode = get_recovery_mode_switch(); + int rec_mode = IS_ENABLED(CONFIG_BOOTMODE_STRAPS) && + get_recovery_mode_switch(); if (((ec_status & 0x3) == EC_IN_RO_MODE) || ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {

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New patch to review for coreboot: b1c7440 device: Conditionally bypass oprom execution
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5595 -gerrit commit b1c7440942838a7625c8a9a72a0a7aed2f1f5982 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 00:22:49 2013 +0200 device: Conditionally bypass oprom execution Builds with CHROMEOS can bypass VGA oprom when boot is not in developer or recovery modes. Have the same functionality available without CHROMEOS but with BOOTMODE_STRAPS. Change-Id: I97644364305dc05aad78a744599476ccc58db163 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index d5f150c..3cf46b3 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -668,20 +668,18 @@ static int should_run_oprom(struct device *dev) if (should_run >= 0) return should_run; -#if CONFIG_CHROMEOS - /* In ChromeOS we want to boot blazingly fast. Therefore - * we don't run (VGA) option ROMs, unless we have to print + /* Don't run VGA option ROMs, unless we have to print * something on the screen before the kernel is loaded. */ - if (!developer_mode_enabled() && !recovery_mode_enabled() && - !vboot_wants_oprom()) { - printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); - should_run = 0; - return should_run; - } -#endif - should_run = 1; + should_run = !IS_ENABLED(CONFIG_BOOTMODE_STRAPS) || + developer_mode_enabled() || recovery_mode_enabled(); +#if CONFIG_CHROMEOS + if (!should_run) + should_run = vboot_wants_oprom(); +#endif + if (!should_run) + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); return should_run; }

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Patch set updated for coreboot: 9f25c53 Build without ChromeOS
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3978 -gerrit commit 9f25c537ccef3fe10d8a871eaeef25d389f04353 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:56 2013 +0300 Build without ChromeOS Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/google/chromeos/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index b4838fd..a1a9d9a 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -24,7 +24,7 @@ menu "ChromeOS" config CHROMEOS bool "Build for ChromeOS" - default y + default n select TPM select BOOTMODE_STRAPS help

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New patch to review for coreboot: 603548f device: provide option to always load PCI option roms
by Kyösti Mälkki 27 Apr '14

27 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5594 -gerrit commit 603548f058dcc580e48e32c88d3e8af40ee4443f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 4 10:21:31 2014 -0600 device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 12 ++++++++++++ src/device/pci_device.c | 50 +++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 52 insertions(+), 10 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 932b4de..ab7a577 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -70,6 +70,18 @@ config S3_VGA_ROM_RUN If unsure, say N when using SeaBIOS as payload, Y otherwise. +config ALWAYS_LOAD_OPROM + def_bool n + depends on VGA_ROM_RUN + help + Always load option roms if any are found. The decision to run + the rom is still determined at runtime, but the distinction + between loading and not running comes into play for CHROMEOS. + + An example where this is required is that VBT (video bios tables) + are needed for the kernel's display driver to know how a piece of + hardware is configured to be used. + config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 24d0552..d5f150c 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -23,6 +23,7 @@ * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ +#include <kconfig.h> #include <console/console.h> #include <stdlib.h> #include <stdint.h> @@ -659,15 +660,13 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } -/** Default handler: only runs the relevant PCI BIOS. */ -void pci_dev_init(struct device *dev) -{ #if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; +static int should_run_oprom(struct device *dev) +{ + static int should_run = -1; - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; + if (should_run >= 0) + return should_run; #if CONFIG_CHROMEOS /* In ChromeOS we want to boot blazingly fast. Therefore @@ -676,19 +675,47 @@ void pci_dev_init(struct device *dev) */ if (!developer_mode_enabled() && !recovery_mode_enabled() && !vboot_wants_oprom()) { - printk(BIOS_DEBUG, "Not loading VGA Option ROM\n"); - return; + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + should_run = 0; + return should_run; } #endif + should_run = 1; + + return should_run; +} +static int should_load_oprom(struct device *dev) +{ #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. */ if ((acpi_slp_type == 3) && ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return; + return 0; #endif + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (should_run_oprom(dev)) + return 1; + + return 0; +} +#endif /* CONFIG_VGA_ROM_RUN */ + +/** Default handler: only runs the relevant PCI BIOS. */ +void pci_dev_init(struct device *dev) +{ +#if CONFIG_VGA_ROM_RUN + struct rom_header *rom, *ram; + + /* Only execute VGA ROMs. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + if (!should_load_oprom(dev)) + return; rom = pci_rom_probe(dev); if (rom == NULL) @@ -698,6 +725,9 @@ void pci_dev_init(struct device *dev) if (ram == NULL) return; + if (!should_run_oprom(dev)) + return; + run_bios(dev, (unsigned long)ram); dev->oprom_is_loaded = 1; printk(BIOS_DEBUG, "VGA Option ROM has been loaded\n");

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coreboot-gerrit April 2014