coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

1 participants
584 discussions

Patch set updated for coreboot: 8e482b1 Kconfig: Unify IDS options for all six AGESA trees into a vendorcode menu
by Alexandru Gagniuc 31 Mar '14

31 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5161 -gerrit commit 8e482b1e5e14cc53d46321da159516111b803121 Author: Peter Stuge <peter(a)stuge.se> Date: Fri Feb 7 03:57:36 2014 +0100 Kconfig: Unify IDS options for all six AGESA trees into a vendorcode menu Change-Id: I5bea6d777581c0cae537cb8cfd196c3ac9fc1a37 Signed-off-by: Peter Stuge <peter(a)stuge.se> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/family10/Kconfig | 8 - src/cpu/amd/agesa/family15/Kconfig | 8 - src/mainboard/amd/dinar/OptionsIds.h | 64 ------- src/mainboard/amd/inagua/OptionsIds.h | 64 ------- src/mainboard/amd/olivehill/OptionsIds.h | 67 ------- src/mainboard/amd/parmer/OptionsIds.h | 67 ------- src/mainboard/amd/persimmon/OptionsIds.h | 64 ------- src/mainboard/amd/south_station/OptionsIds.h | 64 ------- src/mainboard/amd/thatcher/OptionsIds.h | 67 ------- src/mainboard/amd/torpedo/OptionsIds.h | 64 ------- src/mainboard/amd/union_station/OptionsIds.h | 64 ------- src/mainboard/asrock/e350m1/OptionsIds.h | 66 ------- src/mainboard/asrock/imb-a180/OptionsIds.h | 67 ------- src/mainboard/asus/f2a85-m/OptionsIds.h | 67 ------- src/mainboard/gizmosphere/gizmo/OptionsIds.h | 65 ------- src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 67 ------- src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h | 64 ------- src/mainboard/lippert/frontrunner-af/OptionsIds.h | 64 ------- src/mainboard/lippert/toucan-af/OptionsIds.h | 64 ------- src/mainboard/supermicro/h8qgi/OptionsIds.h | 66 ------- src/mainboard/supermicro/h8scm/OptionsIds.h | 67 ------- src/mainboard/tyan/s8226/OptionsIds.h | 67 ------- src/vendorcode/Kconfig | 1 + src/vendorcode/amd/Kconfig | 1 + src/vendorcode/amd/agesa/Kconfig | 203 ++++++++++++++++++++++ src/vendorcode/amd/agesa/Makefile.inc | 2 + src/vendorcode/amd/agesa/OptionsIds.h | 37 ++++ src/vendorcode/amd/agesa/f10/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f12/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f15/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 2 +- 33 files changed, 250 insertions(+), 1331 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 621ee58..ae5a09e 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -49,12 +49,4 @@ config HAVE_INIT_TIMER bool default y -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 02991a0..963ef42 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -70,12 +70,4 @@ config HAVE_INIT_TIMER bool default y -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h deleted file mode 100644 index a756942..0000000 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h deleted file mode 100644 index 4e86877..0000000 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h deleted file mode 100644 index 600753c..0000000 --- a/src/mainboard/asrock/e350m1/OptionsIds.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h deleted file mode 100644 index 0a1d328..0000000 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h deleted file mode 100644 index bf7eedc..0000000 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h deleted file mode 100755 index 3655b5e..0000000 --- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/lippert/toucan-af/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h deleted file mode 100644 index cdf1701..0000000 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/supermicro/h8scm/OptionsIds.h b/src/mainboard/supermicro/h8scm/OptionsIds.h deleted file mode 100644 index bf719bf..0000000 --- a/src/mainboard/supermicro/h8scm/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/tyan/s8226/OptionsIds.h b/src/mainboard/tyan/s8226/OptionsIds.h deleted file mode 100644 index ceb336f..0000000 --- a/src/mainboard/tyan/s8226/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/vendorcode/Kconfig b/src/vendorcode/Kconfig index a8cbe02..9b6e5d4 100644 --- a/src/vendorcode/Kconfig +++ b/src/vendorcode/Kconfig @@ -1,2 +1,3 @@ +source src/vendorcode/amd/Kconfig source src/vendorcode/google/Kconfig source src/vendorcode/intel/Kconfig diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig new file mode 100644 index 0000000..e59f40e --- /dev/null +++ b/src/vendorcode/amd/Kconfig @@ -0,0 +1 @@ +source src/vendorcode/amd/agesa/Kconfig diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..ddcc4e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,203 @@ +if CPU_AMD_AGESA +menu "AGESA" + +config VENDORCODE_AMD_AGESA_F10 + def_bool y if CPU_AMD_AGESA_FAMILY10 + +config VENDORCODE_AMD_AGESA_F12 + def_bool y if CPU_AMD_AGESA_FAMILY12 + +config VENDORCODE_AMD_AGESA_F14 + def_bool y if CPU_AMD_AGESA_FAMILY14 + +config VENDORCODE_AMD_AGESA_F15 + def_bool y if CPU_AMD_AGESA_FAMILY15 + +config VENDORCODE_AMD_AGESA_F15TN + def_bool y if CPU_AMD_AGESA_FAMILY15_TN + +config VENDORCODE_AMD_AGESA_F16KB + def_bool y if CPU_AMD_AGESA_FAMILY16_KB + +config VENDORCODE_AMD_AGESA_R12067 + def_bool y if VENDORCODE_AMD_AGESA_F10 + +config VENDORCODE_AMD_AGESA_R38300 + def_bool y if CPU_AMD_AGESA_FAMILY14 + select VENDORCODE_AMD_AGESA_R12067 + +config VENDORCODE_AMD_AGESA_R44324 + def_bool y if VENDORCODE_AMD_AGESA_F12 || VENDORCODE_AMD_AGESA_F15 + select VENDORCODE_AMD_AGESA_R38300 + +config VENDORCODE_AMD_AGESA_R63425 + def_bool y if VENDORCODE_AMD_AGESA_F15TN + select VENDORCODE_AMD_AGESA_R44324 + +config VENDORCODE_AMD_AGESA_R84150 + def_bool y if VENDORCODE_AMD_AGESA_F16KB + select VENDORCODE_AMD_AGESA_R63425 + + +config IDSOPT_IDS_ENABLED + bool "Integrated Debug Support" + default n + help + Integrated Debug Support Module is used to debug AGESA events. + +config IDSOPT_CONTROL_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + + Support *skip* hooks for IDS options. + +config IDSOPT_CONTROL_NV_TO_CMOS + def_bool n + depends on IDSOPT_IDS_ENABLED && VENDORCODE_AMD_AGESA_R44324 + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDS_OPT_CMOS_INDEX_PORT + hex "IDS NVRAM index I/O port" + default 0x70 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_DATA_PORT + hex "IDS NVRAM data I/O port" + default 0x71 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_REGION_START + hex "IDS NVRAM region start" + default 0x20 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_REGION_END + hex "IDS NVRAM region end" + default 0x7f + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDSOPT_TRACING_ENABLED + bool "Enable trace messages" + default y + depends on IDSOPT_IDS_ENABLED + help + This option enables trace message output by AGESA at runtime. + +config IDSOPT_CUSTOMIZE_TRACING_SERVICE + def_bool n + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_R63425 + help + This IDS option is dead code in the current coreboot AGESA sources. + + The option allows to create custom trace handlers which would + replace the AGESA-internal tracing support. + +choice + prompt "Output trace messages to" + default IDSOPT_TRACING_CONSOLE_SERIALPORT + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_R63425 + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "coreboot console" + depends on VENDORCODE_AMD_AGESA_F10 || VENDORCODE_AMD_AGESA_F15 + help + Output trace messages to the coreboot console. + +config IDSOPT_TRACING_CONSOLE_HDTOUT + bool "hardware debug tool" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a Hardware Debug Tool. + +config IDSOPT_TRACING_CONSOLE_SERIALPORT + bool "serial port" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a 16550-compatible UART. + +config IDSOPT_TRACING_CONSOLE_REDIRECT_IO + bool "I/O port" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a custom I/O port. + +endchoice + +config IDSOPT_SERIAL_PORT + hex "Serial port I/O port" + default 0x3f8 + depends on IDSOPT_TRACING_ENABLED && IDSOPT_TRACING_CONSOLE_SERIALPORT + +config IDSOPT_DEBUG_PRINT_IO_PORT + hex "I/O port" + default 0x80 + depends on IDSOPT_TRACING_ENABLED && IDSOPT_TRACING_CONSOLE_REDIRECT_IO + +config IDSOPT_C_OPTIMIZATION_DISABLED + def_bool n if IDSOPT_TRACING_ENABLED + def_bool y if !IDSOPT_TRACING_ENABLED + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_F14 + help + Disable printk(BIOS_DEBUG) for IDS_HDT_CONSOLE messages. + +config IDSOPT_PERF_ANALYSIS + def_bool n + depends on IDSOPT_IDS_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + + The option enables collection and analysis of performance timestamps. + +config IDSOPT_ERROR_TRAP_ENABLED + bool "Trap Error events with stop code display" + default n + depends on IDSOPT_IDS_ENABLED + help + This option makes IDS trap and stop execution on an AGESA Error event. + +config IDSOPT_ASSERT_ENABLED + bool "Trap ASSERT failures with stop code display" + default y + depends on IDSOPT_IDS_ENABLED + help + This option makes IDS trap and stop execution if an ASSERT() is false. + + ASSERT is used in AGESA code for testing for fatal errors that must + be resolved before production. This is used to do parameter checks, + bounds checking, range checks and 'sanity' checks. + +config IDS_DEBUG_PORT + hex "AGESA_TESTPOINT I/O port" + default 0x80 + depends on IDSOPT_IDS_ENABLED + help + This configures the AGESA_TESTPOINT I/O port, usually the POST port. + +config IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED + select IDSOPT_ERROR_TRAP_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDSOPT_DEBUG_CODE_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED && VENDORCODE_AMD_AGESA_R38300 + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDSOPT_IDT_EXCEPTION_TRAP + bool "Trap exceptions with a 'jmp $' infinite loop" + default n + depends on IDSOPT_IDS_ENABLED && EXPERT && VENDORCODE_AMD_AGESA_F15TN + help + This option adds a 'jmp $' into every exception handler. + + Technically this option is available already with F12 but in the + coreboot AGESA sources the option only does something for F15TN. + +endmenu +endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 99356a6..f52ecd6 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -1,3 +1,5 @@ +AGESA_INC += -Isrc/vendorcode/amd/agesa + subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14 diff --git a/src/vendorcode/amd/agesa/OptionsIds.h b/src/vendorcode/amd/agesa/OptionsIds.h new file mode 100644 index 0000000..d215cff --- /dev/null +++ b/src/vendorcode/amd/agesa/OptionsIds.h @@ -0,0 +1,37 @@ +/** + * Copyright (c) 2014 Peter Stuge <peter(a)stuge.se> + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +#define IDSOPT_IDS_ENABLED (IS_ENABLED(CONFIG_IDSOPT_IDS_ENABLED) ? TRUE : FALSE) +#define IDSOPT_ERROR_TRAP_ENABLED (IS_ENABLED(CONFIG_IDSOPT_ERROR_TRAP_ENABLED) ? TRUE : FALSE) +#define IDSOPT_CONTROL_ENABLED (IS_ENABLED(CONFIG_IDSOPT_CONTROL_ENABLED) ? TRUE : FALSE) + +#define IDSOPT_TRACING_ENABLED (IS_ENABLED(CONFIG_IDSOPT_TRACING_ENABLED) ? TRUE : FALSE) +#define IDSOPT_TRACING_CONSOLE_HDTOUT (IS_ENABLED(CONFIG_IDSOPT_TRACING_CONSOLE_HDTOUT) ? TRUE : FALSE) +#define IDSOPT_TRACING_CONSOLE_SERIALPORT (IS_ENABLED(CONFIG_IDSOPT_TRACING_CONSOLE_SERIALPORT) ? TRUE : FALSE) + +#if CONFIG_IDSOPT_SERIAL_PORT +#define IDSOPT_SERIAL_PORT CONFIG_IDSOPT_SERIAL_PORT +#endif + +#define IDSOPT_TRACING_CONSOLE_REDIRECT_TO (IS_ENABLED(CONFIG_IDSOPT_TRACING_CONSOLE_REDIRECT_TO) ? TRUE : FALSE) + +#if CONFIG_IDSOPT_DEBUG_PRINT_IO_PORT +#define IDSOPT_DEBUG_PRINT_IO_PORT CONFIG_IDSOPT_DEBUG_PRINT_IO_PORT +#endif + +#define IDSOPT_PERF_ANALYSIS (IS_ENABLED(CONFIG_IDSOPT_PERF_ANALYSIS) ? TRUE : FALSE) +#define IDSOPT_ASSERT_ENABLED (IS_ENABLED(CONFIG_IDSOPT_ASSERT_ENABLED) ? TRUE : FALSE) + +#if CONFIG_IDS_DEBUG_PORT +#define IDS_DEBUG_PORT CONFIG_IDS_DEBUG_PORT +#endif + +#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED (IS_ENABLED(CONFIG_IDSOPT_CAR_CORRUPTION_CHECK_ENABLED) ? TRUE : FALSE) +#define IDSOPT_DEBUG_CODE_ENABLED (IS_ENABLED(CONFIG_IDSOPT_DEBUG_CODE_ENABLED) ? TRUE : FALSE) +#define IDSOPT_C_OPTIMIZATION_DISABLED (IS_ENABLED(CONFIG_IDSOPT_C_OPTIMIZATION_DISABLED) ? TRUE : FALSE) +#define IDSOPT_IDT_EXCEPTION_TRAP (IS_ENABLED(CONFIG_IDSOPT_IDT_EXCEPTION_TRAP) ? TRUE : FALSE) + +#endif /* _OPTION_IDS_H_ */ diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc index 203efab..544a8c8 100644 --- a/src/vendorcode/amd/agesa/f10/Makefile.inc +++ b/src/vendorcode/amd/agesa/f10/Makefile.inc @@ -20,7 +20,7 @@ ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT = src/vendorcode/amd/agesa/f10 -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index e1bafbe..b00423d 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f12 -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 6a266ec..9a61432 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f14 -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 2a7acce..51087fb 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -20,7 +20,7 @@ ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT ?= $(PWD) -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..c2e1d2a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f15tn -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 0e68895..cca25f3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f16kb -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib

1 0

New patch to review for coreboot: 5822332 lenovo/x60: Remove duplicate console_init()
by Kyösti Mälkki 30 Mar '14

30 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5433 -gerrit commit 5822332b263571e1a81d4d349bc67a056148d7df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 31 00:09:23 2014 +0300 lenovo/x60: Remove duplicate console_init() For romstage, console_init() was called twice. The one in dock_connect() should have done only UART programming and not touch CBMEM console and/or USBDEBUG when those are enabled. Second case where dock_connect() is called is in SMI handler. If DEBUG_SMI is not enabled, console_init() does nothing in SMM. If DEBUG_SMI is enabled, console_init() is already called every time when enterining SMM. Change-Id: Ib3a842442cb7a5be9d6b71682cd6f368930af886 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x60/dock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 1b15a6c..1f85281 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -237,7 +237,6 @@ int dock_connect(void) dock_write_register(0x07, 0x03); dock_write_register(0x30, 0x01); - console_init(); return 0; }

1 0

Patch set updated for coreboot: 6c02b76 Kconfig: Unify IDS options for all six AGESA trees into a vendorcode menu
by Peter Stuge 30 Mar '14

30 Mar '14

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5161 -gerrit commit 6c02b76e7c7775ac3c750a1ded28a4faad1dd63e Author: Peter Stuge <peter(a)stuge.se> Date: Fri Feb 7 03:57:36 2014 +0100 Kconfig: Unify IDS options for all six AGESA trees into a vendorcode menu Change-Id: I5bea6d777581c0cae537cb8cfd196c3ac9fc1a37 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/cpu/amd/agesa/family10/Kconfig | 8 - src/cpu/amd/agesa/family15/Kconfig | 8 - src/mainboard/amd/dinar/OptionsIds.h | 64 ------- src/mainboard/amd/inagua/OptionsIds.h | 64 ------- src/mainboard/amd/olivehill/OptionsIds.h | 67 ------- src/mainboard/amd/parmer/OptionsIds.h | 67 ------- src/mainboard/amd/persimmon/OptionsIds.h | 64 ------- src/mainboard/amd/south_station/OptionsIds.h | 64 ------- src/mainboard/amd/thatcher/OptionsIds.h | 67 ------- src/mainboard/amd/torpedo/OptionsIds.h | 64 ------- src/mainboard/amd/union_station/OptionsIds.h | 64 ------- src/mainboard/asrock/e350m1/OptionsIds.h | 66 ------- src/mainboard/asrock/imb-a180/OptionsIds.h | 67 ------- src/mainboard/asus/f2a85-m/OptionsIds.h | 67 ------- src/mainboard/gizmosphere/gizmo/OptionsIds.h | 65 ------- src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 67 ------- src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h | 64 ------- src/mainboard/lippert/frontrunner-af/OptionsIds.h | 64 ------- src/mainboard/lippert/toucan-af/OptionsIds.h | 64 ------- src/mainboard/supermicro/h8qgi/OptionsIds.h | 66 ------- src/mainboard/supermicro/h8scm/OptionsIds.h | 67 ------- src/mainboard/tyan/s8226/OptionsIds.h | 67 ------- src/vendorcode/Kconfig | 1 + src/vendorcode/amd/Kconfig | 1 + src/vendorcode/amd/agesa/Kconfig | 203 ++++++++++++++++++++++ src/vendorcode/amd/agesa/Makefile.inc | 2 + src/vendorcode/amd/agesa/OptionsIds.h | 37 ++++ src/vendorcode/amd/agesa/f10/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f12/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f15/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 2 +- 33 files changed, 250 insertions(+), 1331 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 621ee58..ae5a09e 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -49,12 +49,4 @@ config HAVE_INIT_TIMER bool default y -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 02991a0..963ef42 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -70,12 +70,4 @@ config HAVE_INIT_TIMER bool default y -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h deleted file mode 100644 index a756942..0000000 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h deleted file mode 100644 index 4e86877..0000000 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h deleted file mode 100644 index 600753c..0000000 --- a/src/mainboard/asrock/e350m1/OptionsIds.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h deleted file mode 100644 index 0a1d328..0000000 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h deleted file mode 100644 index bf7eedc..0000000 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h deleted file mode 100755 index 3655b5e..0000000 --- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/lippert/toucan-af/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h deleted file mode 100644 index cdf1701..0000000 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/supermicro/h8scm/OptionsIds.h b/src/mainboard/supermicro/h8scm/OptionsIds.h deleted file mode 100644 index bf719bf..0000000 --- a/src/mainboard/supermicro/h8scm/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/tyan/s8226/OptionsIds.h b/src/mainboard/tyan/s8226/OptionsIds.h deleted file mode 100644 index ceb336f..0000000 --- a/src/mainboard/tyan/s8226/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/vendorcode/Kconfig b/src/vendorcode/Kconfig index a8cbe02..9b6e5d4 100644 --- a/src/vendorcode/Kconfig +++ b/src/vendorcode/Kconfig @@ -1,2 +1,3 @@ +source src/vendorcode/amd/Kconfig source src/vendorcode/google/Kconfig source src/vendorcode/intel/Kconfig diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig new file mode 100644 index 0000000..e59f40e --- /dev/null +++ b/src/vendorcode/amd/Kconfig @@ -0,0 +1 @@ +source src/vendorcode/amd/agesa/Kconfig diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..ddcc4e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,203 @@ +if CPU_AMD_AGESA +menu "AGESA" + +config VENDORCODE_AMD_AGESA_F10 + def_bool y if CPU_AMD_AGESA_FAMILY10 + +config VENDORCODE_AMD_AGESA_F12 + def_bool y if CPU_AMD_AGESA_FAMILY12 + +config VENDORCODE_AMD_AGESA_F14 + def_bool y if CPU_AMD_AGESA_FAMILY14 + +config VENDORCODE_AMD_AGESA_F15 + def_bool y if CPU_AMD_AGESA_FAMILY15 + +config VENDORCODE_AMD_AGESA_F15TN + def_bool y if CPU_AMD_AGESA_FAMILY15_TN + +config VENDORCODE_AMD_AGESA_F16KB + def_bool y if CPU_AMD_AGESA_FAMILY16_KB + +config VENDORCODE_AMD_AGESA_R12067 + def_bool y if VENDORCODE_AMD_AGESA_F10 + +config VENDORCODE_AMD_AGESA_R38300 + def_bool y if CPU_AMD_AGESA_FAMILY14 + select VENDORCODE_AMD_AGESA_R12067 + +config VENDORCODE_AMD_AGESA_R44324 + def_bool y if VENDORCODE_AMD_AGESA_F12 || VENDORCODE_AMD_AGESA_F15 + select VENDORCODE_AMD_AGESA_R38300 + +config VENDORCODE_AMD_AGESA_R63425 + def_bool y if VENDORCODE_AMD_AGESA_F15TN + select VENDORCODE_AMD_AGESA_R44324 + +config VENDORCODE_AMD_AGESA_R84150 + def_bool y if VENDORCODE_AMD_AGESA_F16KB + select VENDORCODE_AMD_AGESA_R63425 + + +config IDSOPT_IDS_ENABLED + bool "Integrated Debug Support" + default n + help + Integrated Debug Support Module is used to debug AGESA events. + +config IDSOPT_CONTROL_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + + Support *skip* hooks for IDS options. + +config IDSOPT_CONTROL_NV_TO_CMOS + def_bool n + depends on IDSOPT_IDS_ENABLED && VENDORCODE_AMD_AGESA_R44324 + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDS_OPT_CMOS_INDEX_PORT + hex "IDS NVRAM index I/O port" + default 0x70 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_DATA_PORT + hex "IDS NVRAM data I/O port" + default 0x71 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_REGION_START + hex "IDS NVRAM region start" + default 0x20 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_REGION_END + hex "IDS NVRAM region end" + default 0x7f + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDSOPT_TRACING_ENABLED + bool "Enable trace messages" + default y + depends on IDSOPT_IDS_ENABLED + help + This option enables trace message output by AGESA at runtime. + +config IDSOPT_CUSTOMIZE_TRACING_SERVICE + def_bool n + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_R63425 + help + This IDS option is dead code in the current coreboot AGESA sources. + + The option allows to create custom trace handlers which would + replace the AGESA-internal tracing support. + +choice + prompt "Output trace messages to" + default IDSOPT_TRACING_CONSOLE_SERIALPORT + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_R63425 + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "coreboot console" + depends on VENDORCODE_AMD_AGESA_F10 || VENDORCODE_AMD_AGESA_F15 + help + Output trace messages to the coreboot console. + +config IDSOPT_TRACING_CONSOLE_HDTOUT + bool "hardware debug tool" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a Hardware Debug Tool. + +config IDSOPT_TRACING_CONSOLE_SERIALPORT + bool "serial port" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a 16550-compatible UART. + +config IDSOPT_TRACING_CONSOLE_REDIRECT_IO + bool "I/O port" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a custom I/O port. + +endchoice + +config IDSOPT_SERIAL_PORT + hex "Serial port I/O port" + default 0x3f8 + depends on IDSOPT_TRACING_ENABLED && IDSOPT_TRACING_CONSOLE_SERIALPORT + +config IDSOPT_DEBUG_PRINT_IO_PORT + hex "I/O port" + default 0x80 + depends on IDSOPT_TRACING_ENABLED && IDSOPT_TRACING_CONSOLE_REDIRECT_IO + +config IDSOPT_C_OPTIMIZATION_DISABLED + def_bool n if IDSOPT_TRACING_ENABLED + def_bool y if !IDSOPT_TRACING_ENABLED + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_F14 + help + Disable printk(BIOS_DEBUG) for IDS_HDT_CONSOLE messages. + +config IDSOPT_PERF_ANALYSIS + def_bool n + depends on IDSOPT_IDS_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + + The option enables collection and analysis of performance timestamps. + +config IDSOPT_ERROR_TRAP_ENABLED + bool "Trap Error events with stop code display" + default n + depends on IDSOPT_IDS_ENABLED + help + This option makes IDS trap and stop execution on an AGESA Error event. + +config IDSOPT_ASSERT_ENABLED + bool "Trap ASSERT failures with stop code display" + default y + depends on IDSOPT_IDS_ENABLED + help + This option makes IDS trap and stop execution if an ASSERT() is false. + + ASSERT is used in AGESA code for testing for fatal errors that must + be resolved before production. This is used to do parameter checks, + bounds checking, range checks and 'sanity' checks. + +config IDS_DEBUG_PORT + hex "AGESA_TESTPOINT I/O port" + default 0x80 + depends on IDSOPT_IDS_ENABLED + help + This configures the AGESA_TESTPOINT I/O port, usually the POST port. + +config IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED + select IDSOPT_ERROR_TRAP_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDSOPT_DEBUG_CODE_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED && VENDORCODE_AMD_AGESA_R38300 + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDSOPT_IDT_EXCEPTION_TRAP + bool "Trap exceptions with a 'jmp $' infinite loop" + default n + depends on IDSOPT_IDS_ENABLED && EXPERT && VENDORCODE_AMD_AGESA_F15TN + help + This option adds a 'jmp $' into every exception handler. + + Technically this option is available already with F12 but in the + coreboot AGESA sources the option only does something for F15TN. + +endmenu +endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 99356a6..cff0453 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -1,3 +1,5 @@ +AGESA_INC = -Isrc/vendorcode/amd/agesa + subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14 diff --git a/src/vendorcode/amd/agesa/OptionsIds.h b/src/vendorcode/amd/agesa/OptionsIds.h new file mode 100644 index 0000000..d215cff --- /dev/null +++ b/src/vendorcode/amd/agesa/OptionsIds.h @@ -0,0 +1,37 @@ +/** + * Copyright (c) 2014 Peter Stuge <peter(a)stuge.se> + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +#define IDSOPT_IDS_ENABLED (IS_ENABLED(CONFIG_IDSOPT_IDS_ENABLED) ? TRUE : FALSE) +#define IDSOPT_ERROR_TRAP_ENABLED (IS_ENABLED(CONFIG_IDSOPT_ERROR_TRAP_ENABLED) ? TRUE : FALSE) +#define IDSOPT_CONTROL_ENABLED (IS_ENABLED(CONFIG_IDSOPT_CONTROL_ENABLED) ? TRUE : FALSE) + +#define IDSOPT_TRACING_ENABLED (IS_ENABLED(CONFIG_IDSOPT_TRACING_ENABLED) ? TRUE : FALSE) +#define IDSOPT_TRACING_CONSOLE_HDTOUT (IS_ENABLED(CONFIG_IDSOPT_TRACING_CONSOLE_HDTOUT) ? TRUE : FALSE) +#define IDSOPT_TRACING_CONSOLE_SERIALPORT (IS_ENABLED(CONFIG_IDSOPT_TRACING_CONSOLE_SERIALPORT) ? TRUE : FALSE) + +#if CONFIG_IDSOPT_SERIAL_PORT +#define IDSOPT_SERIAL_PORT CONFIG_IDSOPT_SERIAL_PORT +#endif + +#define IDSOPT_TRACING_CONSOLE_REDIRECT_TO (IS_ENABLED(CONFIG_IDSOPT_TRACING_CONSOLE_REDIRECT_TO) ? TRUE : FALSE) + +#if CONFIG_IDSOPT_DEBUG_PRINT_IO_PORT +#define IDSOPT_DEBUG_PRINT_IO_PORT CONFIG_IDSOPT_DEBUG_PRINT_IO_PORT +#endif + +#define IDSOPT_PERF_ANALYSIS (IS_ENABLED(CONFIG_IDSOPT_PERF_ANALYSIS) ? TRUE : FALSE) +#define IDSOPT_ASSERT_ENABLED (IS_ENABLED(CONFIG_IDSOPT_ASSERT_ENABLED) ? TRUE : FALSE) + +#if CONFIG_IDS_DEBUG_PORT +#define IDS_DEBUG_PORT CONFIG_IDS_DEBUG_PORT +#endif + +#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED (IS_ENABLED(CONFIG_IDSOPT_CAR_CORRUPTION_CHECK_ENABLED) ? TRUE : FALSE) +#define IDSOPT_DEBUG_CODE_ENABLED (IS_ENABLED(CONFIG_IDSOPT_DEBUG_CODE_ENABLED) ? TRUE : FALSE) +#define IDSOPT_C_OPTIMIZATION_DISABLED (IS_ENABLED(CONFIG_IDSOPT_C_OPTIMIZATION_DISABLED) ? TRUE : FALSE) +#define IDSOPT_IDT_EXCEPTION_TRAP (IS_ENABLED(CONFIG_IDSOPT_IDT_EXCEPTION_TRAP) ? TRUE : FALSE) + +#endif /* _OPTION_IDS_H_ */ diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc index 203efab..544a8c8 100644 --- a/src/vendorcode/amd/agesa/f10/Makefile.inc +++ b/src/vendorcode/amd/agesa/f10/Makefile.inc @@ -20,7 +20,7 @@ ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT = src/vendorcode/amd/agesa/f10 -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index e1bafbe..b00423d 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f12 -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 6a266ec..9a61432 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f14 -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 2a7acce..51087fb 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -20,7 +20,7 @@ ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT ?= $(PWD) -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..c2e1d2a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f15tn -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 0e68895..cca25f3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f16kb -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib

1 0

Patch set updated for coreboot: 4866a57 superio/fintek/f81865f: Avoid .c includes
by Edward O'Callaghan 30 Mar '14

30 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5416 -gerrit commit 4866a57812216ec53c410baff63bfda2f12863ee Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 20:28:03 2014 +1100 superio/fintek/f81865f: Avoid .c includes We should not be #include .c files, instead link early_serial into romstage and provide a prototype. Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/via/epia-m850/Makefile.inc | 21 ---------- src/mainboard/via/epia-m850/romstage.c | 3 +- src/superio/fintek/f81865f/Makefile.inc | 1 + src/superio/fintek/f81865f/chip.h | 2 +- src/superio/fintek/f81865f/early_serial.c | 48 +++++++++++++++++++++++ src/superio/fintek/f81865f/f81865f.h | 4 +- src/superio/fintek/f81865f/f81865f_early_serial.c | 47 ---------------------- 9 files changed, 56 insertions(+), 74 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 98c64ed..e082f60 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,7 +31,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 20c973c..5614f88 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,7 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc deleted file mode 100644 index 9c6d31f..0000000 --- a/src/mainboard/via/epia-m850/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see <http://www.gnu.org/licenses/>. -## - -#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c - diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 262bee7..22f5ed6 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -36,8 +36,7 @@ #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" -/* FIXME: This is the only .c include we couldn't get rid of */ -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include <superio/fintek/f81865f/f81865f.h> #define SERIAL_DEV PNP_DEV(0x4e, 0x10) diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index 1700f7c..8afb286 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/chip.h b/src/superio/fintek/f81865f/chip.h index fc17c0f..ae4da18 100644 --- a/src/superio/fintek/f81865f/chip.h +++ b/src/superio/fintek/f81865f/chip.h @@ -30,4 +30,4 @@ struct superio_fintek_f81865f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_FINTEK_F81865_CHIP_H */ diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c new file mode 100644 index 0000000..29b5f9d --- /dev/null +++ b/src/superio/fintek/f81865f/early_serial.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ + +#include <arch/io.h> +#include <device/pnp.h> +#include "f81865f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void f81865f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 0c36571..ccf41af 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -35,4 +35,6 @@ #define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F81865F_PME 0x0a /* Power Management Events (PME) */ -#endif +void f81865f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F81865_F81865_H */ diff --git a/src/superio/fintek/f81865f/f81865f_early_serial.c b/src/superio/fintek/f81865f/f81865f_early_serial.c deleted file mode 100644 index 2989b5f..0000000 --- a/src/superio/fintek/f81865f/f81865f_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ - -#include <arch/io.h> -#include "f81865f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f81865f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -}

1 0

Patch set updated for coreboot: 92c9c5f vendorcode/amd/agesa/fam15tn: Build as a static library
by Alexandru Gagniuc 30 Mar '14

30 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5430 -gerrit commit 92c9c5fa09a4025c2d5a371e93f94c8a34e71b95 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:15:18 2014 -0500 vendorcode/amd/agesa/fam15tn: Build as a static library Up until now, we were building AGESA by specifying each AGESA source file and adding it to the list of romstage and ramstage source files. As a result, we were compiling each AGESA source twice, despite the fact that it does not depend on the stage we're in. Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. We still keep the practice of specifying every single AGESA directory as an include dir and adding the AGESA CFLAGS to our global CFLAGS; this is needed due to the way AGESA builds. Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 436 --------------------------- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 437 ++++++++++++++++++++++++++++ 2 files changed, 437 insertions(+), 436 deletions(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..a5a7071 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -20,442 +20,6 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -AGESA_ROOT = ../../../../vendorcode/amd/agesa/f15tn - -agesa_lib_src = -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c -agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c -agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15BrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Dmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MmioMap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/TN/mmflowtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mndcttn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnflowtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnidendimmtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnmcttn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnottn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnphytn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnregtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mns3tn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mntn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FP2/mpStnfp2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FS1/mpStnfs1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpStn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpUtn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mptn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c - -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/MemLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/PciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchTaskLauncher.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitEnvDef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitResetDef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppHp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppPortInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c - - -romstage-y += $(agesa_lib_src) -ramstage-y += $(agesa_lib_src) - subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..00ace78 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -93,3 +93,440 @@ export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### + +classes-y += libagesa + +libagesa-y += Legacy/Proc/Dispatcher.c +libagesa-y += Legacy/Proc/agesaCallouts.c +libagesa-y += Legacy/Proc/hobTransfer.c +libagesa-y += Lib/amdlib.c +libagesa-y += Lib/helper.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnC6State.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnCpb.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnIoCstate.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnMsrTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnPciTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c +libagesa-y += Proc/CPU/Family/0x15/TN/F15TnUtilities.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c +libagesa-y += Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c +libagesa-y += Proc/CPU/Family/0x15/cpuCommonF15Utilities.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15BrandId.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15CacheDefaults.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Dmi.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15MmioMap.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15MsrTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15PciTables.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15PowerCheck.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15Utilities.c +libagesa-y += Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +libagesa-y += Proc/CPU/Feature/PreserveMailbox.c +libagesa-y += Proc/CPU/Feature/cpuC6State.c +libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Feature/cpuCacheInit.c +libagesa-y += Proc/CPU/Feature/cpuCoreLeveling.c +libagesa-y += Proc/CPU/Feature/cpuCpb.c +libagesa-y += Proc/CPU/Feature/cpuDmi.c +libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa-y += Proc/CPU/Feature/cpuFeatures.c +libagesa-y += Proc/CPU/Feature/cpuHtc.c +libagesa-y += Proc/CPU/Feature/cpuHwC1e.c +libagesa-y += Proc/CPU/Feature/cpuIoCstate.c +libagesa-y += Proc/CPU/Feature/cpuPsi.c +libagesa-y += Proc/CPU/Feature/cpuPstateGather.c +libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c +libagesa-y += Proc/CPU/Feature/cpuPstateTables.c +libagesa-y += Proc/CPU/Feature/cpuSlit.c +libagesa-y += Proc/CPU/Feature/cpuSrat.c +libagesa-y += Proc/CPU/Feature/cpuWhea.c +libagesa-y += Proc/CPU/S3.c +libagesa-y += Proc/CPU/Table.c +libagesa-y += Proc/CPU/cahalt.c +libagesa-y += Proc/CPU/cahaltasm.S +libagesa-y += Proc/CPU/cpuApicUtilities.c +libagesa-y += Proc/CPU/cpuBist.c +libagesa-y += Proc/CPU/cpuBrandId.c +libagesa-y += Proc/CPU/cpuEarlyInit.c +libagesa-y += Proc/CPU/cpuEventLog.c +libagesa-y += Proc/CPU/cpuFamilyTranslation.c +libagesa-y += Proc/CPU/cpuGeneralServices.c +libagesa-y += Proc/CPU/cpuInitEarlyTable.c +libagesa-y += Proc/CPU/cpuLateInit.c +libagesa-y += Proc/CPU/cpuMicrocodePatch.c +libagesa-y += Proc/CPU/cpuPostInit.c +libagesa-y += Proc/CPU/cpuPowerMgmt.c +libagesa-y += Proc/CPU/cpuPowerMgmtMultiSocket.c +libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa-y += Proc/CPU/cpuWarmReset.c +libagesa-y += Proc/CPU/heapManager.c +libagesa-y += Proc/Common/AmdInitEarly.c +libagesa-y += Proc/Common/AmdInitEnv.c +libagesa-y += Proc/Common/AmdInitLate.c +libagesa-y += Proc/Common/AmdInitMid.c +libagesa-y += Proc/Common/AmdInitPost.c +libagesa-y += Proc/Common/AmdInitReset.c +libagesa-y += Proc/Common/AmdInitResume.c +libagesa-y += Proc/Common/AmdLateRunApTask.c +libagesa-y += Proc/Common/AmdS3LateRestore.c +libagesa-y += Proc/Common/AmdS3Save.c +libagesa-y += Proc/Common/CommonInits.c +libagesa-y += Proc/Common/CommonReturns.c +libagesa-y += Proc/Common/CreateStruct.c +libagesa-y += Proc/Common/S3RestoreState.c +libagesa-y += Proc/Common/S3SaveState.c +libagesa-y += Proc/GNB/Common/GnbLibFeatures.c +libagesa-y += Proc/GNB/GnbInitAtEarly.c +libagesa-y += Proc/GNB/GnbInitAtEnv.c +libagesa-y += Proc/GNB/GnbInitAtLate.c +libagesa-y += Proc/GNB/GnbInitAtMid.c +libagesa-y += Proc/GNB/GnbInitAtPost.c +libagesa-y += Proc/GNB/GnbInitAtReset.c +libagesa-y += Proc/GNB/GnbInitAtS3Save.c +libagesa-y += Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLib.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +libagesa-y += Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +libagesa-y += Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieLibTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c +libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +libagesa-y += Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c +libagesa-y += Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +libagesa-y += Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c +libagesa-y += Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +libagesa-y += Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c +libagesa-y += Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +libagesa-y += Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +libagesa-y += Proc/GNB/Modules/GnbSview/GnbSview.c +libagesa-y += Proc/GNB/Modules/GnbTable/GnbTable.c +libagesa-y += Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c +libagesa-y += Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c +libagesa-y += Proc/HT/htFeat.c +libagesa-y += Proc/HT/htInterface.c +libagesa-y += Proc/HT/htInterfaceCoherent.c +libagesa-y += Proc/HT/htInterfaceGeneral.c +libagesa-y += Proc/HT/htInterfaceNonCoherent.c +libagesa-y += Proc/HT/htMain.c +libagesa-y += Proc/HT/htNb.c +libagesa-y += Proc/HT/htNotify.c +libagesa-y += Proc/IDS/Debug/IdsDebug.c +libagesa-y += Proc/IDS/Debug/IdsDebugPrint.c +libagesa-y += Proc/IDS/Debug/IdsDpSerial.c +libagesa-y += Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c +libagesa-y += Proc/IDS/Library/IdsLib.c +libagesa-y += Proc/Mem/Ardk/ma.c +libagesa-y += Proc/Mem/Feat/CHINTLV/mfchi.c +libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c +libagesa-y += Proc/Mem/Feat/ECC/mfecc.c +libagesa-y += Proc/Mem/Feat/ECC/mfemp.c +libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa-y += Proc/Mem/Feat/INTLVRN/mfintlvrn.c +libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa-y += Proc/Mem/Feat/S3/mfs3.c +libagesa-y += Proc/Mem/Feat/TABLE/mftds.c +libagesa-y += Proc/Mem/Main/TN/mmflowtn.c +libagesa-y += Proc/Mem/Main/mdef.c +libagesa-y += Proc/Mem/Main/merrhdl.c +libagesa-y += Proc/Mem/Main/minit.c +libagesa-y += Proc/Mem/Main/mm.c +libagesa-y += Proc/Mem/Main/mmConditionalPso.c +libagesa-y += Proc/Mem/Main/mmEcc.c +libagesa-y += Proc/Mem/Main/mmExcludeDimm.c +libagesa-y += Proc/Mem/Main/mmLvDdr3.c +libagesa-y += Proc/Mem/Main/mmMemClr.c +libagesa-y += Proc/Mem/Main/mmMemRestore.c +libagesa-y += Proc/Mem/Main/mmNodeInterleave.c +libagesa-y += Proc/Mem/Main/mmOnlineSpare.c +libagesa-y += Proc/Mem/Main/mmParallelTraining.c +libagesa-y += Proc/Mem/Main/mmStandardTraining.c +libagesa-y += Proc/Mem/Main/mmUmaAlloc.c +libagesa-y += Proc/Mem/Main/mmflow.c +libagesa-y += Proc/Mem/Main/mu.c +libagesa-y += Proc/Mem/Main/muc.c +libagesa-y += Proc/Mem/NB/TN/mndcttn.c +libagesa-y += Proc/Mem/NB/TN/mnflowtn.c +libagesa-y += Proc/Mem/NB/TN/mnidendimmtn.c +libagesa-y += Proc/Mem/NB/TN/mnmcttn.c +libagesa-y += Proc/Mem/NB/TN/mnottn.c +libagesa-y += Proc/Mem/NB/TN/mnphytn.c +libagesa-y += Proc/Mem/NB/TN/mnregtn.c +libagesa-y += Proc/Mem/NB/TN/mns3tn.c +libagesa-y += Proc/Mem/NB/TN/mntn.c +libagesa-y += Proc/Mem/NB/mn.c +libagesa-y += Proc/Mem/NB/mnS3.c +libagesa-y += Proc/Mem/NB/mndct.c +libagesa-y += Proc/Mem/NB/mnfeat.c +libagesa-y += Proc/Mem/NB/mnflow.c +libagesa-y += Proc/Mem/NB/mnmct.c +libagesa-y += Proc/Mem/NB/mnphy.c +libagesa-y += Proc/Mem/NB/mnreg.c +libagesa-y += Proc/Mem/NB/mntrain3.c +libagesa-y += Proc/Mem/Ps/TN/FM2/mpUtnfm2.c +libagesa-y += Proc/Mem/Ps/TN/FP2/mpStnfp2.c +libagesa-y += Proc/Mem/Ps/TN/FS1/mpStnfs1.c +libagesa-y += Proc/Mem/Ps/TN/mpStn3.c +libagesa-y += Proc/Mem/Ps/TN/mpUtn3.c +libagesa-y += Proc/Mem/Ps/TN/mptn3.c +libagesa-y += Proc/Mem/Ps/mp.c +libagesa-y += Proc/Mem/Ps/mpmaxfreq.c +libagesa-y += Proc/Mem/Ps/mpmr0.c +libagesa-y += Proc/Mem/Ps/mpodtpat.c +libagesa-y += Proc/Mem/Ps/mprtt.c +libagesa-y += Proc/Mem/Ps/mpsao.c +libagesa-y += Proc/Mem/Tech/DDR3/mt3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c +libagesa-y += Proc/Mem/Tech/mt.c +libagesa-y += Proc/Mem/Tech/mthdi.c +libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c +libagesa-y += Proc/Mem/Tech/mttdimbt.c +libagesa-y += Proc/Mem/Tech/mttecc.c +libagesa-y += Proc/Mem/Tech/mtthrc.c +libagesa-y += Proc/Mem/Tech/mtthrcSeedTrain.c +libagesa-y += Proc/Mem/Tech/mttml.c +libagesa-y += Proc/Mem/Tech/mttoptsrc.c +libagesa-y += Proc/Mem/Tech/mttsrc.c +libagesa-y += Proc/Fch/Azalia/AzaliaEnv.c +libagesa-y += Proc/Fch/Azalia/AzaliaLate.c +libagesa-y += Proc/Fch/Azalia/AzaliaMid.c +libagesa-y += Proc/Fch/Azalia/AzaliaReset.c +libagesa-y += Proc/Fch/Common/AcpiLib.c +libagesa-y += Proc/Fch/Common/FchCommon.c +libagesa-y += Proc/Fch/Common/FchLib.c +libagesa-y += Proc/Fch/Common/FchPeLib.c +libagesa-y += Proc/Fch/Common/MemLib.c +libagesa-y += Proc/Fch/Common/PciLib.c +libagesa-y += Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c +libagesa-y += Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c +libagesa-y += Proc/Fch/Gec/GecEnv.c +libagesa-y += Proc/Fch/Gec/GecLate.c +libagesa-y += Proc/Fch/Gec/GecMid.c +libagesa-y += Proc/Fch/Gec/GecReset.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiEnv.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiLate.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiMid.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiReset.c +libagesa-y += Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c +libagesa-y += Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c +libagesa-y += Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c +libagesa-y += Proc/Fch/Hwm/HwmEnv.c +libagesa-y += Proc/Fch/Hwm/HwmLate.c +libagesa-y += Proc/Fch/Hwm/HwmMid.c +libagesa-y += Proc/Fch/Hwm/HwmReset.c +libagesa-y += Proc/Fch/Ide/IdeEnv.c +libagesa-y += Proc/Fch/Ide/IdeLate.c +libagesa-y += Proc/Fch/Ide/IdeMid.c +libagesa-y += Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c +libagesa-y += Proc/Fch/Imc/FchEcEnv.c +libagesa-y += Proc/Fch/Imc/FchEcLate.c +libagesa-y += Proc/Fch/Imc/FchEcMid.c +libagesa-y += Proc/Fch/Imc/FchEcReset.c +libagesa-y += Proc/Fch/Imc/ImcEnv.c +libagesa-y += Proc/Fch/Imc/ImcLate.c +libagesa-y += Proc/Fch/Imc/ImcLib.c +libagesa-y += Proc/Fch/Imc/ImcMid.c +libagesa-y += Proc/Fch/Imc/ImcReset.c +libagesa-y += Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c +libagesa-y += Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c +libagesa-y += Proc/Fch/Interface/FchInitEnv.c +libagesa-y += Proc/Fch/Interface/FchInitLate.c +libagesa-y += Proc/Fch/Interface/FchInitMid.c +libagesa-y += Proc/Fch/Interface/FchInitReset.c +libagesa-y += Proc/Fch/Interface/FchInitS3.c +libagesa-y += Proc/Fch/Interface/FchTaskLauncher.c +libagesa-y += Proc/Fch/Interface/InitEnvDef.c +libagesa-y += Proc/Fch/Interface/InitResetDef.c +libagesa-y += Proc/Fch/Ir/IrEnv.c +libagesa-y += Proc/Fch/Ir/IrLate.c +libagesa-y += Proc/Fch/Ir/IrMid.c +libagesa-y += Proc/Fch/Pcib/PcibEnv.c +libagesa-y += Proc/Fch/Pcib/PcibLate.c +libagesa-y += Proc/Fch/Pcib/PcibMid.c +libagesa-y += Proc/Fch/Pcib/PcibReset.c +libagesa-y += Proc/Fch/Pcie/AbEnv.c +libagesa-y += Proc/Fch/Pcie/AbLate.c +libagesa-y += Proc/Fch/Pcie/AbMid.c +libagesa-y += Proc/Fch/Pcie/AbReset.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c +libagesa-y += Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c +libagesa-y += Proc/Fch/Pcie/GppEnv.c +libagesa-y += Proc/Fch/Pcie/GppHp.c +libagesa-y += Proc/Fch/Pcie/GppLate.c +libagesa-y += Proc/Fch/Pcie/GppLib.c +libagesa-y += Proc/Fch/Pcie/GppMid.c +libagesa-y += Proc/Fch/Pcie/GppPortInit.c +libagesa-y += Proc/Fch/Pcie/GppReset.c +libagesa-y += Proc/Fch/Pcie/PcieEnv.c +libagesa-y += Proc/Fch/Pcie/PcieLate.c +libagesa-y += Proc/Fch/Pcie/PcieMid.c +libagesa-y += Proc/Fch/Pcie/PcieReset.c +libagesa-y += Proc/Fch/Sata/AhciEnv.c +libagesa-y += Proc/Fch/Sata/AhciLate.c +libagesa-y += Proc/Fch/Sata/AhciLib.c +libagesa-y += Proc/Fch/Sata/AhciMid.c +libagesa-y += Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c +libagesa-y += Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c +libagesa-y += Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c +libagesa-y += Proc/Fch/Sata/Ide2AhciEnv.c +libagesa-y += Proc/Fch/Sata/Ide2AhciLate.c +libagesa-y += Proc/Fch/Sata/Ide2AhciLib.c +libagesa-y += Proc/Fch/Sata/Ide2AhciMid.c +libagesa-y += Proc/Fch/Sata/RaidEnv.c +libagesa-y += Proc/Fch/Sata/RaidLate.c +libagesa-y += Proc/Fch/Sata/RaidLib.c +libagesa-y += Proc/Fch/Sata/RaidMid.c +libagesa-y += Proc/Fch/Sata/SataEnv.c +libagesa-y += Proc/Fch/Sata/SataEnvLib.c +libagesa-y += Proc/Fch/Sata/SataIdeEnv.c +libagesa-y += Proc/Fch/Sata/SataIdeLate.c +libagesa-y += Proc/Fch/Sata/SataIdeLib.c +libagesa-y += Proc/Fch/Sata/SataIdeMid.c +libagesa-y += Proc/Fch/Sata/SataLate.c +libagesa-y += Proc/Fch/Sata/SataLib.c +libagesa-y += Proc/Fch/Sata/SataMid.c +libagesa-y += Proc/Fch/Sata/SataReset.c +libagesa-y += Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c +libagesa-y += Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c +libagesa-y += Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c +libagesa-y += Proc/Fch/Sd/SdEnv.c +libagesa-y += Proc/Fch/Sd/SdLate.c +libagesa-y += Proc/Fch/Sd/SdMid.c +libagesa-y += Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c +libagesa-y += Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +libagesa-y += Proc/Fch/Spi/LpcEnv.c +libagesa-y += Proc/Fch/Spi/LpcLate.c +libagesa-y += Proc/Fch/Spi/LpcMid.c +libagesa-y += Proc/Fch/Spi/LpcReset.c +libagesa-y += Proc/Fch/Spi/SpiEnv.c +libagesa-y += Proc/Fch/Spi/SpiLate.c +libagesa-y += Proc/Fch/Spi/SpiMid.c +libagesa-y += Proc/Fch/Spi/SpiReset.c +libagesa-y += Proc/Fch/Usb/EhciEnv.c +libagesa-y += Proc/Fch/Usb/EhciLate.c +libagesa-y += Proc/Fch/Usb/EhciMid.c +libagesa-y += Proc/Fch/Usb/EhciReset.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c +libagesa-y += Proc/Fch/Usb/OhciEnv.c +libagesa-y += Proc/Fch/Usb/OhciLate.c +libagesa-y += Proc/Fch/Usb/OhciMid.c +libagesa-y += Proc/Fch/Usb/OhciReset.c +libagesa-y += Proc/Fch/Usb/UsbEnv.c +libagesa-y += Proc/Fch/Usb/UsbLate.c +libagesa-y += Proc/Fch/Usb/UsbMid.c +libagesa-y += Proc/Fch/Usb/UsbReset.c +libagesa-y += Proc/Fch/Usb/XhciEnv.c +libagesa-y += Proc/Fch/Usb/XhciLate.c +libagesa-y += Proc/Fch/Usb/XhciMid.c +libagesa-y += Proc/Fch/Usb/XhciReset.c + +$(obj)/libagesa.fam15tn.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ + +romstage-libs += $(obj)/libagesa.fam15tn.a +ramstage-libs += $(obj)/libagesa.fam15tn.a

1 0

Patch set updated for coreboot: ac767f1 x86/Makefile: Allow addition of link libraries for rom/ramstage
by Alexandru Gagniuc 30 Mar '14

30 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5425 -gerrit commit ac767f133d9c2c3a66898153f7b9681447011c48 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:01:11 2014 -0500 x86/Makefile: Allow addition of link libraries for rom/ramstage This is useful, for example, when using stage-independent code, as it allows us to compile that code only once. It's also useful for vendor code which needs wonky compiler definitions and include paths which we'd rather not include in the other files. Subsequent patches will make use of this when lib-izing AGESA. Change-Id: Ifb0c5d353bf09d23864270b9eefb6b75fd86e6cb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index acb4e98..107abb4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -207,6 +207,8 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ################################################################################ # Build the coreboot_ram (stage 2) +ramstage-libs := + ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) $(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE))) @@ -227,12 +229,12 @@ endif endif -$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group + $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ @@ -404,24 +406,26 @@ endif ################################################################################ # Build the romstage -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld +romstage-libs := + +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ else true; fi -$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld +$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions

1 0

New patch to review for coreboot: c81dbd1 git-ignore site-local
by Patrick Georgi 30 Mar '14

30 Mar '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5432 -gerrit commit c81dbd139b50f5ad9c446b630cc1a5501b05f982 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 30 18:55:05 2014 +0200 git-ignore site-local It's _local_ Change-Id: I5624e240ffe486763b25b14b218e69362c488f50 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index b37c195..fd22c61 100644 --- a/.gitignore +++ b/.gitignore @@ -30,6 +30,7 @@ util/crossgcc/Python-*/ util/crossgcc/tarballs/ util/crossgcc/w32api-*/ util/crossgcc/xgcc/ +site-local *.\# *.bin

1 0

New patch to review for coreboot: 8213784 AMD CAR: use define
by Patrick Georgi 30 Mar '14

30 Mar '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5431 -gerrit commit 821378454497be5d23cded00d73bee62b524bea6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 30 18:53:12 2014 +0200 AMD CAR: use define Change-Id: I0b40c9811115b204f1cae70546d236049c1b3d30 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/car/cache_as_ram.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 8f0abce..dd02f6c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -160,7 +160,7 @@ CAR_FAM10_out: #else #error "bad MMCONF_BUS_NUMBER value" #endif - movl $(0xc0010058), %ecx + movl $MSR_MCFG_BASE, %ecx wrmsr #endif

1 0

New patch to review for coreboot: 2b245c7 vendorcode/amd/agesa/fam15tn: Build as a static library
by Alexandru Gagniuc 30 Mar '14

30 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5430 -gerrit commit 2b245c734ae4ea542ab06393b4c167d589e06a2d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:15:18 2014 -0500 vendorcode/amd/agesa/fam15tn: Build as a static library FORTEST. NOTFORMERGEYET. Up until now, we were building AGESA by specifying each AGESA source file and adding it to the list of romstage and ramstage source files. As a result, we were compiling each AGESA source twice, despite the fact that it does not depend on the stage we're in. To sweeten the deal, we also remove the practice of specifying every single AGESA directory as an include dir. We are also able to avoid polluting coreboot CFLAGS with the AGESA CFLAGS, thus making AGESA an almost fully self-contained module. Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/amd/agesa/family15tn/Makefile.inc | 436 -------------------------- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 463 +++++++++++++++++++++++++++- 2 files changed, 459 insertions(+), 440 deletions(-) diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..a5a7071 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -20,442 +20,6 @@ ramstage-y += chip_name.c ramstage-y += model_15_init.c -AGESA_ROOT = ../../../../vendorcode/amd/agesa/f15tn - -agesa_lib_src = -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c -agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c -agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15BrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Dmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MmioMap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/TN/mmflowtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mndcttn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnflowtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnidendimmtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnmcttn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnottn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnphytn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnregtn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mns3tn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/TN/mntn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FP2/mpStnfp2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FS1/mpStnfs1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpStn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpUtn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mptn3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c - -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/MemLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Common/PciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Gec/GecReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ide/IdeMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Imc/ImcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/FchTaskLauncher.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitEnvDef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Interface/InitResetDef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Ir/IrMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/AbReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppHp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppPortInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/GppReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/AhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Sd/SdMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/LpcReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Spi/SpiReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/EhciReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c - - -romstage-y += $(agesa_lib_src) -ramstage-y += $(agesa_lib_src) - subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..21a79a6 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -30,9 +30,9 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f15tn -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) -AGESA_INC += -I$(AGESA_ROOT) -AGESA_INC += -I$(AGESA_ROOT)/Include +AGESA_PUB_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_PUB_INC += -I$(AGESA_ROOT) +AGESA_PUB_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy AGESA_INC += -I$(AGESA_ROOT)/Proc/Common @@ -91,5 +91,460 @@ AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-st export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) -CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) +CC := $(CC) $(AGESA_PUB_INC) +#CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) ####################################################################### + +libagesa_srcs = +libagesa_srcs += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c +libagesa_srcs += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +libagesa_srcs += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c +libagesa_srcs += $(AGESA_ROOT)/Lib/amdlib.c +libagesa_srcs += $(AGESA_ROOT)/Lib/helper.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnC6State.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnCpb.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPciTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/F15TnUtilities.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuCommonF15Utilities.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15BrandId.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Dmi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MmioMap.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15MsrTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PciTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15PowerCheck.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15Utilities.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHtc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPsi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/S3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/Table.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cahalt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuBist.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/CPU/heapManager.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/CommonInits.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/CommonReturns.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/CreateStruct.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Common/S3SaveState.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/GnbInitAtS3Save.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSview/GnbSview.c +libagesa_srcs += $(AGESA_ROOT)/Proc/GNB/Modules/GnbTable/GnbTable.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbFam15Mod1x.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/Fam15Mod1x/htNbUtilitiesFam15Mod1x.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htFeat.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htInterface.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htMain.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htNb.c +libagesa_srcs += $(AGESA_ROOT)/Proc/HT/htNotify.c +libagesa_srcs += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c +libagesa_srcs += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebugPrint.c +libagesa_srcs += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDpSerial.c +libagesa_srcs += $(AGESA_ROOT)/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/IDS/Library/IdsLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/TN/mmflowtn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/minit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mm.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/mu.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Main/muc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mndcttn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnflowtn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnidendimmtn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnmcttn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnottn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnphytn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mnregtn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mns3tn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/TN/mntn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mn.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FM2/mpUtnfm2.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FP2/mpStnfp2.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/TN/FS1/mpStnfs1.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpStn3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mpUtn3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/TN/mptn3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c + +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Azalia/AzaliaReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Common/AcpiLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Common/FchCommon.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Common/MemLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Common/PciLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Gec/GecEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Gec/GecLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Gec/GecMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Gec/GecReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/HwAcpi/HwAcpiReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Hwm/HwmReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Ide/IdeEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Ide/IdeLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Ide/IdeMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/FchEcReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/ImcEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/ImcLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/ImcMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Imc/ImcReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/FchInitS3.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/FchTaskLauncher.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/InitEnvDef.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Interface/InitResetDef.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Ir/IrEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Ir/IrLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Ir/IrMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcib/PcibReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/AbEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/AbLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/AbMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/AbReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppHp.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppPortInit.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/GppReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Pcie/PcieReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/AhciEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/AhciLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/AhciMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/Ide2AhciMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/RaidEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/RaidLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/RaidMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataEnvLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataIdeMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataLib.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sata/SataReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdResetService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sd/Family/Hudson2/Hudson2SdService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sd/SdEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sd/SdLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Sd/SdMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/LpcEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/LpcLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/LpcMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/LpcReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/SpiEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/SpiLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/SpiMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Spi/SpiReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/EhciEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/EhciLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/EhciMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/EhciReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciLateService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2EhciMidService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciLateService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2OhciMidService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciEnvService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciLateService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciMidService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/Family/Hudson2/Hudson2XhciResetService.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/OhciEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/OhciLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/OhciMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/OhciReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/UsbEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/UsbLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/UsbMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/UsbReset.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/XhciEnv.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/XhciLate.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/XhciMid.c +libagesa_srcs += $(AGESA_ROOT)/Proc/Fch/Usb/XhciReset.c + +libagesa_objs = $(libagesa_srcs:$(src)/%.c=$(obj)/%.agesa_lib.o) +libagesa_objs += $(libagesa_srcs:$(src)/%.S=$(obj)/%.agesa_lib.o) + +$(obj)/libagesa.a: $(libagesa_objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ + +# We could make a classes-y construct and have the buildsystem take care of this +# rule for us, but then we'd have to export $(AGESA_CFLAGS) and $(AGESA_INC) +# globally, and we're trying to avoid that. The only include paths which should +# be visible from outside are the $(AGESA_PUB_INC) paths. +$(obj)/%.agesa_lib.o: $(src)/%.c + @printf " CC-AGESA $(subst $(obj)/,,$(@))\n" + mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(AGESA_CFLAGS) $(AGESA_INC) $(AGESA_PUB_INC) $^ -c -o $@ + +$(obj)/%.agesa_lib.o: $(src)/%.S + @printf " AS-AGESA $(subst $(obj)/,,$(@))\n" + mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(AGESA_CFLAGS) $(AGESA_INC) $(AGESA_PUB_INC) $^ -c -o $@ + +romstage-libs += $(obj)/libagesa.a +ramstage-libs += $(obj)/libagesa.a

1 0

Patch set updated for coreboot: 221e2a2 jetway/nf81-t56n-lf: Sanitize #includes
by Edward O'Callaghan 30 Mar '14

30 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5414 -gerrit commit 221e2a236dcafa9f6b806a14b2807bbffaa1ebe3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 17:54:26 2014 +1100 jetway/nf81-t56n-lf: Sanitize #includes NOTFORMERGE Following the same reasoning as commit <HASH HERE> (pavilion) hp/pavilion_m6_1035dx: Sanitize #includes Clean up the #include directives in this northbridge code. Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 6 +-- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 7 +--- .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 6 +-- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 22 ++++------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 4 +- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 44 +++++++++------------- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 12 +++--- src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 5 +-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 15 ++++---- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 11 +++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 35 +++++++++-------- 12 files changed, 81 insertions(+), 97 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 700da08..9174183 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -18,10 +18,10 @@ */ #include "agesawrapper.h" -#include "amdlib.h" +#include <Lib/amdlib.h> #include "BiosCallOuts.h" -#include "heapManager.h" -#include "SB800.h" +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +#include <vendorcode/amd/cimx/sb800/SB800.h> #include <northbridge/amd/agesa/family14/dimmSpd.h> STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 3cd69f1..d7413cd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -17,14 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" #include "BiosCallOuts.h" +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> + #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE /*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index ec8a6e3..47ed1a5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -20,10 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 43ee9c9..e7772aa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam14.h> +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 0572335..e6633f3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -22,25 +22,19 @@ *----------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE UNASSIGNED_FILE_FILECODE diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index ba47c53..6544d25 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -26,8 +26,8 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index c6383a2..c6594d3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -33,7 +33,21 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "Filecode.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> + +/* Include the files that instantiate the configuration definitions. */ +#include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> +#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> +/* AGESA nonesense: the next two headers depend on heapManager.h */ +#include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h> +/* These tables are optional and may be used to adjust memory timing settings */ +#include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h> +#include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -224,8 +238,6 @@ * Uncomment and specify the value for the configuration options * needed by the system. */ -#include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = @@ -244,20 +256,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } }; -/* Include the files that instantiate the configuration definitions. */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - /***************************************************************************** * Define the RELEASE VERSION string * @@ -314,8 +312,9 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED #define DFLT_VRM_SLEW_RATE (5000) -// Instantiate all solution relevant data. -#include "PlatformInstall.h" +/* AGESA nonsense: this header depends on the definitions above */ +/* Instantiate all solution relevant data. */ +#include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h> /*---------------------------------------------------------------------------------------- * CUSTOMER OVERIDES MEMORY TABLE @@ -390,11 +389,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -/* - * These tables are optional and may be used to adjust memory timing settings - */ -#include "mm.h" -#include "mn.h" //DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = @@ -454,5 +448,3 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL // /* platform code to read an SPD... */ // return Status; //} - - diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 258d895..1491f29 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif +#include <string.h> + +#include <southbridge/amd/cimx/sb800/sb_cimx.h> /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index b9577cf..b77c375 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -18,12 +18,11 @@ */ +#include <arch/pirq_routing.h> #include <console/console.h> -#include <device/pci.h> +#include <cpu/amd/amdfam14.h> #include <string.h> #include <stdint.h> -#include <arch/pirq_routing.h> -#include <cpu/amd/amdfam14.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 44f9c48..d5f2d03 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -17,18 +17,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/sb800/sb800.h> -#include <arch/acpi.h> -#include "BiosCallOuts.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/amd/mtrr.h> -#include "SBPLATFORM.h" void set_pcie_reset(void); void set_pcie_dereset(void); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 6b8aaa6..d7fe6a0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -18,14 +18,15 @@ */ -#include <console/console.h> +#include <arch/io.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/amd/amdfam14.h> #include <device/pci.h> -#include <arch/io.h> -#include <string.h> #include <stdint.h> -#include <cpu/amd/amdfam14.h> -#include <SBPLATFORM.h> +#include <string.h> + +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> extern u8 bus_sb800[6]; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 1214921..846d5c7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -18,30 +18,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> + +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <string.h> + #include <console/loglevel.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" +#include <cpu/x86/cache.h> +#include <cpu/amd/mtrr.h> +#include <sb_cimx.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include "superio/fintek/f71869ad/f71869ad.h" -#include "cpu/x86/lapic.h" + +/* FIXME: should not include .c files */ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);

1 0

← Newer
1
2
3
4
5
6
7
...
59
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2014