coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: c005e7e superio/fintek/f71863fg: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5435 -gerrit commit c005e7e76c270da4b4e4b7e39ac63e721bb262b5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:08:35 2014 +1100 superio/fintek/f71863fg: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I863c16634873224c17e43100271e9b91419724d0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/pa78vm5/romstage.c | 2 +- src/superio/fintek/f71863fg/Makefile.inc | 2 +- src/superio/fintek/f71863fg/chip.h | 2 +- src/superio/fintek/f71863fg/early_serial.c | 3 ++- src/superio/fintek/f71863fg/f71863fg.h | 4 +++- 5 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index b8fa48e..c082a67 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -42,7 +42,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/fintek/f71863fg/early_serial.c" +#include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/superio/fintek/f71863fg/Makefile.inc b/src/superio/fintek/f71863fg/Makefile.inc index 0deb77e..85ec530 100644 --- a/src/superio/fintek/f71863fg/Makefile.inc +++ b/src/superio/fintek/f71863fg/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.c - diff --git a/src/superio/fintek/f71863fg/chip.h b/src/superio/fintek/f71863fg/chip.h index 9084824..4d2652e 100644 --- a/src/superio/fintek/f71863fg/chip.h +++ b/src/superio/fintek/f71863fg/chip.h @@ -29,4 +29,4 @@ struct superio_fintek_f71863fg_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_FINTEK_F71863FG_CHIP_H */ diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c index 5d1cfb7..251f298 100644 --- a/src/superio/fintek/f71863fg/early_serial.c +++ b/src/superio/fintek/f71863fg/early_serial.c @@ -21,6 +21,7 @@ /* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> #include "f71863fg.h" static void pnp_enter_conf_state(device_t dev) @@ -36,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71863fg_enable_serial(device_t dev, u16 iobase) +void f71863fg_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index 5f11879..127a120 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -33,4 +33,6 @@ #define F71863FG_SPI 0x08 /* SPI */ #define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ -#endif +void f71863fg_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71863FG_F71863FG_H */

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Patch set updated for coreboot: 48471ec superio/fintek/f71805f: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5434 -gerrit commit 48471ece71ec7fcb5139743de231c38bdf250630 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:01:16 2014 +1100 superio/fintek/f71805f: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/superio/fintek/f71805f/Makefile.inc | 2 +- src/superio/fintek/f71805f/early_serial.c | 3 ++- src/superio/fintek/f71805f/f71805f.h | 4 +++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 928fcef..37c3ab4 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -31,7 +31,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/fintek/f71805f/early_serial.c" +#include <superio/fintek/f71805f/f71805f.h> #include <lib.h> #include <spd.h> diff --git a/src/superio/fintek/f71805f/Makefile.inc b/src/superio/fintek/f71805f/Makefile.inc index 9ed5e6f..22c01e0 100644 --- a/src/superio/fintek/f71805f/Makefile.inc +++ b/src/superio/fintek/f71805f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c - diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c index 827f870..b823a43 100644 --- a/src/superio/fintek/f71805f/early_serial.c +++ b/src/superio/fintek/f71805f/early_serial.c @@ -21,6 +21,7 @@ /* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> #include "f71805f.h" static void pnp_enter_conf_state(device_t dev) @@ -36,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71805f_enable_serial(device_t dev, u16 iobase) +void f71805f_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71805f/f71805f.h b/src/superio/fintek/f71805f/f71805f.h index 0670128..6aae58f 100644 --- a/src/superio/fintek/f71805f/f71805f.h +++ b/src/superio/fintek/f71805f/f71805f.h @@ -38,4 +38,6 @@ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F71805F_PME 0x0a /* Power Management Events (PME) */ -#endif +void f71805f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71805F_F71805F_H */

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Patch set updated for coreboot: 3131502 superio/fintek/f71859: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5417 -gerrit commit 313150290c5b70162b9de5f9d767f6f1859143f0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 20:42:58 2014 +1100 superio/fintek/f71859: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- src/superio/fintek/f71859/Makefile.inc | 2 +- src/superio/fintek/f71859/early_serial.c | 3 ++- src/superio/fintek/f71859/f71859.h | 4 +++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index e5e2c57..299ba61 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/fintek/f71859/early_serial.c" +#include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/superio/fintek/f71859/Makefile.inc b/src/superio/fintek/f71859/Makefile.inc index bf150da..8858811 100644 --- a/src/superio/fintek/f71859/Makefile.inc +++ b/src/superio/fintek/f71859/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71859) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c - diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c index 4401714..cb0d3de 100644 --- a/src/superio/fintek/f71859/early_serial.c +++ b/src/superio/fintek/f71859/early_serial.c @@ -21,6 +21,7 @@ /* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> #include "f71859.h" static void pnp_enter_conf_state(device_t dev) @@ -36,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71859_enable_serial(device_t dev, u16 iobase) +void f71859_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index 2c89d19..580fa34 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -24,4 +24,6 @@ /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ -#endif +void f71859_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71859_F71859_H */

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Patch set updated for coreboot: 3eaeae1 superio/serverengines/pilot: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5439 -gerrit commit 3eaeae1ffcc44ff6444f0125d6f2da970c527b19 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:53:32 2014 +1100 superio/serverengines/pilot: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/hp/dl145_g3/Kconfig | 1 + src/mainboard/hp/dl145_g3/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/superio/Makefile.inc | 2 +- src/superio/serverengines/Makefile.inc | 20 ++++++++++++++++++++ src/superio/serverengines/pilot/Makefile.inc | 22 ++++++++++++++++++++++ src/superio/serverengines/pilot/early_init.c | 6 +++++- src/superio/serverengines/pilot/early_serial.c | 3 ++- src/superio/serverengines/pilot/pilot.h | 6 +++++- 10 files changed, 59 insertions(+), 8 deletions(-) diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index be3f009..3ff5f0b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..9deaaba 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,8 +40,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index b72b8dd..b53809a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..474190b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index e34fa89..2ca57cb 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -23,7 +23,7 @@ subdirs-y += ite subdirs-y += nsc subdirs-y += nuvoton subdirs-y += renesas -#subdirs-y += serverengines +subdirs-y += serverengines subdirs-y += smsc subdirs-y += via subdirs-y += winbond diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc new file mode 100644 index 0000000..4ba0a24 --- /dev/null +++ b/src/superio/serverengines/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc new file mode 100644 index 0000000..b07438f --- /dev/null +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 1993c9e..f227939 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -23,11 +23,15 @@ #define BLUBB_DEV PNP_DEV(port, 0x04) +#include <arch/io.h> +#include <device/pnp.h> +#include "pilot.h" + /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -static void pilot_early_init(device_t dev) +void pilot_early_init(device_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 4112901..1b2e38e 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,6 +22,7 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ #include <arch/io.h> +#include <device/pnp.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ @@ -38,7 +39,7 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Serial config is a fairly standard procedure. */ -static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a5bddd3..84d1989 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -30,4 +30,8 @@ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ -#endif +void pilot_early_init(device_t dev); + +void pilot_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */

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Patch set updated for coreboot: 6b8afa8 superio/serverengines/pilot: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5439 -gerrit commit 6b8afa803d140a75083b26ca9abcd7ff12fd2f17 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:53:32 2014 +1100 superio/serverengines/pilot: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/hp/dl145_g3/Kconfig | 1 + src/mainboard/hp/dl145_g3/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/superio/serverengines/Makefile.inc | 20 ++++++++++++++++++++ src/superio/serverengines/pilot/Makefile.inc | 22 ++++++++++++++++++++++ src/superio/serverengines/pilot/early_init.c | 6 +++++- src/superio/serverengines/pilot/early_serial.c | 3 ++- src/superio/serverengines/pilot/pilot.h | 6 +++++- 9 files changed, 58 insertions(+), 7 deletions(-) diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index be3f009..3ff5f0b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..9deaaba 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,8 +40,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index b72b8dd..b53809a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..474190b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc new file mode 100644 index 0000000..4ba0a24 --- /dev/null +++ b/src/superio/serverengines/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc new file mode 100644 index 0000000..b07438f --- /dev/null +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 1993c9e..f227939 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -23,11 +23,15 @@ #define BLUBB_DEV PNP_DEV(port, 0x04) +#include <arch/io.h> +#include <device/pnp.h> +#include "pilot.h" + /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -static void pilot_early_init(device_t dev) +void pilot_early_init(device_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 4112901..1b2e38e 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,6 +22,7 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ #include <arch/io.h> +#include <device/pnp.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ @@ -38,7 +39,7 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Serial config is a fairly standard procedure. */ -static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a5bddd3..84d1989 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -30,4 +30,8 @@ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ -#endif +void pilot_early_init(device_t dev); + +void pilot_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */

1 0

Patch set updated for coreboot: c2a1e5a superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit c2a1e5a86cc49695c7f4045a29659216f57b76ec Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 3 +-- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 5 +++-- src/superio/intel/i3100/i3100.h | 6 +++++- 6 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..08b1a18 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..a7376b7 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -38,14 +39,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..a0a9d15 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); + +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */

1 0

New patch to review for coreboot: c517f46 superio/serverengines/pilot: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5439 -gerrit commit c517f46524e7c2125d8933b6c156c918a7c60876 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:53:32 2014 +1100 superio/serverengines/pilot: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/hp/dl145_g3/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/superio/serverengines/Makefile.inc | 20 ++++++++++++++++++++ src/superio/serverengines/pilot/Makefile.inc | 22 ++++++++++++++++++++++ src/superio/serverengines/pilot/early_init.c | 6 +++++- src/superio/serverengines/pilot/early_serial.c | 3 ++- src/superio/serverengines/pilot/pilot.h | 6 +++++- 7 files changed, 56 insertions(+), 7 deletions(-) diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..9deaaba 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,8 +40,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..474190b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc new file mode 100644 index 0000000..4ba0a24 --- /dev/null +++ b/src/superio/serverengines/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc new file mode 100644 index 0000000..b07438f --- /dev/null +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 1993c9e..f227939 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -23,11 +23,15 @@ #define BLUBB_DEV PNP_DEV(port, 0x04) +#include <arch/io.h> +#include <device/pnp.h> +#include "pilot.h" + /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -static void pilot_early_init(device_t dev) +void pilot_early_init(device_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 4112901..1b2e38e 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,6 +22,7 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ #include <arch/io.h> +#include <device/pnp.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ @@ -38,7 +39,7 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Serial config is a fairly standard procedure. */ -static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a5bddd3..84d1989 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -30,4 +30,8 @@ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ -#endif +void pilot_early_init(device_t dev); + +void pilot_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */

1 0

Patch set updated for coreboot: 1a5ffd1 superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 1a5ffd12b328ee1063d50a36db56dfa3ea1fd176 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 3 +-- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 5 +++-- src/superio/intel/i3100/i3100.h | 6 +++++- 6 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..08b1a18 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..a7376b7 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -38,14 +39,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..a0a9d15 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); + +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */

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New patch to review for coreboot: 8e40a8f superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 8e40a8f1cc51ebea8bdcf0ce91c35224de2ad8fb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 2 +- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 3 ++- src/superio/intel/i3100/i3100.h | 4 +++- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..7bf3a3d 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -33,7 +33,7 @@ #include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..ab0ad15 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -45,7 +46,7 @@ static void i3100_configure_uart_clk(device_t dev, u8 predivide) pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..2b9302c 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,6 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */

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Patch set updated for coreboot: ebce465 superio/fintek/f71889: [4/5] Avoid .c includes
by Edward O'Callaghan 31 Mar '14

31 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5437 -gerrit commit ebce4655743cb2dec8de4da0adb729963ee4d3a8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:14:14 2014 +1100 superio/fintek/f71889: [4/5] Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71889/Makefile.inc | 2 +- src/superio/fintek/f71889/chip.h | 2 +- src/superio/fintek/f71889/early_serial.c | 4 ++-- src/superio/fintek/f71889/f71889.h | 4 +++- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/superio/fintek/f71889/Makefile.inc b/src/superio/fintek/f71889/Makefile.inc index ef14b74..9864140 100644 --- a/src/superio/fintek/f71889/Makefile.inc +++ b/src/superio/fintek/f71889/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71889) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c - diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h index 2895efc..50312ad 100644 --- a/src/superio/fintek/f71889/chip.h +++ b/src/superio/fintek/f71889/chip.h @@ -29,4 +29,4 @@ struct superio_fintek_f71889_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_FINTEK_F71889_CHIP_H */ diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c index 9623cbd..5e11474 100644 --- a/src/superio/fintek/f71889/early_serial.c +++ b/src/superio/fintek/f71889/early_serial.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> #include <arch/io.h> +#include <device/pnp.h> #include "f71889.h" static void pnp_enter_conf_state(device_t dev) @@ -35,7 +35,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71889_enable_serial(device_t dev, u16 iobase) +void f71889_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 1b6a369..6dc43b3 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -34,4 +34,6 @@ #define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ #define F71889_VREF 0x0b /* Vref */ -#endif +void f71889_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71889_F71889_H */

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coreboot-gerrit March 2014