coreboot-gerrit March 2014

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Patch set updated for coreboot: 62988e2 superio/ite/it8712f: NOTFORMERGE - Avoid .c includes
by Edward O'Callaghan 29 Mar '14

29 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5418 -gerrit commit 62988e2d09fe82506b48c538a8146757e604550a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 23:23:15 2014 +1100 superio/ite/it8712f: NOTFORMERGE - Avoid .c includes We should not be #include c files all around the shop.. Link early_serial into romstage and provide a prototype. This highlights the trainwreck we have with the current Super I/O infrastructure. We really should not have early_serial.c containing what it does here and it should not find its way into ramstage in this way! Change-Id: I0026eb87749e46bcafd224cf5b61526045c38898 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 35 ------------------------- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/superio/ite/it8712f/Makefile.inc | 3 ++- src/superio/ite/it8712f/early_serial.c | 28 +++++++++++--------- src/superio/ite/it8712f/it8712f.h | 12 ++++++++- 20 files changed, 45 insertions(+), 65 deletions(-) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 74b6d1b..5b839ae 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -35,7 +35,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2971072..5c00d51 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -30,7 +30,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..4b89122 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -33,7 +33,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..e9cf3f1 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -34,7 +34,7 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/amd/agesa/s3_resume.h" #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..22f10b9 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..23a62d3 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 18c6f18..bb890d5 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 660ab0f..be2a615 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 1ebdedd..252863f 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -30,7 +30,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "drivers/pc80/udelay_io.c" #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <lib.h> void main(unsigned long bist) diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 95ea27d..5a6d743 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -35,7 +35,7 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" /* Bit0 enables Spread Spectrum. */ diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6edcf37..00935a3 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -35,7 +35,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 68dcfc0..b8ca5c1 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -35,7 +35,7 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 59bd618..8ac5601 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -35,7 +35,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6d36524..fcbf6de 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -43,7 +43,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..cd9cfe2 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -55,11 +55,6 @@ #define TV_MODE_09 0x09 /* SCART-RGB */ #define TV_MODE_NO 0xff /* No TV Support */ -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 - /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -69,7 +64,6 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ -#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ #define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); @@ -82,35 +76,6 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); -} - -static void it8712f_exit_conf(void) -{ - /* Exit the configuration state (MB PnP mode). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - /* set thermal config */ static void set_thermal_config(void) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 42c2599..f757a3c 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -37,7 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 22a1212..1797bb8 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -37,7 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..6fbbfd1 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..6f0e1ff 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,13 +19,9 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8712f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -35,16 +31,23 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ -static void it8712f_sio_write(u8 ldn, u8 index, u8 value) +/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the + LDN the register belongs to, before you can access the register. */ +void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) { - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); + outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); } -static void it8712f_enter_conf(void) +void it8712f_enter_conf(void) { + /* Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x2e. */ + /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ + /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ u16 port = 0x2e; /* TODO: Don't hardcode! */ outb(0x87, port); @@ -53,8 +56,9 @@ static void it8712f_enter_conf(void) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void it8712f_exit_conf(void) +void it8712f_exit_conf(void) { + /* Exit the configuration state (MB PnP mode). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..56560da 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -39,4 +39,14 @@ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value); +void it8712f_enter_conf(void); +void it8712f_exit_conf(void); + +#endif /* SUPERIO_ITE_IT8712F_IT8712F_H */

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Patch set updated for coreboot: 087785d superio/fintek/f81865f: Avoid .c includes
by Edward O'Callaghan 29 Mar '14

29 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5416 -gerrit commit 087785d99f085c0965bf98adde8060128829edf8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 20:28:03 2014 +1100 superio/fintek/f81865f: Avoid .c includes We should not be #include c files all around the shop.. Link early_serial into romstage and provide a prototype. Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/via/epia-m850/Makefile.inc | 21 ---------- src/mainboard/via/epia-m850/romstage.c | 3 +- src/superio/fintek/f81865f/Makefile.inc | 1 + src/superio/fintek/f81865f/chip.h | 2 +- src/superio/fintek/f81865f/early_serial.c | 48 +++++++++++++++++++++++ src/superio/fintek/f81865f/f81865f.h | 4 +- src/superio/fintek/f81865f/f81865f_early_serial.c | 47 ---------------------- 9 files changed, 56 insertions(+), 74 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 98c64ed..21f3566 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,7 +31,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/fintek/f81865f/f81865f.h" #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 20c973c..d85cec7 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,7 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/fintek/f81865f/f81865f.h" #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc deleted file mode 100644 index 9c6d31f..0000000 --- a/src/mainboard/via/epia-m850/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see <http://www.gnu.org/licenses/>. -## - -#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c - diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 262bee7..80027f6 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -36,8 +36,7 @@ #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" -/* FIXME: This is the only .c include we couldn't get rid of */ -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/fintek/f81865f/f81865f.h" #define SERIAL_DEV PNP_DEV(0x4e, 0x10) diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index 1700f7c..8afb286 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/chip.h b/src/superio/fintek/f81865f/chip.h index fc17c0f..ae4da18 100644 --- a/src/superio/fintek/f81865f/chip.h +++ b/src/superio/fintek/f81865f/chip.h @@ -30,4 +30,4 @@ struct superio_fintek_f81865f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_FINTEK_F81865_CHIP_H */ diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c new file mode 100644 index 0000000..29b5f9d --- /dev/null +++ b/src/superio/fintek/f81865f/early_serial.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ + +#include <arch/io.h> +#include <device/pnp.h> +#include "f81865f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void f81865f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 0c36571..ccf41af 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -35,4 +35,6 @@ #define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F81865F_PME 0x0a /* Power Management Events (PME) */ -#endif +void f81865f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F81865_F81865_H */ diff --git a/src/superio/fintek/f81865f/f81865f_early_serial.c b/src/superio/fintek/f81865f/f81865f_early_serial.c deleted file mode 100644 index 2989b5f..0000000 --- a/src/superio/fintek/f81865f/f81865f_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ - -#include <arch/io.h> -#include "f81865f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f81865f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -}

1 0

Patch set updated for coreboot: f462895 superio/fintek/f71859: Avoid .c includes
by Edward O'Callaghan 29 Mar '14

29 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5417 -gerrit commit f462895f39d084bfdc7207b732508d0739b61268 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 20:42:58 2014 +1100 superio/fintek/f71859: Avoid .c includes We should not be #include c files all around the shop.. Link early_serial into romstage and provide a prototype. Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +- src/superio/fintek/f71859/Makefile.inc | 2 +- src/superio/fintek/f71859/early_serial.c | 3 ++- src/superio/fintek/f71859/f71859.h | 4 +++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index e5e2c57..8134053 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/fintek/f71859/early_serial.c" +#include "superio/fintek/f71859/f71859.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/superio/fintek/f71859/Makefile.inc b/src/superio/fintek/f71859/Makefile.inc index bf150da..8858811 100644 --- a/src/superio/fintek/f71859/Makefile.inc +++ b/src/superio/fintek/f71859/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71859) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c - diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c index 4401714..cb0d3de 100644 --- a/src/superio/fintek/f71859/early_serial.c +++ b/src/superio/fintek/f71859/early_serial.c @@ -21,6 +21,7 @@ /* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> #include "f71859.h" static void pnp_enter_conf_state(device_t dev) @@ -36,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71859_enable_serial(device_t dev, u16 iobase) +void f71859_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index 2c89d19..580fa34 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -24,4 +24,6 @@ /* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ -#endif +void f71859_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71859_F71859_H */

1 0

Patch set updated for coreboot: 08ad5d5 x86: use car_(get|set)_var accessors for apic timer
by Kyösti Mälkki 29 Mar '14

29 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5411 -gerrit commit 08ad5d5ba3b3b4145e5e4b959eef209c43e361b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 28 08:40:59 2014 -0500 x86: use car_(get|set)_var accessors for apic timer The timer_fsb variable was not correctly being accessed in the presence of cache-as-ram. The cache-as-ram backing store could be torn down but then udelay() could be called causing hangs from accessing variables that have unknown values. Instead change the timer_fsb variable to g_timer_fsb and obtain the value through a local access method that does the correct things to obtain the correct value. Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/lapic/apic_timer.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 868fb92..a113143 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -34,14 +34,17 @@ */ #if CONFIG_UDELAY_LAPIC_FIXED_FSB -static const u32 timer_fsb = CONFIG_UDELAY_LAPIC_FIXED_FSB; +static inline u32 get_timer_fsb(void) +{ + return CONFIG_UDELAY_LAPIC_FIXED_FSB; +} static int set_timer_fsb(void) { return 0; } #else -static u32 timer_fsb CAR_GLOBAL = 0; +static u32 g_timer_fsb CAR_GLOBAL; static int set_timer_fsb(void) { @@ -56,25 +59,30 @@ static int set_timer_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + car_set_var(g_timer_fsb, core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + car_set_var(g_timer_fsb, core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - timer_fsb = 100; + car_set_var(g_timer_fsb, 100); break; default: - timer_fsb = 200; + car_set_var(g_timer_fsb, 200); break; } return 0; } + +static inline u32 get_timer_fsb(void) +{ + return car_get_var(g_timer_fsb); +} #endif void init_timer(void) @@ -94,15 +102,18 @@ void init_timer(void) void udelay(u32 usecs) { - u32 start, value, ticks; + u32 start, value, ticks, timer_fsb; if (!thread_yield_microseconds(usecs)) return; + timer_fsb = get_timer_fsb(); if (!timer_fsb || (lapic_read(LAPIC_LVTT) & (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) + (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) { init_timer(); + timer_fsb = get_timer_fsb(); + } /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */ ticks = usecs * timer_fsb; @@ -125,9 +136,11 @@ void timer_monotonic_get(struct mono_time *mt) { uint32_t current_tick; uint32_t usecs_elapsed; + uint32_t timer_fsb; if (!mono_counter.initialized) { init_timer(); + timer_fsb = get_timer_fsb(); /* An FSB frequency of 200Mhz provides a 20 second polling * interval between timer_monotonic_get() calls before wrap * around occurs. */ @@ -139,6 +152,7 @@ void timer_monotonic_get(struct mono_time *mt) mono_counter.initialized = 1; } + timer_fsb = get_timer_fsb(); current_tick = lapic_read(LAPIC_TMCCT); /* Note that the APIC timer counts down. */ usecs_elapsed = (mono_counter.last_value - current_tick) / timer_fsb;

1 0

Patch set updated for coreboot: 1d6092e Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
by Kyösti Mälkki 29 Mar '14

29 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5419 -gerrit commit 1d6092e2a45791f6817219fc6629d17e755017a4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 28 23:46:45 2014 +0200 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE Use of CAR_GLOBAL is not safe after CAR is torn down, unless the board properly implements EARLY_CBMEM_INIT. Flag vulnerable boards that only do cbmem_recovery() in romstage on S3 resume and implementation with Intel FSP that invalidates cache before we have a chance to copy the contents. Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 9 +++++++++ src/arch/x86/boot/Makefile.inc | 2 +- src/arch/x86/boot/cbmem.c | 4 +++- src/cpu/x86/Makefile.inc | 2 +- src/lib/Makefile.inc | 2 +- src/mainboard/asus/dsbf/Kconfig | 1 + src/mainboard/intel/cougar_canyon2/Kconfig | 1 + src/mainboard/iwave/iWRainbowG6/Kconfig | 1 + src/mainboard/supermicro/x7db8/Kconfig | 1 + 9 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 531a8c8..fe7dc9b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -170,6 +170,15 @@ config EARLY_CBMEM_INIT some, for instance, execution timestamps. It needs support in romstage.c and should be enabled by the board's Kconfig. +config BROKEN_CAR_MIGRATE + bool + default y if !EARLY_CBMEM_INIT && HAVE_ACPI_RESUME + default n + help + Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and + manage CAR migration on S3 resume path only. Couple boards use + CAR_GLOBAL and never do CAR migration. + config DYNAMIC_CBMEM bool "The CBMEM space is dynamically grown." default n diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 79c6417..928fc03 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,5 +1,5 @@ romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c ramstage-y += boot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index c2d9a2e..8b2b6da 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -49,13 +49,15 @@ void set_top_of_ram(uint64_t ramtop) backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } +#endif /* !__PRE_RAM__ */ +#if CONFIG_BROKEN_CAR_MIGRATE || !defined(__PRE_RAM__) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } -#endif /* !__PRE_RAM__ */ +#endif #else diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index c0b50c5..514d96c 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,5 +1,5 @@ romstage-$(CONFIG_EARLY_CBMEM_INIT) += car.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += car.c +romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += car.c subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 93babd3..f8cf3b1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -103,7 +103,7 @@ romstage-y += dynamic_cbmem.c else ramstage-y += cbmem.c romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c endif # CONFIG_DYNAMIC_CBMEM ramstage-y += cbmem_info.c diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 5d67014..99aa56d 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 select DRIVERS_GENERIC_IOAPIC + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 569888d..61f1c6d 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_SIO1007 select ENABLE_VMX select EARLY_CBMEM_INIT + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 75d4bb9..c6c15d5 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select GFXUMA + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 03f8ceb..7becacb 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 select DRIVERS_GENERIC_IOAPIC + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: 845951a hp/pavilion_m6_1035dx: Sanitize #includes
by Alexandru Gagniuc 29 Mar '14

29 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5412 -gerrit commit 845951a6642b5cbd94e07def6363bd84793aeeb5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Mar 28 14:48:13 2014 -0500 hp/pavilion_m6_1035dx: Sanitize #includes There were a number of things wrong with the includes. First, The includes did not use paths to AGESA files, thus relying on the compiler include paths to find the correct file. This made it unclear where the file included was located, and whether it was local, under vendorcode, or under a different directory. Instead, use full paths for each non-local include. Second, the local includes were mixed with the rest, making it unclear which file is local and which one is not. Keep the local includes at the top. This also prevents us from polluting the namespace of local headers, with library definitions, and allows us to catch if we missed an otherwise needed external header. Thirdly, alphabetize the order of includes where possible. Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 12 ++++------ .../hp/pavilion_m6_1035dx/PlatformGnbPcie.c | 7 ++---- .../hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h | 5 ++-- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 13 ++++------ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 28 ++++++++-------------- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 5 ++-- src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 11 ++++----- src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 5 ++-- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 14 +++++------ src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 14 +++++------ src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 28 +++++++++++----------- 12 files changed, 61 insertions(+), 84 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 110c2c8..34e688d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -18,16 +18,12 @@ */ #include "agesawrapper.h" -#include "amdlib.h" #include "BiosCallOuts.h" -#include "Ids.h" #include "OptionsIds.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#include "imc.h" -#endif + +#include <cbfs.h> +#include <southbridge/amd/agesa/hudson/imc.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c index 784f6d9..de046ac 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c @@ -17,12 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h index b3c69cf..add9008 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h @@ -20,9 +20,8 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index d93fecc..1c1d94b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -17,19 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <string.h> +#include "agesawrapper.h" + #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/ioapic.h> +#include <cpu/amd/amdfam15.h> +#include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/msr.h> -#include "agesawrapper.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/amdfam15.h> - -#include "agesawrapper.h" +#include <string.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 827ce6d..a89ddbe 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -22,30 +22,22 @@ *---------------------------------------------------------------------------------------- */ -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <cbmem.h> + #include <arch/acpi.h> #include <arch/io.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> -#include "hudson.h" +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h index 5007510..29eedaf 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h @@ -26,8 +26,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 1a23190..d5dfe30 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -33,9 +33,8 @@ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ -#include "AGESA.h" -//#include "CommonReturns.h" -#include "Filecode.h" +#include <vendorcode/amd/agesa/f15tn/AGESA.h> + #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE /* Select the cpu family. */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c index bf76fe2..79a5380 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c @@ -17,17 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" + #include <console/console.h> +#include <cpu/amd/amdfam15.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam14.h> -#include "agesawrapper.h" -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#include "imc.h" -#endif +#include <string.h> +#include <southbridge/amd/agesa/hudson/imc.h> /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index d5339ad..dfa5d8f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -17,12 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam15.h> #include <console/console.h> -#include <device/pci.h> #include <string.h> #include <stdint.h> -#include <arch/pirq_routing.h> -#include <cpu/amd/amdfam15.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index f41d010..5ac478f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -17,17 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "agesawrapper.h" +#include "BiosCallOuts.h" + +#include <arch/acpi.h> +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/agesa/s3_resume.h> #include <device/device.h> #include <device/pci.h> -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include "BiosCallOuts.h" -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/acpi.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" /************************************************* * enable the dedicated function in parmer board. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index d106697..8d42fff 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> +#include <arch/cpu.h> #include <arch/io.h> -#include <string.h> -#include <stdint.h> +#include <arch/smp/mpspec.h> +#include <console/console.h> #include <cpu/amd/amdfam15.h> -#include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */ +#include <device/pci.h> +#include <stdint.h> +#include <string.h> +#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 202442c..dd19679 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -17,25 +17,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> +#include "agesawrapper.h" + +#include <arch/cpu.h> #include <arch/io.h> #include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> +#include <cbmem.h> #include <console/console.h> -#include <console/loglevel.h> -#include "agesawrapper.h" -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <string.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" -#include "cbmem.h" + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void disable_cache_as_ram(void);

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New patch to review for coreboot: 2d3edb7 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
by Kyösti Mälkki 29 Mar '14

29 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5419 -gerrit commit 2d3edb7834ac5652f1849333b607af4f9f4a3fb7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 28 23:46:45 2014 +0200 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE Use of CAR_GLOBAL is not safe after CAR is torn down, unless the board properly implements EARLY_CBMEM_INIT. Flag vulnerable boards that only do cbmem_recovery() in romstage on S3 resume and implementation with Intel FSP that invalidates cache before we have a chance to copy the contents. Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 9 +++++++++ src/arch/x86/boot/Makefile.inc | 2 +- src/arch/x86/boot/cbmem.c | 4 +++- src/cpu/x86/Makefile.inc | 2 +- src/lib/Makefile.inc | 2 +- src/mainboard/asus/dsbf/Kconfig | 1 + src/mainboard/intel/cougar_canyon2/Kconfig | 1 + src/mainboard/iwave/iWRainbowG6/Kconfig | 1 + src/mainboard/supermicro/x7db8/Kconfig | 1 + 9 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 531a8c8..06d16aa 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -170,6 +170,15 @@ config EARLY_CBMEM_INIT some, for instance, execution timestamps. It needs support in romstage.c and should be enabled by the board's Kconfig. +config BROKEN_CAR_MIGRATE + bool + default y if !EARLY_CBMEM_INIT && ACPI_HAVE_RESUME + default n + help + Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and + manage CAR migration on S3 resume path only. Couple boards use + CAR_GLOBAL and never do CAR migration. + config DYNAMIC_CBMEM bool "The CBMEM space is dynamically grown." default n diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 79c6417..928fc03 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,5 +1,5 @@ romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c ramstage-y += boot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index c2d9a2e..8b2b6da 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -49,13 +49,15 @@ void set_top_of_ram(uint64_t ramtop) backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } +#endif /* !__PRE_RAM__ */ +#if CONFIG_BROKEN_CAR_MIGRATE || !defined(__PRE_RAM__) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } -#endif /* !__PRE_RAM__ */ +#endif #else diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index c0b50c5..514d96c 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,5 +1,5 @@ romstage-$(CONFIG_EARLY_CBMEM_INIT) += car.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += car.c +romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += car.c subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 93babd3..f8cf3b1 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -103,7 +103,7 @@ romstage-y += dynamic_cbmem.c else ramstage-y += cbmem.c romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +romstage-$(CONFIG_BROKEN_CAR_MIGRATE) += cbmem.c endif # CONFIG_DYNAMIC_CBMEM ramstage-y += cbmem_info.c diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 5d67014..99aa56d 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 select DRIVERS_GENERIC_IOAPIC + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 569888d..61f1c6d 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_SIO1007 select ENABLE_VMX select EARLY_CBMEM_INIT + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 75d4bb9..c6c15d5 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select GFXUMA + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 03f8ceb..7becacb 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select DRIVERS_I2C_W83793 select DRIVERS_GENERIC_IOAPIC + select BROKEN_CAR_MIGRATE config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: 80f5b1f x86: use car_(get|set)_var accessors for apic timer
by Kyösti Mälkki 29 Mar '14

29 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5411 -gerrit commit 80f5b1fe4ea9d3f4dcbaef6b84994e4cef2576c2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 28 08:40:59 2014 -0500 x86: use car_(get|set)_var accessors for apic timer The timer_fsb variable was not correctly being accessed in the presence of cache-as-ram. The cache-as-ram backing store could be torn down but then udelay() could be called causing hangs from accessing variables that have unknown values. Instead change the timer_fsb variable to g_timer_fsb and obtain the value through a local access method that does the correct things to obtain the correct value. Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/lapic/apic_timer.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 868fb92..a113143 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -34,14 +34,17 @@ */ #if CONFIG_UDELAY_LAPIC_FIXED_FSB -static const u32 timer_fsb = CONFIG_UDELAY_LAPIC_FIXED_FSB; +static inline u32 get_timer_fsb(void) +{ + return CONFIG_UDELAY_LAPIC_FIXED_FSB; +} static int set_timer_fsb(void) { return 0; } #else -static u32 timer_fsb CAR_GLOBAL = 0; +static u32 g_timer_fsb CAR_GLOBAL; static int set_timer_fsb(void) { @@ -56,25 +59,30 @@ static int set_timer_fsb(void) switch (c.x86_model) { case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ - timer_fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + car_set_var(g_timer_fsb, core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ - timer_fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; + car_set_var(g_timer_fsb, core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]); break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ - timer_fsb = 100; + car_set_var(g_timer_fsb, 100); break; default: - timer_fsb = 200; + car_set_var(g_timer_fsb, 200); break; } return 0; } + +static inline u32 get_timer_fsb(void) +{ + return car_get_var(g_timer_fsb); +} #endif void init_timer(void) @@ -94,15 +102,18 @@ void init_timer(void) void udelay(u32 usecs) { - u32 start, value, ticks; + u32 start, value, ticks, timer_fsb; if (!thread_yield_microseconds(usecs)) return; + timer_fsb = get_timer_fsb(); if (!timer_fsb || (lapic_read(LAPIC_LVTT) & (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != - (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) + (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) { init_timer(); + timer_fsb = get_timer_fsb(); + } /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */ ticks = usecs * timer_fsb; @@ -125,9 +136,11 @@ void timer_monotonic_get(struct mono_time *mt) { uint32_t current_tick; uint32_t usecs_elapsed; + uint32_t timer_fsb; if (!mono_counter.initialized) { init_timer(); + timer_fsb = get_timer_fsb(); /* An FSB frequency of 200Mhz provides a 20 second polling * interval between timer_monotonic_get() calls before wrap * around occurs. */ @@ -139,6 +152,7 @@ void timer_monotonic_get(struct mono_time *mt) mono_counter.initialized = 1; } + timer_fsb = get_timer_fsb(); current_tick = lapic_read(LAPIC_TMCCT); /* Note that the APIC timer counts down. */ usecs_elapsed = (mono_counter.last_value - current_tick) / timer_fsb;

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Patch set updated for coreboot: e8a89ea superio/ite/it8712f: Let the linker do its job.
by Edward O'Callaghan 29 Mar '14

29 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5418 -gerrit commit e8a89eade43ae4b000af961f00c9a1033733095a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 23:23:15 2014 +1100 superio/ite/it8712f: Let the linker do its job. We should not be #include c files all around the shop.. Link early_serial into romstage and provide a prototype. On aside, this Super I/O could do with a rewrite basically but that is for another commit. Change-Id: I0026eb87749e46bcafd224cf5b61526045c38898 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/superio/ite/it8712f/Makefile.inc | 2 +- src/superio/ite/it8712f/early_serial.c | 7 ++++--- src/superio/ite/it8712f/it8712f.h | 7 ++++++- 19 files changed, 27 insertions(+), 21 deletions(-) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 74b6d1b..5b839ae 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -35,7 +35,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2971072..5c00d51 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -30,7 +30,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..4b89122 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -33,7 +33,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..e9cf3f1 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -34,7 +34,7 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/amd/agesa/s3_resume.h" #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..22f10b9 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..23a62d3 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 18c6f18..bb890d5 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 660ab0f..be2a615 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 1ebdedd..252863f 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -30,7 +30,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "drivers/pc80/udelay_io.c" #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <lib.h> void main(unsigned long bist) diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 95ea27d..5a6d743 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -35,7 +35,7 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" /* Bit0 enables Spread Spectrum. */ diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6edcf37..00935a3 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -35,7 +35,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 68dcfc0..b8ca5c1 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -35,7 +35,7 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 59bd618..8ac5601 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -35,7 +35,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h" /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6d36524..fcbf6de 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -43,7 +43,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 42c2599..f757a3c 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -37,7 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 22a1212..1797bb8 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -37,7 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..ce75645 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..df22caf 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ @@ -35,7 +36,7 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ -static void it8712f_sio_write(u8 ldn, u8 index, u8 value) +void it8712f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -43,7 +44,7 @@ static void it8712f_sio_write(u8 ldn, u8 index, u8 value) outb(value, SIO_DATA); } -static void it8712f_enter_conf(void) +void it8712f_enter_conf(void) { u16 port = 0x2e; /* TODO: Don't hardcode! */ @@ -53,7 +54,7 @@ static void it8712f_enter_conf(void) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void it8712f_exit_conf(void) +void it8712f_exit_conf(void) { it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..4dc3909 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -39,4 +39,9 @@ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +void it8712f_sio_write(u8 ldn, u8 index, u8 value); +void it8712f_enter_conf(void); +void it8712f_exit_conf(void); + +#endif /* SUPERIO_ITE_IT8712F_IT8712F_H */

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New patch to review for coreboot: 0f74396 superio/ite/it8712f: Let the linker do its job.
by Edward O'Callaghan 29 Mar '14

29 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5418 -gerrit commit 0f74396b8b9e44485a108efba3a0600fcbe884e5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 29 23:23:15 2014 +1100 superio/ite/it8712f: Let the linker do its job. We should not be #include c files all around the shop.. Link early_serial into romstage and provide a prototype. Change-Id: I0026eb87749e46bcafd224cf5b61526045c38898 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/superio/ite/it8712f/Makefile.inc | 2 +- src/superio/ite/it8712f/early_serial.c | 1 + src/superio/ite/it8712f/it8712f.h | 3 ++- 6 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..e9cf3f1 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -34,7 +34,7 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/amd/agesa/s3_resume.h" #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..22f10b9 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..23a62d3 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..ce75645 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..46e02f0 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..f051bcf 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -39,4 +39,5 @@ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +#endif /* SUPERIO_ITE_IT8712F_IT8712F_H */

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coreboot-gerrit March 2014