Patch set updated for coreboot: 62988e2 superio/ite/it8712f: NOTFORMERGE - Avoid .c includes
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5418
-gerrit
commit 62988e2d09fe82506b48c538a8146757e604550a Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat Mar 29 23:23:15 2014 +1100
superio/ite/it8712f: NOTFORMERGE - Avoid .c includes
We should not be #include c files all around the shop.. Link early_serial into romstage and provide a prototype.
This highlights the trainwreck we have with the current Super I/O infrastructure. We really should not have early_serial.c containing what it does here and it should not find its way into ramstage in this way!
Change-Id: I0026eb87749e46bcafd224cf5b61526045c38898 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 35 ------------------------- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/superio/ite/it8712f/Makefile.inc | 3 ++- src/superio/ite/it8712f/early_serial.c | 28 +++++++++++--------- src/superio/ite/it8712f/it8712f.h | 12 ++++++++- 20 files changed, 45 insertions(+), 65 deletions(-)
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 74b6d1b..5b839ae 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -35,7 +35,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2971072..5c00d51 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -30,7 +30,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..4b89122 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -33,7 +33,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..e9cf3f1 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -34,7 +34,7 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/smbus.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/amd/agesa/s3_resume.h" #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..22f10b9 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..23a62d3 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,7 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 18c6f18..bb890d5 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 660ab0f..be2a615 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 1ebdedd..252863f 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -30,7 +30,7 @@ #include "northbridge/intel/i82810/raminit.h" #include "drivers/pc80/udelay_io.c" #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include <lib.h>
void main(unsigned long bist) diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 95ea27d..5a6d743 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -35,7 +35,7 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum. */ diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6edcf37..00935a3 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -35,7 +35,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 68dcfc0..b8ca5c1 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -35,7 +35,7 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h"
int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 59bd618..8ac5601 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -35,7 +35,7 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "northbridge/amd/lx/raminit.h"
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6d36524..fcbf6de 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -43,7 +43,7 @@
#include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h"
#include "cpu/x86/bist.h"
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..cd9cfe2 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -55,11 +55,6 @@ #define TV_MODE_09 0x09 /* SCART-RGB */ #define TV_MODE_NO 0xff /* No TV Support */
-/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 - /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -69,7 +64,6 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ #define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); @@ -82,35 +76,6 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); -} - -static void it8712f_exit_conf(void) -{ - /* Exit the configuration state (MB PnP mode). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - /* set thermal config */ static void set_thermal_config(void) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 42c2599..f757a3c 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -37,7 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 22a1212..1797bb8 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -37,7 +37,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include "superio/ite/it8712f/it8712f.h" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..6fbbfd1 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..6f0e1ff 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,13 +19,9 @@ */
#include <arch/io.h> +#include <device/pnp.h> #include "it8712f.h"
-/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -35,16 +31,23 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
-static void it8712f_sio_write(u8 ldn, u8 index, u8 value) +/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the + LDN the register belongs to, before you can access the register. */ +void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) { - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); + outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); }
-static void it8712f_enter_conf(void) +void it8712f_enter_conf(void) { + /* Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x2e. */ + /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ + /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ u16 port = 0x2e; /* TODO: Don't hardcode! */
outb(0x87, port); @@ -53,8 +56,9 @@ static void it8712f_enter_conf(void) outb((port == 0x4e) ? 0xaa : 0x55, port); }
-static void it8712f_exit_conf(void) +void it8712f_exit_conf(void) { + /* Exit the configuration state (MB PnP mode). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); }
diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..56560da 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -39,4 +39,14 @@ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value); +void it8712f_enter_conf(void); +void it8712f_exit_conf(void); + +#endif /* SUPERIO_ITE_IT8712F_IT8712F_H */
-
Edward O'Callaghan