Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5061
-gerrit
commit f0a2cb6909205e1a0cc756df3f603754118ccf17
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 23 08:34:54 2014 -0800
VBOOT: Set virtual recovery switch based on EC Software Sync
The Virtual Recovery switch flag needs to be set in coreboot since
it is passed through directly to VBOOT layer by depthcharge.
Rather than add a new config option we can assume that devices with
EC Software Sync also have a virtual recovery switch and set the
flag appropriately.
BUG=chrome-os-partner:25250
BRANCH=all
TEST=build and boot on rambi, successfully enter developer mode
Change-Id: Id067eacbc48bc25a86887bce8395fa3a9b85e9f2
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183672
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot_loader.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c
index 6eff99c..badff27 100644
--- a/src/vendorcode/google/chromeos/vboot_loader.c
+++ b/src/vendorcode/google/chromeos/vboot_loader.c
@@ -94,8 +94,10 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff)
*iflags |= VB_INIT_FLAG_WP_ENABLED;
if (CONFIG_VIRTUAL_DEV_SWITCH)
*iflags |= VB_INIT_FLAG_VIRTUAL_DEV_SWITCH;
- if (CONFIG_EC_SOFTWARE_SYNC)
+ if (CONFIG_EC_SOFTWARE_SYNC) {
*iflags |= VB_INIT_FLAG_EC_SOFTWARE_SYNC;
+ *iflags |= VB_INIT_FLAG_VIRTUAL_REC_SWITCH;
+ }
context.handoff = vboot_handoff;
context.cparams = &cparams;
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5059
-gerrit
commit 825bcddc5725c4f71a06d240e2bad962e437405c
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 21 15:24:40 2014 -0800
baytrail: Add basic support for ACPI System Wake Source
This adds the very basic top-level support for determining the
system wake source from ACPI. It only implements the _SWS method
in the _SB scope which just returns a bit index into the PM1
status register for the first fixed functional block.
This can be used to determine wake source of RTC or Power Button
but does not help determine wake source for USB or GPIO.
The ACPI spec says to return -1 if no source can be determined
from PM1 status register.
BUG=chrome-os-partner:8127
BRANCH=baytrail
TEST=build and boot on rambi
1) Test resume from S3 by RTC:
ACPI System Wake Source is PM1 Index 10
(bit 10 is RTC_STS in ACPI spec, ACPI_EVENT_RTC in kernel)
2) Test resume from S3 by power button:
ACPI System Wake Source is PM1 Index 8
(bit 8 is PWRBTN_STS in ACPI spec, ACPI_EVENT_POWER_BUTTON in kernel)
3) Test resume from S3 by USB:
ACPI System Wake Source is PM1 Index -1
Change-Id: Ifc5c0867f82cf291af157537b8c13fe44923d8f5
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183333
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/acpi.c | 3 +++
src/soc/intel/baytrail/acpi/globalnvs.asl | 1 +
src/soc/intel/baytrail/acpi/platform.asl | 5 +++++
src/soc/intel/baytrail/baytrail/nvs.h | 3 ++-
src/soc/intel/baytrail/ramstage.c | 29 +++++++++++++++++++++++++++++
5 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 57233a9..1ab1eb3 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -80,6 +80,9 @@ static acpi_cstate_t cstate_map[] = {
void acpi_init_gnvs(global_nvs_t *gnvs)
{
+ /* Set unknown wake source */
+ gnvs->pm1i = -1;
+
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index b384cea..a201c03 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -52,6 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TPMP, 8, // 0x12 - TPM Present and Enabled
TLVL, 8, // 0x13 - Throttle Level
PPCM, 8, // 0x14 - Maximum P-state usable by OS
+ PM1I, 32, // 0x15 - System Wake Source - PM1 Index
/* Device Config */
Offset (0x20),
diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl
index e069392..e32880e 100644
--- a/src/soc/intel/baytrail/acpi/platform.asl
+++ b/src/soc/intel/baytrail/acpi/platform.asl
@@ -71,3 +71,8 @@ Method(_WAK,1)
Return(Package(){0,0})
}
+Method (_SWS)
+{
+ /* Index into PM1 for device that caused wake */
+ Return (\PM1I)
+}
diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h
index 5bc1b0e..b1561f7 100644
--- a/src/soc/intel/baytrail/baytrail/nvs.h
+++ b/src/soc/intel/baytrail/baytrail/nvs.h
@@ -43,7 +43,8 @@ typedef struct {
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
- u8 rsvd1[11];
+ u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */
+ u8 rsvd1[7];
/* Device Config */
u8 s5u0; /* 0x20 - Enable USB0 in S5 */
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 9fe6c27..0cc9327 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -36,6 +36,7 @@
#include <baytrail/nvs.h>
#include <baytrail/pattrs.h>
#include <baytrail/pci_devs.h>
+#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
/* Global PATTRS */
@@ -131,6 +132,32 @@ static inline void set_acpi_sleep_type(int val)
#endif
}
+/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
+static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+{
+ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+ uint16_t pm1;
+
+ if (!ps)
+ return;
+
+ pm1 = ps->pm1_sts & ps->pm1_en;
+
+ /* Scan for first set bit in PM1 */
+ for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
+ if (pm1 & 1)
+ break;
+ pm1 >>= 1;
+ }
+
+ /* If unable to determine then return -1 */
+ if (gnvs->pm1i >= 16)
+ gnvs->pm1i = -1;
+
+ printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
+ gnvs->pm1i);
+}
+
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
@@ -148,6 +175,8 @@ static void s3_resume_prepare(void)
}
set_acpi_sleep_type(3);
+
+ s3_save_acpi_wake_source(gnvs);
}
void baytrail_init_pre_device(void)
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5056
-gerrit
commit 0fc9572e8458ee032ae05bc89f33eeb621d35404
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Jan 20 11:58:58 2014 -0800
baytrail: Set PMC PTPS register correctly
I messed up in setting this register, it should be using Tj_max-Temp
which in the default case works out to be 90-90=0.
This was apparently heavly throttling the CPU at idle temps.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=build and boot on rambi, run graphics_WebGLPerformance test
Change-Id: I4338280cf50db84dc44313d6fb6771ea5af21dad
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183280
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/dptf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c
index 184f694..044a807 100644
--- a/src/soc/intel/baytrail/dptf.c
+++ b/src/soc/intel/baytrail/dptf.c
@@ -30,7 +30,7 @@ static const struct reg_script dptf_init_settings[] = {
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */
+ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029),