Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4774
-gerrit
commit f81b8536fbf817c582cbcc128f219f3daa80691c
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Thu Jan 23 09:06:08 2014 +0100
lenovo: Handle EEPROM/RFID chip.
EEPROM/RFID chip present in thinkpad should be locked in a way to avoid
any potential RFID access.
Read serial number, UUID and P/N from EEPROM.
This info is stored on AT24RF08 chip acessible through SMBUS.
Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/drivers/i2c/Makefile.inc | 1 +
src/drivers/i2c/at24rf08c/Makefile.inc | 2 +
src/drivers/i2c/at24rf08c/at24rf08c.c | 74 ++++++++++++++++
src/drivers/i2c/at24rf08c/lenovo_serials.c | 137 +++++++++++++++++++++++++++++
src/mainboard/lenovo/t60/devicetree.cb | 11 +++
src/mainboard/lenovo/x201/devicetree.cb | 11 +++
src/mainboard/lenovo/x230/devicetree.cb | 14 ++-
src/mainboard/lenovo/x60/devicetree.cb | 12 ++-
8 files changed, 260 insertions(+), 2 deletions(-)
diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc
index ef7ac4b..8c61b6a 100644
--- a/src/drivers/i2c/Makefile.inc
+++ b/src/drivers/i2c/Makefile.inc
@@ -7,3 +7,4 @@ subdirs-y += lm63
subdirs-y += rtd2132
subdirs-y += w83795
subdirs-y += w83793
+subdirs-y += at24rf08c
diff --git a/src/drivers/i2c/at24rf08c/Makefile.inc b/src/drivers/i2c/at24rf08c/Makefile.inc
new file mode 100644
index 0000000..10c91d1
--- /dev/null
+++ b/src/drivers/i2c/at24rf08c/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-$(CONFIG_VENDOR_LENOVO) += at24rf08c.c
+ramstage-$(CONFIG_VENDOR_LENOVO) += lenovo_serials.c
diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c
new file mode 100644
index 0000000..a9cf2c5
--- /dev/null
+++ b/src/drivers/i2c/at24rf08c/at24rf08c.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <smbios.h>
+#include <console/console.h>
+
+static void at24rf08c_init(device_t dev)
+{
+ int i, j;
+
+ if (!dev->enabled)
+ return;
+
+ /* Ensure that EEPROM/RFID chip is not accessible through RFID.
+ Need to do it only on 5c. */
+ if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c)
+ return;
+
+ printk (BIOS_DEBUG, "Locking EEPROM RFID\n");
+
+ for (i = 0; i < 8; i++)
+ {
+ /* After a register write AT24RF08C sometimes stops responding.
+ Retry several times in case of failure.
+ */
+ for (j = 0; j < 100; j++)
+ if (smbus_write_byte(dev, i, 0x0f) >= 0)
+ break;
+ }
+
+ printk (BIOS_DEBUG, "init EEPROM done\n");
+}
+
+static void at24rf08c_noop(device_t dummy)
+{
+}
+
+static struct device_operations at24rf08c_operations = {
+ .read_resources = at24rf08c_noop,
+ .set_resources = at24rf08c_noop,
+ .enable_resources = at24rf08c_noop,
+ .init = at24rf08c_init,
+};
+
+static void enable_dev(device_t dev)
+{
+ dev->ops = &at24rf08c_operations;
+}
+
+struct chip_operations drivers_i2c_at24rf08c_ops = {
+ CHIP_NAME("AT24RF08C")
+ .enable_dev = enable_dev,
+};
diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c
new file mode 100644
index 0000000..0aab982
--- /dev/null
+++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/smbus.h>
+#include <smbios.h>
+#include <console/console.h>
+
+static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result)
+{
+ int i;
+ device_t dev;
+
+ dev = dev_find_slot_on_smbus(1, 0x54 | bank);
+ if (dev == 0) {
+ printk(BIOS_WARNING, "EEPROM not found\n");
+ memcpy(result, "*INVALID*", sizeof ("*INVALID*"));
+ return;
+ }
+
+ for (i = 0; i < len; i++) {
+ int t;
+ int j;
+ /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding.
+ Retry several times in case of failure.
+ */
+ for (j = 0; j < 100; j++) {
+ t = smbus_read_byte(dev, start + i);
+ if (t >= 0)
+ break;
+ }
+ if (t < 0x20 || t > 0x7f) {
+ memcpy(result, "*INVALID*", sizeof ("*INVALID*"));
+ return;
+ }
+ result[i] = t;
+ }
+}
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char result[12];
+ static int already_read;
+
+ if (already_read)
+ return result;
+
+ memset(result, 0, sizeof (result));
+ at24rf08c_read_string(0, 0x2e, 7, result);
+
+ already_read = 1;
+ return result;
+}
+
+const char *smbios_mainboard_product_name(void)
+{
+ static char result[12];
+ static int already_read;
+
+ if (already_read)
+ return result;
+
+ memset (result, 0, sizeof (result));
+ at24rf08c_read_string(0, 0x27, 7, result);
+
+ already_read = 1;
+ return result;
+}
+
+void smbios_mainboard_set_uuid(u8 *uuid)
+{
+ static char result[16];
+ unsigned i;
+ static int already_read;
+ device_t dev;
+ const int remap[16] = {
+ /* UUID byteswap. */
+ 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15
+ };
+
+
+ if (already_read) {
+ memcpy (uuid, result, 16);
+ return;
+ }
+
+ memset (result, 0, sizeof (result));
+
+ dev = dev_find_slot_on_smbus(1, 0x56);
+ if (dev == 0) {
+ printk(BIOS_WARNING, "eeprom not found\n");
+ already_read = 1;
+ memset (uuid, 0, 16);
+ return;
+ }
+
+ for (i = 0; i < 16; i++) {
+ int t;
+ int j;
+ /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding.
+ Retry several times in case of failure.
+ */
+ for (j = 0; j < 100; j++) {
+ t = smbus_read_byte(dev, 0x12 + i);
+ if (t >= 0)
+ break;
+ }
+ if (t < 0) {
+ memset (result, 0, sizeof (result));
+ break;
+ }
+ result[remap[i]] = t;
+ }
+
+ already_read = 1;
+
+ memcpy (uuid, result, 16);
+}
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 899ea5a..b87a223 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -213,6 +213,17 @@ chip northbridge/intel/i945
register "reg11" = "0x07"
device i2c 69 on end
end
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
end
end
end
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index a8831c2..37a430c 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -145,6 +145,17 @@ chip northbridge/intel/nehalem
end
device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x2167
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
end
end
end
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 3650b38..f630e3d 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -127,7 +127,19 @@ chip northbridge/intel/sandybridge
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on end # SMBus
+ device pci 1f.3 on
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
+ end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index cfbb9db..3880f18 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -190,7 +190,17 @@ chip northbridge/intel/i945
register "reg11" = "0x07"
device i2c 69 on end
end
-
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
end
end
chip southbridge/ricoh/rl5c476
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5066
-gerrit
commit b43785f6c725deb5e15eed77df5eb522a20b3df9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Jan 24 11:06:58 2014 -0600
rambi: disable slp_x stretching after sus fail
In order to boot from G3 quickly disable the
slp_x stretching policy.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I039de7990cc6ff519d873d64756c8d119b131165
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183588
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 15cb5ff..1d83c91 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -48,6 +48,9 @@ chip soc/intel/baytrail
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5065
-gerrit
commit 06d1ad6bf755a5b0aa0d2cdc336ed69513a9ff0f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Jan 24 10:42:00 2014 -0600
baytrail: add config option for disabling slp_x stretching
Provide an option for the mainboard to set in its devicetree
to disable slp_x stretching on SUS power well failure. This
will allow for fast G3->S0 transition instead of waiting for
1-4 seconds.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Enabled option. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I213525b3ad44fe4c95bfd014b614bbc80623cbb8
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183587
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/chip.h | 3 +++
src/soc/intel/baytrail/southcluster.c | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 774f076..0a57885 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -35,6 +35,9 @@ struct soc_intel_baytrail_config {
int vnn_ps2_enable;
int vcc_ps2_enable;
+ /* Disable SLP_X stretching after SUS power well loss. */
+ int disable_slp_x_stretch_sus_fail;
+
/* USB Port Disable mask */
uint16_t usb2_port_disable_mask;
uint16_t usb3_port_disable_mask;
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 1ee5edc..527ae64 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -35,6 +35,7 @@
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
+#include "chip.h"
static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
@@ -145,8 +146,10 @@ static void sc_init(device_t dev)
int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
+ const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1;
const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
+ struct soc_intel_baytrail_config *config = dev->chip_info;
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) {
@@ -161,6 +164,15 @@ static void sc_init(device_t dev)
write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
sc_rtc_init();
+
+ if (config->disable_slp_x_stretch_sus_fail) {
+ printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
+ write32(gen_pmcon1,
+ read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
+ } else {
+ write32(gen_pmcon1,
+ read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
+ }
}
/*
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5064
-gerrit
commit 68840748bdc7e1251ca05e5c4c615aeaf369174c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 23 23:10:53 2014 -0600
rambi: enable PS2 mode for VNN and VCC
Enable the PS2 mode for the VNN and VCC's
voltage regulator. It only gets enabled on
C0 and later parts.
BUG=chrome-os-partner:24542
BRANCH=baytrail
TEST=Built and booted b3.
Change-Id: Id96b5527227ec31da1e5cd106791fe45576b063b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183596
---
src/mainboard/google/rambi/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index fe5ec7b..15cb5ff 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -44,6 +44,10 @@ chip soc/intel/baytrail
register "gpu_pipea_light_off_delay" = "2000" # 200ms
register "gpu_pipea_backlight_pwm" = "0x400"
+ # VR PS2 control
+ register "vnn_ps2_enable" = "1"
+ register "vcc_ps2_enable" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end