Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5040
-gerrit
commit 3632277952153530952c4448e11a11276c72bb5e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 9 14:35:41 2014 -0600
baytrail: reboot with EC in S0 with no MRC cache and EC in RW
This improves boot time in 2 ways for a firmware upgrade:
1. Normally MRC would detect the S0 state without an MRC cache
even though it's told to the S5 path. When it observes this
state a cold reset occurs. The cold reset stays in S5 for
at least 4 seconds which is time observed by the end user.
2. As the EC was running RW code before the reset after firmware
upgrade it will still be running the older RW code. Vboot will
then reboot the EC and the whole system to put the EC into RO
mode so it can handle the RW update.
The issues are mitigated by detecting the system is in S0 with
no MRC cache and the EC isn't in RO mode. Therefore we can do the
reboot without waiting the 4 secs and the EC is running RO so
the 2nd reboot is not necessary.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
EC reboot before MRC execution.
Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182061
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/romstage/raminit.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 9b0d892..d49735b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -31,6 +31,8 @@
#include <baytrail/pci_devs.h>
#include <baytrail/reset.h>
#include <baytrail/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
@@ -138,6 +140,12 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ if (prev_sleep_state == 0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
}
mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab,
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5039
-gerrit
commit 9df5b97dc554dc02f176125aed4f95ff4ca7e29b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 9 14:28:05 2014 -0600
chromeec: add function to reboot on unexpected image
It's helpful to have a generic function that will tell
the EC to reboot if the EC isn't running a specified
image. Add that and implement google_chromeec_early_init()
to utilize the new function still maintaing its semantics
of if recvoery mode is enabled the EC should be running its
RO image. There is a slight change in that no communication
is done with the EC if not in recovery mode.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Built and boot with recovery request. Noted EC reboot.
Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182060
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/ec/google/chromeec/ec.c | 16 +++++++++++-----
src/ec/google/chromeec/ec.h | 3 +++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index f1cefae..0dcbbd3 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -100,8 +100,7 @@ u32 google_chromeec_get_events_b(void)
}
#ifndef __SMM__
-/* Check for recovery mode and ensure EC is in RO */
-void google_chromeec_early_init(void)
+void google_chromeec_check_ec_image(int expected_type)
{
struct chromeec_command cec_cmd;
struct ec_response_get_version cec_resp = {{0}};
@@ -113,9 +112,7 @@ void google_chromeec_early_init(void)
cec_cmd.cmd_size_out = sizeof(cec_resp);
google_chromeec_command(&cec_cmd);
- if (cec_cmd.cmd_code ||
- (recovery_mode_enabled() &&
- (cec_resp.current_image != EC_IMAGE_RO))) {
+ if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) {
struct ec_params_reboot_ec reboot_ec;
/* Reboot the EC and make it come back in RO mode */
reboot_ec.cmd = EC_REBOOT_COLD;
@@ -133,6 +130,15 @@ void google_chromeec_early_init(void)
}
}
+/* Check for recovery mode and ensure EC is in RO */
+void google_chromeec_early_init(void)
+{
+ /* If in recovery ensure EC is running RO firmware. */
+ if (recovery_mode_enabled()) {
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+}
+
u16 google_chromeec_get_board_version(void)
{
struct chromeec_command cmd;
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index a037d01..d033bab 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -36,7 +36,10 @@ int google_ec_running_ro(void);
void google_chromeec_init(void);
#endif
+/* If recovery mode is enabled and EC is not running RO firmware reboot. */
void google_chromeec_early_init(void);
+/* Reboot if EC firmware is not expected type. */
+void google_chromeec_check_ec_image(int expected_type);
uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size);
u16 google_chromeec_get_board_version(void);
u32 google_chromeec_get_events_b(void);
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5036
-gerrit
commit ded0afe489c58a4c5e3636f1da88bb454821b44f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Jan 9 10:01:05 2014 -0800
chrome ec: Fix temperature calcualtion in PATx methods
The PATx methods will be passed a temperature in deci-kelvin,
so it needs to be converted back to kelvin before being sent
to the EC.
The PAT disable method is changed to take the temperature ID
as an argument so individual sensors can be disabled.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, load esif_lf kernel drivers and
esif_uf userspace application. Start and stop DPTF and see
that temperature thresholds are set to sane values.
Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182023
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/ec/google/chromeec/acpi/ec.asl | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index c931225..1cadcc8 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -299,13 +299,14 @@ Device (EC0)
Return (0)
}
- Store ("EC: PAT0", Debug)
-
/* Set sensor ID */
Store (ToInteger (Arg0), ^PATI)
- /* Adjust by offset to get Kelvin and set Threshold */
- Add (ToInteger (Arg1), ^TOFS, ^PATT)
+ /* Temperature is passed in 1/10 Kelvin */
+ Divide (ToInteger (Arg1), 10, Local0, Local1)
+
+ /* Adjust by EC temperature offset */
+ Subtract (Local1, ^TOFS, ^PATT)
/* Set commit value with SELECT=0 and ENABLE=1 */
Store (0x02, ^PATC)
@@ -325,13 +326,14 @@ Device (EC0)
Return (0)
}
- Store ("EC: PAT1", Debug)
-
/* Set sensor ID */
Store (ToInteger (Arg0), ^PATI)
- /* Adjust by offset to get Kelvin and set Threshold */
- Add (ToInteger (Arg1), ^TOFS, ^PATT)
+ /* Temperature is passed in 1/10 Kelvin */
+ Divide (ToInteger (Arg1), 10, Local0, Local1)
+
+ /* Adjust by EC temperature offset */
+ Subtract (Local1, ^TOFS, ^PATT)
/* Set commit value with SELECT=1 and ENABLE=1 */
Store (0x03, ^PATC)
@@ -340,16 +342,16 @@ Device (EC0)
Return (1)
}
- /* Disable Aux Trip Points */
- Method (PATD)
+ /* Disable Aux Trip Points
+ * Arg0 = Temp Sensor ID
+ */
+ Method (PATD, 1, Serialized)
{
If (Acquire (^PATM, 1000)) {
Return (0)
}
- Store ("EC: PAT Disable", Debug)
-
- Store (0x00, ^PATI)
+ Store (ToInteger (Arg0), ^PATI)
Store (0x00, ^PATT)
/* Disable PAT0 */
@@ -365,14 +367,12 @@ Device (EC0)
/*
* Thermal Threshold Event
*/
- Method (_Q09, 0, Serialized)
+ Method (_Q09, 0, NotSerialized)
{
If (Acquire (^PATM, 1000)) {
Return ()
}
- Store ("EC: THERMAL THRESHOLD", Debug)
-
/* Read sensor ID for event */
Store (^PATI, Local0)
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5035
-gerrit
commit 98d634a99a8e6a6ae84627e2beb6fb1e990e8208
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 9 10:44:06 2014 -0600
baytrail: don't SMI on tco timer firing
The SMI on TCO timer timeout policy was copied from other
chipsets. However, it's not very advantageous to have
the TCO timer timeout trigger an SMI unless the firmware
was the one responsible for setting up the timer.
BUG=chromium:321832
BRANCH=rambi,squawks
TEST=Manually enabled TCO timer. TCO fires and logged in
eventlog.
Change-Id: I420b14d6aa778335a925784a64160fa885cba20f
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181985
---
src/soc/intel/baytrail/smm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index 1fb35d7..d4b3d58 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -102,14 +102,14 @@ void southcluster_smm_enable_smi(void)
southcluster_smm_route_gpios();
/* Enable SMI generation:
- * - on TCO events
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
* No SMIs:
+ * - on TCO events
* - on microcontroller writes (io 0x62/0x66)
*/
- enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5033
-gerrit
commit 659cad4c09bb2cb8e0c539c7a78c2e5c739c0a41
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 9 10:41:30 2014 -0600
baytrail: log reset, power, and wake events in elog
When CONFIG_ELOG is selected the reset, power, and wake
events are logged in the eventlog.
BUG=chrome-os-partner:24907
BRANCH=rambi,squawks
TEST=Various resets and wake sources. Interrogated eventlog
to ensure results are expected.
Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181983
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/elog.c | 118 ++++++++++++++++++++++++++++++++++++
2 files changed, 119 insertions(+)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index eafa65f..85ddb94 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -47,6 +47,7 @@ ramstage-y += sd.c
ramstage-y += perf_power.c
ramstage-y += stage_cache.c
romstage-y += stage_cache.c
+ramstage-$(CONFIG_ELOG) += elog.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c
new file mode 100644
index 0000000..8c6be9f
--- /dev/null
+++ b/src/soc/intel/baytrail/elog.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <stdint.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <elog.h>
+#include <baytrail/iomap.h>
+#include <baytrail/pmc.h>
+
+static void log_power_and_resets(const struct chipset_power_state *ps)
+{
+ if (ps->gen_pmcon1 & PWR_FLR) {
+ elog_add_event(ELOG_TYPE_POWER_FAIL);
+ elog_add_event(ELOG_TYPE_PWROK_FAIL);
+ }
+
+ if (ps->gen_pmcon1 & SUS_PWR_FLR) {
+ elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
+ }
+
+ if (ps->tco_sts & SECOND_TO_STS) {
+ elog_add_event(ELOG_TYPE_TCO_RESET);
+ }
+
+ if (ps->pm1_sts & PRBTNOR_STS) {
+ elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
+ }
+
+ if (ps->gen_pmcon1 & SRS) {
+ elog_add_event(ELOG_TYPE_RESET_BUTTON);
+ }
+
+ if (ps->gen_pmcon1 & GEN_RST_STS) {
+ elog_add_event(ELOG_TYPE_SYSTEM_RESET);
+ }
+}
+
+static void log_wake_events(const struct chipset_power_state *ps)
+{
+ const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS |
+ PCIE_WAKE2_STS | PCIE_WAKE1_STS |
+ PCIE_WAKE0_STS;
+ uint32_t gpe0_sts;
+ uint32_t gpio_mask;
+ int i;
+
+ /* Mask off disabled events. */
+ gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
+
+ if (ps->pm1_sts & WAK_STS) {
+ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
+ acpi_slp_type == 3 ? 3 : 5);
+ }
+
+ if (ps->pm1_sts & PWRBTN_STS) {
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
+ }
+
+ if (ps->pm1_sts & RTC_STS) {
+ elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
+ }
+
+ if (gpe0_sts & PME_B0_EN) {
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
+ }
+
+ if (gpe0_sts & pcie_wake_mask) {
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+ }
+
+ gpio_mask = SUS_GPIO_STS0;
+ i = 0;
+ while (gpio_mask) {
+ if (gpio_mask & gpe0_sts) {
+ elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+ }
+ gpio_mask <<= 1;
+ i++;
+ }
+}
+
+void southcluster_log_state(void)
+{
+ struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+ if (ps == NULL) {
+ printk(BIOS_DEBUG, "Not logging power state information. "
+ "Power state not found in cbmem.\n");
+ return;
+ }
+
+ log_power_and_resets(ps);
+ log_wake_events(ps);
+}