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coreboot-gerrit@coreboot.org
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New patch to review for coreboot: 51fa54d ramstage_cache: allow ramstage usage add valid helper
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5011
-gerrit commit 51fa54d8c321472e6def02fc67410c611abf97d7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:10:52 2013 -0800 ramstage_cache: allow ramstage usage add valid helper Allow ramstage cache to be used from ramstage proper. Also add a helper function for checking validity of ramstage cache structure. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179775
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/ramstage_cache.h | 10 +++++++--- src/lib/ramstage_cache.c | 2 +- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/include/ramstage_cache.h b/src/include/ramstage_cache.h index 5b0597a..8d9b095 100644 --- a/src/include/ramstage_cache.h +++ b/src/include/ramstage_cache.h @@ -20,9 +20,8 @@ #ifndef _RAMSTAGE_CACHE_ #define _RAMSTAGE_CACHE_ -#if !defined(__PRE_RAM__) -#error "ramstage_cache only used in romstage for loading ramstage." -#endif +#include <stddef.h> +#include <stdint.h> /* This structure is saved along with the relocated ramstage program when * CONFIG_RELOCATED_RAMSTAGE is employed. For x86, it can used to protect @@ -46,4 +45,9 @@ struct ramstage_cache *ramstage_cache_location(long *size); /* Chipset/Board function called when cache is invalid on resume. */ void ramstage_cache_invalid(struct ramstage_cache *cache); +static inline int ramstage_cache_is_valid(const struct ramstage_cache *c) +{ + return (c != NULL && c->magic == RAMSTAGE_CACHE_MAGIC); +} + #endif /* _RAMSTAGE_CACHE_ */ diff --git a/src/lib/ramstage_cache.c b/src/lib/ramstage_cache.c index a1a4804..0f7273a 100644 --- a/src/lib/ramstage_cache.c +++ b/src/lib/ramstage_cache.c @@ -79,7 +79,7 @@ void *load_cached_ramstage(struct romstage_handoff *handoff, cache = ramstage_cache_location(&size); - if (cache == NULL || cache->magic != RAMSTAGE_CACHE_MAGIC) { + if (!ramstage_cache_is_valid(cache)) { printk(BIOS_DEBUG, "Invalid ramstage cache found.\n"); ramstage_cache_invalid(cache); return NULL;
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New patch to review for coreboot: 5630539 baytrail: note S3 resume status earlier
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5010
-gerrit commit 563053961fba0f17c32fa08af817882b9c333d9f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:07:00 2013 -0800 baytrail: note S3 resume status earlier Certain code paths want to know if S3 resume is happening. However, the current baytrail code doesn't note S3 resume early enough. Therefore, mark S3 resume just after pattr setup. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179774
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/ramstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index b0b48b0..9fe6c27 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -159,6 +159,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + /* Run reference code. */ baytrail_run_reference_code(); @@ -167,7 +170,4 @@ void baytrail_init_pre_device(void) setup_soc_gpios(config); baytrail_init_scc(); - - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); }
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New patch to review for coreboot: f8b9d72 baytrail: utilize reg_script_run_on_dev()
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5009
-gerrit commit f8b9d72a35e205470e9368f4f952b8fbd3824776 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 17:12:44 2013 -0800 baytrail: utilize reg_script_run_on_dev() The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin(a)chromium.og> Reviewed-on:
https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/ehci.c | 28 +++++++++++----------------- src/soc/intel/baytrail/emmc.c | 9 ++------- src/soc/intel/baytrail/gfx.c | 15 ++++----------- src/soc/intel/baytrail/lpss.c | 11 ++++------- src/soc/intel/baytrail/pcie.c | 11 ++--------- src/soc/intel/baytrail/scc.c | 3 +-- src/soc/intel/baytrail/xhci.c | 11 ++++------- 7 files changed, 28 insertions(+), 60 deletions(-) diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index c648415..d4e2986 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -34,7 +34,7 @@ #include "chip.h" -const struct reg_script ehci_init_script[] = { +static const struct reg_script ehci_init_script[] = { /* Enable S0 PLL shutdown * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ REG_PCI_OR16(0x7a, 0x14de), @@ -60,7 +60,7 @@ const struct reg_script ehci_init_script[] = { REG_SCRIPT_END }; -const struct reg_script ehci_clock_gating_script[] = { +static const struct reg_script ehci_clock_gating_script[] = { /* Enable SB local clock gating */ REG_PCI_OR32(0x7c, 0x00004000), /* RCBA + 0x284=0xbe (step B0+) */ @@ -68,7 +68,7 @@ const struct reg_script ehci_clock_gating_script[] = { REG_SCRIPT_END }; -const struct reg_script ehci_disable_script[] = { +static const struct reg_script ehci_disable_script[] = { /* Clear Run/Stop Bit */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), /* Wait for HC Halted */ @@ -86,6 +86,11 @@ const struct reg_script ehci_disable_script[] = { REG_SCRIPT_END }; +static const struct reg_script ehci_hc_reset[] = { + REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), + REG_SCRIPT_END +}; + static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -121,18 +126,7 @@ static void usb2_phy_init(device_t dev) static void ehci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ehci_hc_reset[] = { - REG_SCRIPT_SET_DEV(dev), - REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), - REG_SCRIPT_END - }; - struct reg_script ehci_hc_disable[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(ehci_disable_script), - REG_SCRIPT_END - }; struct reg_script ehci_hc_init[] = { - REG_SCRIPT_SET_DEV(dev), /* Controller init */ REG_SCRIPT_NEXT(ehci_init_script), /* Enable clock gating */ @@ -150,19 +144,19 @@ static void ehci_init(device_t dev) /* Don't reset controller in S3 resume path */ if (acpi_slp_type != 3) - reg_script_run(ehci_hc_reset); + reg_script_run_on_dev(dev, ehci_hc_reset); /* Disable controller if ports are routed to XHCI */ if (config->usb_route_to_xhci) { /* Disable controller */ - reg_script_run(ehci_hc_disable); + reg_script_run_on_dev(dev, ehci_disable_script); /* Hide device with southcluster function */ dev->enabled = 0; southcluster_enable_dev(dev); } else { /* Initialize EHCI controller */ - reg_script_run(ehci_hc_init); + reg_script_run_on_dev(dev, ehci_hc_init); } /* Setup USB2 PHY based on board config */ diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 0a7e9b1..a724c4a 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -52,16 +52,11 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(emmc_ops), - REG_SCRIPT_END, - }; - printk(BIOS_DEBUG, "eMMC init\n"); - reg_script_run(ops); if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + printk(BIOS_DEBUG, "eMMC init\n"); + reg_script_run_on_dev(dev, emmc_ops); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index bf271be..37fdc70 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -259,14 +259,9 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) { - struct reg_script steps[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(ops), - REG_SCRIPT_END, - }; - reg_script_run(&steps[0]); + reg_script_run_on_dev(dev, ops); } static void gfx_pre_vbios_init(device_t dev) @@ -294,7 +289,6 @@ static void gfx_panel_setup(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { - REG_SCRIPT_SET_DEV(dev), /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), @@ -322,7 +316,6 @@ static void gfx_panel_setup(device_t dev) REG_SCRIPT_END }; struct reg_script gfx_pipeb_init[] = { - REG_SCRIPT_SET_DEV(dev), /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), @@ -352,12 +345,12 @@ static void gfx_panel_setup(device_t dev) if (config->gpu_pipea_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); - reg_script_run(gfx_pipea_init); + reg_script_run_on_dev(dev, gfx_pipea_init); } if (config->gpu_pipeb_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); - reg_script_run(gfx_pipeb_init); + reg_script_run_on_dev(dev, gfx_pipeb_init); } } diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index e009c7d..a543fd8 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -36,7 +36,6 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -68,20 +67,19 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.lpss_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), REG_SCRIPT_END, }; - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) @@ -128,8 +126,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) static void i2c_disable_resets(device_t dev) { /* Release the I2C devices from reset. */ - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script ops[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), REG_SCRIPT_END, }; @@ -146,7 +143,7 @@ static void i2c_disable_resets(device_t dev) CASE_I2C(I2C6): CASE_I2C(I2C7): printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); break; default: return; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index f68304d..ce76d6d 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -90,7 +90,6 @@ static const struct reg_script init_static_after_exit_latency[] = { static void byt_pcie_init(device_t dev) { struct reg_script init_script[] = { - REG_SCRIPT_SET_DEV(dev), REG_SCRIPT_NEXT(init_static_before_exit_latency), /* Exit latency configuration based on * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ @@ -108,7 +107,7 @@ static void byt_pcie_init(device_t dev) REG_SCRIPT_END, }; - reg_script_run(init_script); + reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -157,19 +156,13 @@ static void check_port_enabled(device_t dev) static void check_device_present(device_t dev) { - struct reg_script no_dev[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(no_dev_behind_port), - REG_SCRIPT_END, - }; - /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); - reg_script_run(no_dev); + reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } else if(!dev->enabled) { /* Port is disabled, but device present. Disable link. */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 64792c2..7efb66d 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -90,7 +90,6 @@ void baytrail_init_scc(void) void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -122,5 +121,5 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.scc_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 1155ca6..b6dc2b2 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -132,7 +132,6 @@ const struct reg_script xhci_clock_gating_script[] = { static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { - REG_SCRIPT_SET_DEV(dev), /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WPR), @@ -145,14 +144,13 @@ static void xhci_reset_port_usb3(device_t dev, int port) ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), REG_SCRIPT_END }; - reg_script_run(reset_port_usb3_script); + reg_script_run_on_dev(dev, reset_port_usb3_script); } /* Prepare ports to be routed to EHCI or XHCI */ static void xhci_route_all(device_t dev) { - struct reg_script xhci_route_all_script[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), /* USB2 Port Route to XHCI */ @@ -165,7 +163,7 @@ static void xhci_route_all(device_t dev) printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); /* Route ports to XHCI controller */ - reg_script_run(xhci_route_all_script); + reg_script_run_on_dev(dev, xhci_route_all_script); /* Reset enabled USB3 ports */ port_disabled = pci_read_config32(dev, XHCI_USB3PDO); @@ -180,7 +178,6 @@ static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { - REG_SCRIPT_SET_DEV(dev), /* Setup USB3 phy */ REG_SCRIPT_NEXT(usb3_phy_script), /* Initialize host controller */ @@ -207,7 +204,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller */ - reg_script_run(xhci_hc_init); + reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci)
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New patch to review for coreboot: 10bd5fa baytrail: initialize perf/power registers
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5008
-gerrit commit 10bd5facff46dd049c9c5098362a4f4775e95068 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 11 17:15:45 2013 -0800 baytrail: initialize perf/power registers According to the reference code all these registers need to be set to their best known values. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. No idea about observable impact yet. Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179749
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/perf_power.c | 295 ++++++++++++++++++++++++++++++++++++ 2 files changed, 296 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 63e7c61..f601c7e 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += emmc.c ramstage-y += lpss.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += perf_power.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c new file mode 100644 index 0000000..a577c6b --- /dev/null +++ b/src/soc/intel/baytrail/perf_power.c @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <reg_script.h> +#include <baytrail/iosf.h> + +#define MAKE_MASK_INCLUSIVE(msb) \ + ((1ULL << (1 + (msb))) - 1) +#define MAKE_MASK(msb) \ + ((1ULL << (msb)) - 1) +#define MASK_VAL(msb, lsb, val) \ + ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) + +#define E(arg1, arg2, args) \ + REG_IOSF_RMW(IOSF_PORT_##arg1, arg2, args) + +static const struct reg_script perf_power_settings[] = { +E(AUNIT, 0x18, MASK_VAL(22, 22, 0x1)), // ACKGATE.AMESSAGE_MSGIF +E(AUNIT, 0x18, MASK_VAL(21, 21, 0x1)), // ACKGATE.AREQDOWN_SCL0_ARB +E(AUNIT, 0x18, MASK_VAL(20, 20, 0x1)), // ACKGATE.AREQUP_MIRROR +E(AUNIT, 0x18, MASK_VAL(19, 19, 0x1)), // ACKGATE.AREQTAHACK +E(AUNIT, 0x18, MASK_VAL(18, 18, 0x1)), // ACKGATE.AREQDOWN_TAREQQ +E(AUNIT, 0x18, MASK_VAL(17, 17, 0x1)), // ACKGATE.AREQDOWN_CREDIT +E(AUNIT, 0x18, MASK_VAL(16, 16, 0x1)), // ACKGATE.ASCLUP_FAIR_ARBITER +E(AUNIT, 0x18, MASK_VAL(15, 15, 0x1)), // ACKGATE.AIOSFDOWN_DATA +E(AUNIT, 0x18, MASK_VAL(14, 14, 0x1)), // ACKGATE.ASCLUP_IOSF_ADAPTER +E(AUNIT, 0x18, MASK_VAL(12, 12, 0x1)), // ACKGATE.ASCLUP_CMD_QUEUE +E(AUNIT, 0x18, MASK_VAL(11, 11, 0x1)), // ACKGATE.ASCLUP_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(10, 10, 0x1)), // ACKGATE.AREQUP_CMD_QUEUE +E(AUNIT, 0x18, MASK_VAL(9, 9, 0x1)), // ACKGATE.AREQUP_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(8, 8, 0x1)), // ACKGATE.AREQDOWN_RSP_QUEUE +E(AUNIT, 0x18, MASK_VAL(7, 7, 0x1)), // ACKGATE.AREQDOWN_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(6, 6, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DRVR +E(AUNIT, 0x18, MASK_VAL(5, 5, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF +E(AUNIT, 0x18, MASK_VAL(4, 4, 0x1)), // ACKGATE.AT_REQ_QUEUE +E(AUNIT, 0x18, MASK_VAL(3, 3, 0x1)), // ACKGATE.AT_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(2, 2, 0x1)), // ACKGATE.TA_REQ_QUEUE +E(AUNIT, 0x18, MASK_VAL(1, 1, 0x1)), // ACKGATE.TA_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(0, 0, 0x1)), // ACKGATE.CONFIG_REGS +E(AUNIT, 0x20, MASK_VAL(26, 24, 0x2)), // AISOCHCTL.CHANNEL_AB_DEADLINE_EN +E(AUNIT, 0x20, MASK_VAL(8, 0, 0x1)), // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY +E(AUNIT, 0x21, MASK_VAL(31, 31, 0x1)), // AVCCTL.EFFICIENT_PERF_UP_EN +E(AUNIT, 0x21, MASK_VAL(8, 8, 0x0)), // AVCCTL.VC_EN_PRIORITY_DNARB +E(AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)), // AARBCTL0.IOSF0VC2_WGT +E(AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)), // AARBCTL0.IOSF0VC1_WGT +E(AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)), // AARBCTL0.IOSF0VC0_WGT +E(BUNIT, 0x3, MASK_VAL(29, 24, 0x4)), // BARBCTRL0.AGENT3_WEIGHT +E(BUNIT, 0x3, MASK_VAL(21, 16, 0x4)), // BARBCTRL0.AGENT2_WEIGHT +E(BUNIT, 0x3, MASK_VAL(13, 8, 0x4)), // BARBCTRL0.AGENT1_WEIGHT +E(BUNIT, 0x3, MASK_VAL(5, 0, 0x4)), // BARBCTRL0.AGENT0_WEIGHT +E(BUNIT, 0x4, MASK_VAL(29, 24, 0x4)), // BARBCTRL1.AGENT7_WEIGHT +E(BUNIT, 0x4, MASK_VAL(21, 16, 0x4)), // BARBCTRL1.AGENT6_WEIGHT +E(BUNIT, 0x4, MASK_VAL(13, 8, 0x4)), // BARBCTRL1.AGENT5_WEIGHT +E(BUNIT, 0x4, MASK_VAL(5, 0, 0x4)), // BARBCTRL1.AGENT4_WEIGHT +E(BUNIT, 0x5, MASK_VAL(21, 16, 0x4)), // BARBCTRL2.AGENT10_WEIGHT +E(BUNIT, 0x5, MASK_VAL(13, 8, 0x4)), // BARBCTRL2.AGENT9_WEIGHT +E(BUNIT, 0x5, MASK_VAL(5, 0, 0x8)), // BARBCTRL2.AGENT8_WEIGHT +E(BUNIT, 0x7, MASK_VAL(31, 24, 0x20)), // BWFLUSH.FLUSH_THRSHOLD +E(BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)), // BWFLUSH.DIRTY_LWM +E(BUNIT, 0x7, MASK_VAL(7, 0, 0x10)), // BWFLUSH.DIRTY_HWM +E(BUNIT, 0x8, MASK_VAL(23, 0, 0x0)), // BBANKMASK.BANK_MASK +E(BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)), // BROWMASK.ROW_MASK +E(BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)), // BRANKMASK.RANK_MASK +E(BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)), // BALIMIT0.AGENT3_LIMIT +E(BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)), // BALIMIT0.AGENT2_LIMIT +E(BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)), // BALIMIT0.AGENT1_LIMIT +E(BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)), // BALIMIT0.AGENT0_LIMIT +E(BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)), // BALIMIT1.AGENT7_LIMIT +E(BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)), // BALIMIT1.AGENT6_LIMIT +E(BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)), // BALIMIT1.AGENT5_LIMIT +E(BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)), // BALIMIT1.AGENT4_LIMIT +E(BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)), // BALIMIT2.AGENT10_LIMIT +E(BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)), // BALIMIT2.AGENT9_LIMIT +E(BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)), // BALIMIT2.AGENT8_LIMIT +E(BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)), // BARES0.AGENT7_RSVD +E(BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)), // BARES0.AGENT6_RSVD +E(BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)), // BARES0.AGENT5_RSVD +E(BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)), // BARES0.AGENT4_RSVD +E(BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)), // BARES0.AGENT3_RSVD +E(BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)), // BARES0.AGENT2_RSVD +E(BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)), // BARES0.AGENT1_RSVD +E(BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)), // BARES0.AGENT0_RSVD +E(BUNIT, 0x10, MASK_VAL(9, 8, 0x0)), // BARES1.AGENT10_RSVD +E(BUNIT, 0x10, MASK_VAL(5, 4, 0x0)), // BARES1.AGENT9_RSVD +E(BUNIT, 0x10, MASK_VAL(1, 0, 0x0)), // BARES1.AGENT8_RSVD +E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH +E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN +E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY +E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY +E(BUNIT, 0x11, MASK_VAL(6, 0, 0xC)), // BISOC.EXIT_SELF_REFRESH_LATENCY +E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE +E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 +E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13 +E(BUNIT, 0x12, MASK_VAL(25, 24, 0x0)), // BCOSCAT.COS_CAT_AGENT12 +E(BUNIT, 0x12, MASK_VAL(23, 22, 0x0)), // BCOSCAT.COS_CAT_AGENT11 +E(BUNIT, 0x12, MASK_VAL(21, 20, 0x0)), // BCOSCAT.COS_CAT_AGENT10 +E(BUNIT, 0x12, MASK_VAL(19, 18, 0x0)), // BCOSCAT.COS_CAT_AGENT9 +E(BUNIT, 0x12, MASK_VAL(17, 16, 0x1)), // BCOSCAT.COS_CAT_AGENT8 +E(BUNIT, 0x12, MASK_VAL(15, 14, 0x0)), // BCOSCAT.COS_CAT_AGENT7 +E(BUNIT, 0x12, MASK_VAL(13, 12, 0x0)), // BCOSCAT.COS_CAT_AGENT6 +E(BUNIT, 0x12, MASK_VAL(11, 10, 0x1)), // BCOSCAT.COS_CAT_AGENT5 +E(BUNIT, 0x12, MASK_VAL(9, 8, 0x1)), // BCOSCAT.COS_CAT_AGENT4 +E(BUNIT, 0x12, MASK_VAL(7, 6, 0x0)), // BCOSCAT.COS_CAT_AGENT3 +E(BUNIT, 0x12, MASK_VAL(5, 4, 0x0)), // BCOSCAT.COS_CAT_AGENT2 +E(BUNIT, 0x12, MASK_VAL(3, 2, 0x0)), // BCOSCAT.COS_CAT_AGENT1 +E(BUNIT, 0x12, MASK_VAL(1, 0, 0x0)), // BCOSCAT.COS_CAT_AGENT0 +E(BUNIT, 0x14, MASK_VAL(31, 31, 0x0)), // BFLWT.DISABLE_FLUSH_WEIGHTS +E(BUNIT, 0x14, MASK_VAL(30, 30, 0x0)), // BFLWT.ENABLE_READ_INVALIDATE_TIMER +E(BUNIT, 0x14, MASK_VAL(13, 8, 0x8)), // BFLWT.WRITE_WEIGHTS +E(BUNIT, 0x14, MASK_VAL(5, 0, 0x10)), // BFLWT.READ_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(31, 31, 0x0)), // BISOCWT.ENABLE_ISOC_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)), // BISOCWT.ISOC_REQUEST_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(5, 0, 0x8)), // BISOCWT.NON_ISOC_REQUEST_WEIGHTS +E(BUNIT, 0x18, MASK_VAL(31, 24, 0x20)), // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY +E(BUNIT, 0x18, MASK_VAL(23, 21, 0x6)), // BSCHCTRL0.PAGE_HIT_DELAY +E(BUNIT, 0x18, MASK_VAL(13, 7, 0x0)), // BSCHCTRL0.ISOC_BANK_PREFETCH +E(BUNIT, 0x18, MASK_VAL(6, 0, 0x20)), // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH +E(BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)), // BDEBUG0.CASUAL_TIMER +E(BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)), // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC +E(BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)), // BDEBUG0.CASUAL_WATER_MARK +E(BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)), // BDEBUG1.AGENT_WEIGHT_ENABLE +E(BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)), // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH +E(BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)), // BDEBUG1.ENABLE_DRAM_SELF_RFRSH +E(BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)), // BCTRL.BANK_STATUS_ENABLE +E(BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)), // BCTRL.DISABLE_OWNED +E(BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)), // BCTRL.INORDER_READ_ENABLE +E(BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)), // BCTRL.INORDER_FLUSH_ENABLE +E(BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)), // BCTRL.MISS_VALID_ENTRIES +E(BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)), // BCTRL.DIRTY_STALL +E(BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)), // BCTRL.SINGLE_TAG_ACCESS +E(BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)), // BCTRL.SINGLE_CHUNK_ACCESS +E(BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)), // BCTRL.BECLK_GATE_EN +E(BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)), // BCTRL.MASTERCLK_GATE_EN +E(BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)), // BCTRL.REQUESTCLK_GATE_EN +E(BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)), // BTHCTRL.AGENT_THROTTLING_ENABLE +E(BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)), // BTHCTRL.RANK_SELECTION_MASK +E(BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)), // BTHMASK.ORWRITE_MASK +E(BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)), // BTHMASK.ORREAD_MASK +E(BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)), // BTHMASK.ERWRITE_MASK +E(BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)), // BTHMASK.ERREAD_MASK + //0x02, 0x0, 2, 0, 0x1, //T_INTR_REDIR_CTL.REDIR_MODE_SEL +E(CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)), // T_CTL.SPLIT_GOIWP_MODE +E(CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)), // T_CTL.DISABLE_TRDY_RDGO +E(CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)), // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN +E(CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)), // T_CTL.ENABLE_NPC_COLLECTOR +E(CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)), // T_CTL.ENABLE_IN_ORDER_APIC +E(CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)), // T_CTL.TG_HIGHPRI_WRITE_PULLS + //0x02, 0x3, 12, 12, 0x1, // T_CTL.TG_NDRAMSNP +E(CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)), // T_CTL.TG_DW_POST_PUSH_LOG +E(CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)), // T_CTL.ALWAYS_SNP_IDI +E(CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)), // T_CTL.DIS_LIVE_BRAM_BYP_IDI +E(CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)), // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE +E(CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)), // T_MISC_CTL.DPTE_CNT +E(CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)), // T_MISC_CTL.DPTE_EN +E(CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)), // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)), // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)), // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)), // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)), // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)), // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)), // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)), // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)), // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)), // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)), // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)), // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)), // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)), // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)), // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)), // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)), // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)), // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)), // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)), // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)), // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)), // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)), // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)), // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)), // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)), // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x55, 0x54, MASK_VAL(1, 0, 0x0)), // SMB_Config_PMCSR.PS +E(0x55, 0x0FC, MASK_VAL(17, 17, 0x0)), // SMB_Config_CGC.FUNC_CLK_CGD +E(0x55, 0x0FC, MASK_VAL(9, 9, 0x0)), // SMB_Config_CGC.SB_LOCAL_CGD +E(0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x47, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x45, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x46, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(PMC, 0x0, MASK_VAL(11, 11, 0x1)), // PUNIT_CONTROL.MODE_DEMOTE_EN +E(PMC, 0x0, MASK_VAL(10, 10, 0x1)), // PUNIT_CONTROL.CORE_DEMOTE_EN + + // + //s0ix_PnP_Settings + // +E(0x58, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en +E(0x58, 0x1e0, MASK_VAL(0, 0, 0x0)), //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en +E(0x58, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en +E(0x58, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en +E(0x58, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en +E(0x58, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en +E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate +E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 +E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en +E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en +E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en +E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en +E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en +E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en +E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on +E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en +E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en +E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en +E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en +E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en +E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en +E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel +E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e +E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc +E(0x5a, 0x40, MASK_VAL(18, 18, 0x1)), //vlv.usb.xhci.controller.xhcc1.xhcil1e +E(0x5a, 0x50, MASK_VAL(3, 3, 0x1)), //vlv.usb.xhci.controller.xhclkgten.hsltcge +E(0x5a, 0x50, MASK_VAL(0, 0, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfblcge +E(0x5a, 0x50, MASK_VAL(1, 1, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfbtcge +E(0x5a, 0x50, MASK_VAL(2, 2, 0x1)), //vlv.usb.xhci.controller.xhclkgten.ssltcge +E(0x5a, 0x50, MASK_VAL(7, 5, 0x2)), //vlv.usb.xhci.controller.xhclkgten.sspllsue +E(0x5a, 0x50, MASK_VAL(13, 13, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso +E(0x5a, 0x50, MASK_VAL(4, 4, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcblcge +E(0x5a, 0x50, MASK_VAL(14, 14, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcftclkse +E(0x5a, 0x50, MASK_VAL(12, 12, 0x0)), //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe +E(0x5a, 0x50, MASK_VAL(11, 10, 0x3)), //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle +E(SCORE, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten +E(SSUS, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten +E(LPSS, 0x180, MASK_VAL(1, 1, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en +E(LPSS, 0x180, MASK_VAL(4, 4, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(0, 0, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable +E(LPSS, 0x180, MASK_VAL(3, 3, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(5, 5, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(2, 2, 0x1)), //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable + //0x54, 0xfc, 31, 0, 0x0, //vlv.pcu.iosfahbep.clock_gating_control + //0x55, 0xfc, 1, 1, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd + //0x55, 0xfc, 0, 0, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd + //0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd +E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 +E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en +E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en +E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en +E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en +E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en +E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en +E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis +E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis +E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis +E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis +E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis +E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis +E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis +E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis +REG_SCRIPT_END, +}; + + +static void perf_power(void *unused) +{ + printk(BIOS_DEBUG, "Applying perf/power settings.\n"); + reg_script_run(perf_power_settings); +} + +BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), +};
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New patch to review for coreboot: ec3b8fa baytrail: add more iosf access functions
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5007
-gerrit commit ec3b8fad2a5a97723322252578d91c3d905eb479 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 11 17:13:10 2013 -0800 baytrail: add more iosf access functions There's a slew of ports required to initialize baytrail's perf and power values. Therefore, add the necessary functionality in the iosf module as well as the reg_script library. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179748
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/lib/reg_script.c | 68 +++++++++++++++++++ src/soc/intel/baytrail/baytrail/iosf.h | 55 ++++++++++++++- src/soc/intel/baytrail/iosf.c | 120 +++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+), 1 deletion(-) diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 7d03463..1839881 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -249,6 +249,10 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) const struct reg_script *step = reg_script_get_step(ctx); switch (step->id) { + case IOSF_PORT_AUNIT: + return iosf_aunit_read(step->reg); + case IOSF_PORT_CPU_BUS: + return iosf_cpu_bus_read(step->reg); case IOSF_PORT_BUNIT: return iosf_bunit_read(step->reg); case IOSF_PORT_DUNIT_CH0: @@ -257,16 +261,40 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_punit_read(step->reg); case IOSF_PORT_USBPHY: return iosf_usbphy_read(step->reg); + case IOSF_PORT_SEC: + return iosf_sec_read(step->reg); + case IOSF_PORT_0x45: + return iosf_port45_read(step->reg); + case IOSF_PORT_0x46: + return iosf_port46_read(step->reg); + case IOSF_PORT_0x47: + return iosf_port47_read(step->reg); case IOSF_PORT_SCORE: return iosf_score_read(step->reg); + case IOSF_PORT_0x55: + return iosf_port55_read(step->reg); + case IOSF_PORT_0x58: + return iosf_port58_read(step->reg); + case IOSF_PORT_0x59: + return iosf_port59_read(step->reg); + case IOSF_PORT_0x5a: + return iosf_port5a_read(step->reg); case IOSF_PORT_USHPHY: return iosf_ushphy_read(step->reg); case IOSF_PORT_SCC: return iosf_scc_read(step->reg); case IOSF_PORT_LPSS: return iosf_lpss_read(step->reg); + case IOSF_PORT_0xa2: + return iosf_porta2_read(step->reg); case IOSF_PORT_CCU: return iosf_ccu_read(step->reg); + case IOSF_PORT_SSUS: + return iosf_ssus_read(step->reg); + default: + printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", + step->id); + break; } #endif return 0; @@ -278,6 +306,12 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) const struct reg_script *step = reg_script_get_step(ctx); switch (step->id) { + case IOSF_PORT_AUNIT: + iosf_aunit_write(step->reg, step->value); + break; + case IOSF_PORT_CPU_BUS: + iosf_cpu_bus_write(step->reg, step->value); + break; case IOSF_PORT_BUNIT: iosf_bunit_write(step->reg, step->value); break; @@ -290,9 +324,33 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_USBPHY: iosf_usbphy_write(step->reg, step->value); break; + case IOSF_PORT_SEC: + iosf_sec_write(step->reg, step->value); + break; + case IOSF_PORT_0x45: + iosf_port45_write(step->reg, step->value); + break; + case IOSF_PORT_0x46: + iosf_port46_write(step->reg, step->value); + break; + case IOSF_PORT_0x47: + iosf_port47_write(step->reg, step->value); + break; case IOSF_PORT_SCORE: iosf_score_write(step->reg, step->value); break; + case IOSF_PORT_0x55: + iosf_port55_write(step->reg, step->value); + break; + case IOSF_PORT_0x58: + iosf_port58_write(step->reg, step->value); + break; + case IOSF_PORT_0x59: + iosf_port59_write(step->reg, step->value); + break; + case IOSF_PORT_0x5a: + iosf_port5a_write(step->reg, step->value); + break; case IOSF_PORT_USHPHY: iosf_ushphy_write(step->reg, step->value); break; @@ -302,9 +360,19 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_LPSS: iosf_lpss_write(step->reg, step->value); break; + case IOSF_PORT_0xa2: + iosf_porta2_write(step->reg, step->value); + break; case IOSF_PORT_CCU: iosf_ccu_write(step->reg, step->value); break; + case IOSF_PORT_SSUS: + iosf_ssus_write(step->reg, step->value); + break; + default: + printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", + step->id); + break; } #endif } diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index d173901..8cbe67a 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -55,6 +55,10 @@ #define MDR_REG 0xd4 #define MCRX_REG 0xd8 +uint32_t iosf_aunit_read(int reg); +void iosf_aunit_write(int reg, uint32_t val); +uint32_t iosf_cpu_bus_read(int reg); +void iosf_cpu_bus_write(int reg, uint32_t val); uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); uint32_t iosf_dunit_read(int reg); @@ -68,6 +72,22 @@ uint32_t iosf_usbphy_read(int reg); void iosf_usbphy_write(int reg, uint32_t val); uint32_t iosf_ushphy_read(int reg); void iosf_ushphy_write(int reg, uint32_t val); +uint32_t iosf_sec_read(int reg); +void iosf_sec_write(int reg, uint32_t val); +uint32_t iosf_port45_read(int reg); +void iosf_port45_write(int reg, uint32_t val); +uint32_t iosf_port46_read(int reg); +void iosf_port46_write(int reg, uint32_t val); +uint32_t iosf_port47_read(int reg); +void iosf_port47_write(int reg, uint32_t val); +uint32_t iosf_port55_read(int reg); +void iosf_port55_write(int reg, uint32_t val); +uint32_t iosf_port58_read(int reg); +void iosf_port58_write(int reg, uint32_t val); +uint32_t iosf_port59_read(int reg); +void iosf_port59_write(int reg, uint32_t val); +uint32_t iosf_port5a_read(int reg); +void iosf_port5a_write(int reg, uint32_t val); uint32_t iosf_lpss_read(int reg); void iosf_lpss_write(int reg, uint32_t val); uint32_t iosf_ccu_read(int reg); @@ -76,6 +96,10 @@ uint32_t iosf_score_read(int reg); void iosf_score_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_porta2_read(int reg); +void iosf_porta2_write(int reg, uint32_t val); +uint32_t iosf_ssus_read(int reg); +void iosf_ssus_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -88,12 +112,22 @@ void iosf_scc_write(int reg, uint32_t val); #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_SEC 0x44 /* SEC */ +#define IOSF_PORT_0x45 0x45 +#define IOSF_PORT_0x46 0x46 +#define IOSF_PORT_0x47 0x47 #define IOSF_PORT_SCORE 0x48 /* SCORE */ +#define IOSF_PORT_0x55 0x55 +#define IOSF_PORT_0x58 0x58 +#define IOSF_PORT_0x59 0x59 +#define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ +#define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_SSUS 0xa8 /* SUS */ #define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ /* Read and write opcodes differ per port. */ @@ -113,22 +147,41 @@ void iosf_scc_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) #define IOSF_OP_READ_USBPHY 0x06 #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_SEC 0x04 +#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) +#define IOSF_OP_READ_0x45 0x06 +#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) +#define IOSF_OP_READ_0x46 0x06 +#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) +#define IOSF_OP_READ_0x47 0x06 +#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) #define IOSF_OP_READ_SCORE 0x06 #define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) +#define IOSF_OP_READ_0x55 0x04 +#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) +#define IOSF_OP_READ_0x58 0x06 +#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) +#define IOSF_OP_READ_0x59 0x06 +#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) +#define IOSF_OP_READ_0x5a 0x04 +#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) #define IOSF_OP_READ_USHPHY 0x06 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) #define IOSF_OP_READ_SCC 0x06 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) #define IOSF_OP_READ_LPSS 0x06 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) +#define IOSF_OP_READ_0xa2 0x06 +#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) #define IOSF_OP_READ_SATAPHY 0x00 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 #define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) +#define IOSF_OP_READ_SSUS 0x10 +#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) #define IOSF_OP_READ_CCU 0x06 #define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) - /* * BUNIT Registers. */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index c3d4f0e..2b07e2b 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -165,3 +165,123 @@ void iosf_scc_write(int reg, uint32_t val) { return iosf_write_port(IOSF_WRITE(SCC), reg, val); } + +uint32_t iosf_aunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(AUNIT), reg); +} + +void iosf_aunit_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); +} + +uint32_t iosf_cpu_bus_read(int reg) +{ + return iosf_read_port(IOSF_READ(CPU_BUS), reg); +} + +void iosf_cpu_bus_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); +} + +uint32_t iosf_sec_read(int reg) +{ + return iosf_read_port(IOSF_READ(SEC), reg); +} + +void iosf_sec_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SEC), reg, val); +} + +uint32_t iosf_port45_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x45), reg); +} + +void iosf_port45_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x45), reg, val); +} + +uint32_t iosf_port46_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x46), reg); +} + +void iosf_port46_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x46), reg, val); +} + +uint32_t iosf_port47_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x47), reg); +} + +void iosf_port47_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x47), reg, val); +} + +uint32_t iosf_port55_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x55), reg); +} + +void iosf_port55_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x55), reg, val); +} + +uint32_t iosf_port58_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x58), reg); +} + +void iosf_port58_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x58), reg, val); +} + +uint32_t iosf_port59_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x59), reg); +} + +void iosf_port59_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x59), reg, val); +} + +uint32_t iosf_port5a_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x5a), reg); +} + +void iosf_port5a_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x5a), reg, val); +} + +uint32_t iosf_porta2_read(int reg) +{ + return iosf_read_port(IOSF_READ(0xa2), reg); +} + +void iosf_porta2_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0xa2), reg, val); +} + +uint32_t iosf_ssus_read(int reg) +{ + return iosf_read_port(IOSF_READ(SSUS), reg); +} + +void iosf_ssus_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SSUS), reg, val); +}
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New patch to review for coreboot: ddce869 baytrail: remove verbosity in iosf
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5006
-gerrit commit ddce86958730a92714fc4fbfb61bbf2f397834a9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 11 17:10:58 2013 -0800 baytrail: remove verbosity in iosf The iosf access functions already use some common code, however there is a duplication for setting up the proper control register for port and opcode. Introduce macros to remove this verbosity. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179747
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/iosf.c | 77 +++++++++++++------------------------------ 1 file changed, 23 insertions(+), 54 deletions(-) diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 4840dea..c3d4f0e 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -59,25 +59,24 @@ static void iosf_write_port(uint32_t cr, int reg, uint32_t val) write_iosf_reg(MCR_REG, cr); } +#define IOSF_READ(port) \ + IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) +#define IOSF_WRITE(port) \ + IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) + uint32_t iosf_bunit_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(BUNIT), reg); } void iosf_bunit_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT); - iosf_write_port(cr, reg, val); + iosf_write_port(IOSF_WRITE(BUNIT), reg, val); } uint32_t iosf_dunit_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(SYSMEMC), reg); } uint32_t iosf_dunit_ch0_read(int reg) @@ -94,105 +93,75 @@ uint32_t iosf_dunit_ch1_read(int reg) void iosf_dunit_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC); - iosf_write_port(cr, reg, val); + iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); } uint32_t iosf_punit_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) | - IOSF_PORT(IOSF_PORT_PMC); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(PMC), reg); } void iosf_punit_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | - IOSF_PORT(IOSF_PORT_PMC); - iosf_write_port(cr, reg, val); + iosf_write_port(IOSF_WRITE(PMC), reg, val); } uint32_t iosf_usbphy_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(USBPHY), reg); } void iosf_usbphy_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY); - return iosf_write_port(cr, reg, val); + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); } uint32_t iosf_ushphy_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(USHPHY), reg); } void iosf_ushphy_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY); - return iosf_write_port(cr, reg, val); + return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); } uint32_t iosf_lpss_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(LPSS), reg); } void iosf_lpss_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS); - return iosf_write_port(cr, reg, val); + return iosf_write_port(IOSF_WRITE(LPSS), reg, val); } uint32_t iosf_ccu_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_CCU) | - IOSF_PORT(IOSF_PORT_CCU); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(CCU), reg); } void iosf_ccu_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_CCU) | - IOSF_PORT(IOSF_PORT_CCU); - return iosf_write_port(cr, reg, val); + return iosf_write_port(IOSF_WRITE(CCU), reg, val); } uint32_t iosf_score_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SCORE) | - IOSF_PORT(IOSF_PORT_SCORE); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(SCORE), reg); } void iosf_score_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SCORE) | - IOSF_PORT(IOSF_PORT_SCORE); - return iosf_write_port(cr, reg, val); + return iosf_write_port(IOSF_WRITE(SCORE), reg, val); } uint32_t iosf_scc_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SCC) | - IOSF_PORT(IOSF_PORT_SCC); - return iosf_read_port(cr, reg); + return iosf_read_port(IOSF_READ(SCC), reg); } void iosf_scc_write(int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SCC) | - IOSF_PORT(IOSF_PORT_SCC); - return iosf_write_port(cr, reg, val); + return iosf_write_port(IOSF_WRITE(SCC), reg, val); }
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New patch to review for coreboot: 83edd1b reg_script: add reg_script_run_on_dev()
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5005
-gerrit commit 83edd1bb8ce2d406aab7fce0e9a93b9df08e673a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 17:09:40 2013 -0800 reg_script: add reg_script_run_on_dev() The reg_script library has proven to be useful. It's also shown that many scripts operate on devices. However, certain code paths run the same script on multiple, but different, devices. In order to make that easier introduce reg_script_run_on_dev() which takes a device as a parameter. That way, chained reg_scripts are not scrictly needed to run the same script on multiple devices. BUG=None BRANCH=None TEST=Built. Change-Id: I273499af4d303ebd7dc19e9b635ca23cf9bb2225 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179540
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/reg_script.h | 1 + src/lib/reg_script.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 81a4648..72e1e96 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -334,5 +334,6 @@ struct reg_script { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) void reg_script_run(const struct reg_script *script); +void reg_script_run_on_dev(device_t dev, const struct reg_script *step); #endif /* REG_SCRIPT_H */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index a331b14..7d03463 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -468,11 +468,16 @@ static void reg_script_run_next(struct reg_script_context *prev_ctx, reg_script_run_with_context(&ctx); } -void reg_script_run(const struct reg_script *step) +void reg_script_run_on_dev(device_t dev, const struct reg_script *step) { struct reg_script_context ctx; - reg_script_set_dev(&ctx, EMPTY_DEV); + reg_script_set_dev(&ctx, dev); reg_script_set_step(&ctx, step); reg_script_run_with_context(&ctx); } + +void reg_script_run(const struct reg_script *step) +{ + reg_script_run_on_dev(EMPTY_DEV, step); +}
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New patch to review for coreboot: 5d6fc4d baytrail: Add support for LPSS and SCC devices in ACPI mode
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5004
-gerrit commit 5d6fc4dd305db36906e41bd58f4949288579a56a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 10 14:37:42 2013 -0800 baytrail: Add support for LPSS and SCC devices in ACPI mode This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179481
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/acpi/device_nvs.asl | 87 ++++ src/soc/intel/baytrail/acpi/globalnvs.asl | 24 +- src/soc/intel/baytrail/acpi/lpss.asl | 670 +++++++++++++++++++++++++++ src/soc/intel/baytrail/acpi/scc.asl | 187 ++++++++ src/soc/intel/baytrail/acpi/southcluster.asl | 14 +- src/soc/intel/baytrail/baytrail/device_nvs.h | 59 +++ src/soc/intel/baytrail/baytrail/iosf.h | 9 + src/soc/intel/baytrail/baytrail/irq.h | 6 +- src/soc/intel/baytrail/baytrail/nvs.h | 16 +- src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.h | 5 + src/soc/intel/baytrail/emmc.c | 6 + src/soc/intel/baytrail/lpss.c | 58 ++- src/soc/intel/baytrail/scc.c | 43 ++ src/soc/intel/baytrail/sd.c | 5 + src/vendorcode/google/chromeos/gnvs.h | 2 +- 16 files changed, 1153 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl new file mode 100644 index 0000000..fce7b53 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Device Enabled in ACPI Mode */ + +S0EN, 8, // SDMA Enable +S1EN, 8, // I2C1 Enable +S2EN, 8, // I2C2 Enable +S3EN, 8, // I2C3 Enable +S4EN, 8, // I2C4 Enable +S5EN, 8, // I2C5 Enable +S6EN, 8, // I2C6 Enable +S7EN, 8, // I2C7 Enable +S8EN, 8, // SDMA2 Enable +S9EN, 8, // SPI Enable +SAEN, 8, // PWM1 Enable +SBEN, 8, // PWM2 Enable +SCEN, 8, // UART2 Enable +SDEN, 8, // UART2 Enable +C0EN, 8, // MMC Enable +C1EN, 8, // SDIO Enable +C2EN, 8, // SD Card Enable +LPEN, 8, // LPE Enable + +/* BAR 0 */ + +S0B0, 32, // SDMA BAR0 +S1B0, 32, // I2C1 BAR0 +S2B0, 32, // I2C2 BAR0 +S3B0, 32, // I2C3 BAR0 +S4B0, 32, // I2C4 BAR0 +S5B0, 32, // I2C5 BAR0 +S6B0, 32, // I2C6 BAR0 +S7B0, 32, // I2C7 BAR0 +S8B0, 32, // SDMA2 BAR0 +S9B0, 32, // SPI BAR0 +SAB0, 32, // PWM1 BAR0 +SBB0, 32, // PWM2 BAR0 +SCB0, 32, // UART1 BAR0 +SDB0, 32, // UART2 BAR0 +C0B0, 32, // MMC BAR0 +C1B0, 32, // SDIO BAR0 +C2B0, 32, // SD Card BAR0 +LPB0, 32, // LPE BAR0 + +/* BAR 1 */ + +S0B1, 32, // SDMA BAR1 +S1B1, 32, // I2C1 BAR1 +S2B1, 32, // I2C2 BAR1 +S3B1, 32, // I2C3 BAR1 +S4B1, 32, // I2C4 BAR1 +S5B1, 32, // I2C5 BAR1 +S6B1, 32, // I2C6 BAR1 +S7B1, 32, // I2C7 BAR1 +S8B1, 32, // SDMA2 BAR1 +S9B1, 32, // SPI BAR1 +SAB1, 32, // PWM1 BAR1 +SBB1, 32, // PWM2 BAR1 +SCB1, 32, // UART1 BAR1 +SDB1, 32, // UART2 BAR1 +C0B1, 32, // MMC BAR1 +C1B1, 32, // SDIO BAR1 +C2B1, 32, // SD Card BAR1 +LPB1, 32, // LPE BAR1 + +/* Extra */ + +LPFW, 32, // LPE BAR2 Firmware diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index cd00824..b384cea 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -30,7 +30,7 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00) +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -70,28 +70,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TOLM, 32, // 0x34 - Top of Low Memory CBMC, 32, // 0x38 - coreboot mem console pointer - /* Serial IO device BARs */ - Offset (0x60), - S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0 - S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0 - S2B0, 32, // 0x68 - D21:F2 Serial IO I2C1 BAR0 - S3B0, 32, // 0x6c - D21:F3 Serial IO SPI0 BAR0 - S4B0, 32, // 0x70 - D21:F4 Serial IO SPI1 BAR0 - S5B0, 32, // 0x74 - D21:F5 Serial IO UAR0 BAR0 - S6B0, 32, // 0x78 - D21:F6 Serial IO UAR1 BAR0 - S7B0, 32, // 0x7c - D23:F0 Serial IO SDIO BAR0 - S0B1, 32, // 0x80 - D21:F0 Serial IO SDMA BAR1 - S1B1, 32, // 0x84 - D21:F1 Serial IO I2C0 BAR1 - S2B1, 32, // 0x88 - D21:F2 Serial IO I2C1 BAR1 - S3B1, 32, // 0x8c - D21:F3 Serial IO SPI0 BAR1 - S4B1, 32, // 0x90 - D21:F4 Serial IO SPI1 BAR1 - S5B1, 32, // 0x94 - D21:F5 Serial IO UAR0 BAR1 - S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1 - S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1 - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> + + Offset (0x1000), + #include <soc/intel/baytrail/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl new file mode 100644 index 0000000..f56c6a8 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -0,0 +1,670 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (SDM1) +{ + Name (_HID, "INTL9C60") + Name (_UID, 1) + Name (_DDN, "DMA Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA1_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (SDM2) +{ + Name (_HID, "INTL9C60") + Name (_UID, 2) + Name (_DDN, "DMA Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA2_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S8B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S8EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (I2C1) +{ + Name (_HID, "80860F41") + Name (_UID, 1) + Name (_DDN, "I2C Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C1_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C2) +{ + Name (_HID, "80860F41") + Name (_UID, 2) + Name (_DDN, "I2C Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C2_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C3) +{ + Name (_HID, "80860F41") + Name (_UID, 3) + Name (_DDN, "I2C Controller #3") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C3_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S3B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S3EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S3B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C4) +{ + Name (_HID, "80860F41") + Name (_UID, 4) + Name (_DDN, "I2C Controller #4") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C4_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S4B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S4EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S4B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C5) +{ + Name (_HID, "80860F41") + Name (_UID, 5) + Name (_DDN, "I2C Controller #5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C5_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S5B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S5B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C6) +{ + Name (_HID, "80860F41") + Name (_UID, 6) + Name (_DDN, "I2C Controller #6") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C6_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S6B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S6B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C7) +{ + Name (_HID, "80860F41") + Name (_UID, 7) + Name (_DDN, "I2C Controller #7") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C7_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S7B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S7EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S7B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SPI1) +{ + Name (_HID, "80860F0E") + Name (_UID, 1) + Name (_DDN, "SPI Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_SPI_IRQ + } + FixedDMA (0x0, 0x0, Width32Bit, ) + FixedDMA (0x1, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S9B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S9EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S9B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (PWM1) +{ + Name (_HID, "80860F09") + Name (_UID, 1) + Name (_DDN, "PWM Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SAB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SAEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (PWM2) +{ + Name (_HID, "80860F09") + Name (_UID, 2) + Name (_DDN, "PWM Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SBB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SBEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (UAR1) +{ + Name (_HID, "80860F0A") + Name (_UID, 1) + Name (_DDN, "HS-UART Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART1_IRQ + } + FixedDMA (0x2, 0x2, Width32Bit, ) + FixedDMA (0x3, 0x3, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SCB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SCEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SCB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (UAR2) +{ + Name (_HID, "80860F0A") + Name (_UID, 2) + Name (_DDN, "HS-UART Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART2_IRQ + } + FixedDMA (0x4, 0x4, Width32Bit, ) + FixedDMA (0x5, 0x5, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SDB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SDEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SDB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/baytrail/acpi/scc.asl b/src/soc/intel/baytrail/acpi/scc.asl new file mode 100644 index 0000000..7181fb1 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/scc.asl @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (EMMC) +{ + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_UID, 1) + Name (_DDN, "eMMC Controller 4.5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_EMMC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C0B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Device (EM45) + { + /* Slot 0, Function 8 */ + Name (_ADR, 0x8) + + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device (SDIO) +{ + Name (_HID, "INT33BB") + Name (_CID, "PNP0D40") + Name (_UID, 2) + Name (_DDN, "SDIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SDIO_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SDCD) +{ + Name (_HID, "80860F16") + Name (_CID, "PNP0D40") + Name (_UID, 3) + Name (_DDN, "SD Card Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SD_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 49349c4..cf27a24 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -20,6 +20,7 @@ */ #include <soc/intel/baytrail/baytrail/iomap.h> +#include <soc/intel/baytrail/baytrail/irq.h> Scope(\) { @@ -233,5 +234,14 @@ Method (_OSC, 4) // IRQ routing for each PCI device #include "irqroute.asl" -// GPIO Devices -#include "gpio.asl" +Scope (\_SB) +{ + // GPIO Devices + #include "gpio.asl" + + // LPSS Devices + #include "lpss.asl" + + // SCC Devices + #include "scc.asl" +} diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h new file mode 100644 index 0000000..dcb05d2 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +#define LPSS_NVS_SIO_DMA1 0 +#define LPSS_NVS_I2C1 1 +#define LPSS_NVS_I2C2 2 +#define LPSS_NVS_I2C3 3 +#define LPSS_NVS_I2C4 4 +#define LPSS_NVS_I2C5 5 +#define LPSS_NVS_I2C6 6 +#define LPSS_NVS_I2C7 7 +#define LPSS_NVS_SIO_DMA2 8 +#define LPSS_NVS_SPI 9 +#define LPSS_NVS_PWM1 10 +#define LPSS_NVS_PWM2 11 +#define LPSS_NVS_HSUART1 12 +#define LPSS_NVS_HSUART2 13 + +#define SCC_NVS_MMC 0 +#define SCC_NVS_SDIO 1 +#define SCC_NVS_SD 2 + +typedef struct { + /* Device Enabled in ACPI Mode */ + u8 lpss_en[14]; + u8 scc_en[3]; + u8 lpe_en; + + /* BAR 0 */ + u32 lpss_bar0[14]; + u32 scc_bar0[3]; + u32 lpe_bar0; + + /* BAR 0 */ + u32 lpss_bar1[14]; + u32 scc_bar1[3]; + u32 lpe_bar1; + + /* Extra */ + u32 lpe_fw; /* LPE Firmware */ +} __attribute__((packed)) device_nvs_t; diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 3a63d4a..d173901 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -211,6 +211,15 @@ void iosf_scc_write(int reg, uint32_t val); # define LPSS_CTL_PM_CAP_PRSNT (1 << 1) /* + * SCC Registers + */ +#define SCC_SD_CTL 0x504 +#define SCC_SDIO_CTL 0x508 +#define SCC_MMC_CTL 0x50c +# define SCC_CTL_PCI_CFG_DIS (1 << 0) +# define SCC_CTL_ACPI_INT_EN (1 << 1) + +/* * CCU Registers */ diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index deffad7..e66fab5 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -45,9 +45,9 @@ #define LPSS_HSUART1_IRQ 39 #define LPSS_HSUART2_IRQ 40 #define LPSS_SPI_IRQ 41 -#define LPSS_DMA2_IRQ 42 -#define LPSS_DMA1_IRQ 43 -#define SCC_EMMC_IRQ 45 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 #define SCC_SDIO_IRQ 46 #define SCC_SD_IRQ 47 #define GPIO_NC_IRQ 48 diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index 7cabaaa..e8849b9 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> +#include <baytrail/device_nvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -55,15 +57,13 @@ typedef struct { u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd5[36]; - - /* Serial IO device BARs */ - u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ - u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ - u8 rsvd6[96]; + u8 rsvd3[196]; - /* ChromeOS specific (starts at 0x100)*/ + /* ChromeOS specific (0x100-0xfff)*/ chromeos_acpi_t chromeos; + + /* Baytrail LPSS (0x1000) */ + device_nvs_t dev; } __attribute__((packed)) global_nvs_t; #ifdef __SMM__ diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index 217c67b..d2e7e62 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -34,6 +34,7 @@ void baytrail_run_reference_code(void); static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 2cc3fd6..955ecb0 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -56,6 +56,11 @@ struct soc_intel_baytrail_config { uint32_t sdcard_cap_low; uint32_t sdcard_cap_high; + /* Enable devices in ACPI mode */ + int lpss_acpi_mode; + int scc_acpi_mode; + int lpe_acpi_mode; + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 18c16e8..0a7e9b1 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -26,8 +26,10 @@ #include <reg_script.h> #include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include "chip.h" static const struct reg_script emmc_ops[] = { /* Enable 2ms card stable feature. */ @@ -49,6 +51,7 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(device_t dev) { + struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ops[] = { REG_SCRIPT_SET_DEV(dev), REG_SCRIPT_NEXT(emmc_ops), @@ -56,6 +59,9 @@ static void emmc_init(device_t dev) }; printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run(ops); + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index ccfab38..e009c7d 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -26,9 +27,49 @@ #include <reg_script.h> #include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include "chip.h" + +static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, + LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpss_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run(ops); +} static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { @@ -43,12 +84,14 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run(ops); } -static int dev_ctl_reg(device_t dev) +static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) { - int iosf_reg = -1; + *iosf_reg = -1; + *nvs_index = -1; #define SET_IOSF_REG(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - iosf_reg = LPSS_ ## name_ ## _CTL + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_ switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); @@ -80,7 +123,6 @@ static int dev_ctl_reg(device_t dev) SET_IOSF_REG(SPI); break; } - return iosf_reg; } static void i2c_disable_resets(device_t dev) @@ -113,7 +155,10 @@ static void i2c_disable_resets(device_t dev) static void lpss_init(device_t dev) { - int iosf_reg = dev_ctl_reg(dev); + struct soc_intel_baytrail_config *config = dev->chip_info; + int iosf_reg, nvs_index; + + dev_ctl_reg(dev, &iosf_reg, &nvs_index); if (iosf_reg < 0) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -124,6 +169,9 @@ static void lpss_init(device_t dev) } dev_enable_snoop_and_pm(dev, iosf_reg); + if (config->lpss_acpi_mode) + dev_enable_acpi_mode(dev, iosf_reg, nvs_index); + i2c_disable_resets(dev); } diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index af941fa..64792c2 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -18,10 +18,15 @@ */ +#include <cbmem.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> #include <reg_script.h> #include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/ramstage.h> static const struct reg_script scc_start_dll[] = { @@ -81,3 +86,41 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } + +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, + SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.scc_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run(ops); +} diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 82833c3..97c8628 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -24,6 +24,8 @@ #include <device/pci_ids.h> #include <reg_script.h> +#include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> #include "chip.h" @@ -46,6 +48,9 @@ static void sd_init(device_t dev) pci_write_config32(dev, CAP_OVERRIDE_HIGH, config->sdcard_cap_high | USE_CAP_OVERRIDES); } + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); } static const struct device_operations device_ops = { diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 00fe443..123b2cc 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -58,7 +58,7 @@ typedef struct { u8 vdat[3072]; // 19a u32 vbt10; // d9a smbios bios version u32 mehh[8]; // d9e management engine hash - // dbe + u8 pad[322]; // dbe-eff } __attribute__((packed)) chromeos_acpi_t; extern chromeos_acpi_t *vboot_data;
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New patch to review for coreboot: b2d65ba rambi: Enable DPTF
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5003
-gerrit commit b2d65bad854a29444f4184e7202c34d1fb32cf1c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 10 07:48:00 2013 -0800 rambi: Enable DPTF This enables the DPTF framework, but it doesn't do much without some sort of kernel+user components to drive it. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179480
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/acpi/dptf.asl | 28 +++++++++++++++++++++++++ src/mainboard/google/rambi/acpi_tables.c | 8 ++++++++ src/mainboard/google/rambi/dsdt.asl | 3 +++ src/mainboard/google/rambi/thermal.h | 35 +++++--------------------------- 4 files changed, 44 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl new file mode 100644 index 0000000..0d5cd65 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -0,0 +1,28 @@ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0}, + + /* CPU and Charger Effect on Temp Sensor 0 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 80, 300, 0, 0, 0, 0 }, + + /* CPU and Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 80, 300, 0, 0, 0, 0 }, + + /* CPU and Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 80, 300, 0, 0, 0, 0 }, +}) + +/* Include Baytrail DPTF */ +#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index a4754f1..1d96dec 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -36,6 +36,8 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> +#include "thermal.h" + extern const unsigned char AmlCode[]; static void acpi_create_gnvs(global_nvs_t *gnvs) @@ -59,6 +61,12 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; + /* Enable DPTF */ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tact = ACTIVE_TEMPERATURE; + gnvs->dpte = 1; + #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 1fbb8eb..53f2922 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -46,6 +46,9 @@ DefinitionBlock( //#include <soc/intel/baytrail/acpi/northcluster.asl> #include <soc/intel/baytrail/acpi/southcluster.asl> } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" } #include "acpi/chromeos.asl" diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h index f771014..2432b8d 100644 --- a/src/mainboard/google/rambi/thermal.h +++ b/src/mainboard/google/rambi/thermal.h @@ -20,38 +20,13 @@ #ifndef BAYLEYBAY_THERMAL_H #define BAYLEYBAY_THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 -#define FAN0_PWM 0xff - /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 +#define CRITICAL_TEMPERATURE 95 -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +/* Passive cooling policy threshold */ +#define PASSIVE_TEMPERATURE 0 -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 +/* Temperature which OS will throttle CPU (when using a Fan) */ +#define ACTIVE_TEMPERATURE 80 #endif
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New patch to review for coreboot: 245bd83 baytrail: Basic DPTF framework
by Aaron Durbin
28 Jan '14
28 Jan '14
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/5002
-gerrit commit 245bd837baafa4848a7de3e0cda37d4dd98ea387 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 10 07:41:33 2013 -0800 baytrail: Basic DPTF framework This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on:
https://chromium-review.googlesource.com/179459
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/acpi/ec.asl | 71 +++++++++++ src/soc/intel/baytrail/acpi.c | 4 +- src/soc/intel/baytrail/acpi/dptf/charger.asl | 36 ++++++ src/soc/intel/baytrail/acpi/dptf/cpu.asl | 180 +++++++++++++++++++++++++++ src/soc/intel/baytrail/acpi/dptf/dptf.asl | 51 ++++++++ src/soc/intel/baytrail/acpi/dptf/thermal.asl | 116 +++++++++++++++++ src/soc/intel/baytrail/acpi/globalnvs.asl | 5 + src/soc/intel/baytrail/baytrail/nvs.h | 9 +- 8 files changed, 468 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 31ef905..d0540ed 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -25,6 +25,7 @@ // Mainboard specific throttle handler External (\_TZ.THRT, MethodObj) +External (\_SB.DPTF.TEVT, MethodObj) Device (EC0) { @@ -47,6 +48,7 @@ Device (EC0) TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte KBLV, 8, // Keyboard Backlight + FAND, 8, // Set Fan Duty Cycle } OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) @@ -89,6 +91,8 @@ Device (EC0) BMOD, 64, // Battery Model String BSER, 64, // Battery Serial String BTYP, 64, // Battery Type String + Offset (0x80), + ALS0, 16, // ALS reading 0 in lux } Method (TINS, 1, Serialized) @@ -134,6 +138,40 @@ Device (EC0) Store (LIDS, \LIDS) } + /* Read requested temperature and check against EC error values */ + Method (TSRD, 1, Serialized) + { + Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0) + + /* Check for sensor not calibrated */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (Zero) + } + + /* Check for sensor not present */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (Zero) + } + + /* Check for sensor not powered */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (Zero) + } + + /* Check for sensor bad reading */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (Zero) + } + + /* Adjust by offset to get Kelvin */ + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + /* Convert to 1/10 Kelvin */ + Multiply (Local0, 10, Local0) + + Return (Local0) + } + // Lid Closed Event Method (_Q01, 0, NotSerialized) { @@ -247,6 +285,39 @@ Device (EC0) } } + /* + * Dynamic Platform Thermal Framework support + */ + + /* + * Set Aux Trip Point 0 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT0, 2, Serialized) + { + } + + /* + * Set Aux Trip Point 1 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT1, 2, Serialized) + { + } + + /* + * DPTF Thermal Threshold Event + */ + Method (_Q14, 0, Serialized) + { + Store ("EC: DPTF THERMAL THRESHOLD", Debug) + If (CondRefOf (\_SB.DPTF.TEVT, Local0)) { + \_SB.DPTF.TEVT () + } + } + #include "ac.asl" #include "battery.asl" } diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index fff63e1..89ab929 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -338,8 +338,8 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Write _PCT indicating use of FFixedHW */ len = acpigen_write_empty_PCT(); - /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC(0); + /* Write _PPC with NVS specified limit on supported P-state */ + len += acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ len += acpigen_write_PSD_package(core, 1, coord_type); diff --git a/src/soc/intel/baytrail/acpi/dptf/charger.asl b/src/soc/intel/baytrail/acpi/dptf/charger.asl new file mode 100644 index 0000000..7560f13 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/charger.asl @@ -0,0 +1,36 @@ +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (PPSS, Package () + { + Package () { 0, 0, 0, 0, 0, 0x880, "mA", 0 }, /* 2.1A */ + Package () { 0, 0, 0, 0, 1, 0x800, "mA", 0 }, /* 2.0A */ + Package () { 0, 0, 0, 0, 2, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 3, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 4, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 5, 0x000, "mA", 0 }, /* 0.0A */ + }) + + Method (PPPC) + { + Return (0) + } + + Method (SPPC, 1, Serialized) + { + /* TODO: Tell EC to limit battery charging */ + } +} diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl new file mode 100644 index 0000000..6e6c792 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -0,0 +1,180 @@ +External (\_PR.CPU0._TSS, MethodObj) +External (\_PR.CPU0._TPC, MethodObj) +External (\_PR.CPU0._PTC, PkgObj) +External (\_PR.CPU0._TSD, PkgObj) +External (\_PR.CPU0._PPC, MethodObj) +External (\_PR.CPU0._PSS, MethodObj) + +Device (TCPU) +{ + Name (_HID, EISAID ("INT3401")) + Name (_UID, 0) + Name (CTYP, 0) /* Passive Cooling by default */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CPU0._TSS)) { + Return (\_PR.CPU0._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CPU0._TPC)) { + Return (\_PR.CPU0._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CPU0._PTC)) { + Return (\_PR.CPU0._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CPU0._TSD)) { + Return (\_PR.CPU0._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CPU0._TSS)) { + Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + If (CondRefOf (\_PR.CPU0._PPC)) { + Return (\_PR.CPU0._PPC) + } Else { + Return (0) + } + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CPU0._PSS)) { + Return (\_PR.CPU0._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + Method (_PDL) + { + If (CondRefOf (\_PR.CPU0._PSS)) { + Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * DPTF + */ + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Critical temperature from NVS */ + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + /* Hot temperature is 3 less than critical temperature */ + Method (_HOT, 0, Serialized) + { + Return (CTOK (Subtract (\TCRT, 3))) + } + + Method (_PSV, 0, Serialized) + { + If (CTYP) { + Return (CTOK (\TACT)) + } Else { + Return (CTOK (\TPSV)) + } + } + + /* Set Cooling Policy + * Arg0 - Cooling policy mode, 1=active, 0=passive + * Arg1 - Acoustic Limit + * Arg2 - Power Limit + */ + Method (_SCP, 3, Serialized) + { + If (LEqual (Arg0, 0)) { + Store (0, CTYP) + } Else { + Store (1, CTYP) + } + + /* DPTF Thermal Trip Points Changed Event */ + Notify (TCPU, 0x91) + } +} diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl new file mode 100644 index 0000000..b636886 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl @@ -0,0 +1,51 @@ +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_OSC, 4, Serialized) + { + /* TODO: Enable/Disable EC control of thermals/charging */ + Return (Arg3) + } + + Method (_TRT) + { + Return (\_SB.DTRT) + } + + /* Thermal Threshold Event Handler */ + Method (TEVT, 0, Serialized) + { + } + + /* Include CPU Participant */ + #include "cpu.asl" + + /* Include Thermal Participants */ + #include "thermal.asl" + + /* Include Charger Participant */ + #include "charger.asl" +} diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl new file mode 100644 index 0000000..2a77e6a --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -0,0 +1,116 @@ +#ifdef DPTF_TSR0_SENSOR_ID +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } +} +#endif diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 2f614a9..cd00824 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -51,6 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PCNT, 8, // 0x11 - Processor count TPMP, 8, // 0x12 - TPM Present and Enabled TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS /* Device Config */ Offset (0x20), @@ -58,6 +59,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S5U1, 8, // 0x21 - Enable USB1 in S5 S3U0, 8, // 0x22 - Enable USB0 in S3 S3U1, 8, // 0x23 - Enable USB1 in S3 + TACT, 8, // 0x24 - Thermal Active trip point + TPSV, 8, // 0x25 - Thermal Passive trip point + TCRT, 8, // 0x26 - Thermal Critical trip point + DPTE, 8, // 0x27 - Enable DPTF /* Base addresses */ Offset (0x30), diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index ae1f099..7cabaaa 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -37,14 +37,19 @@ typedef struct { u8 pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ - u8 rsvd1[12]; + u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ + u8 rsvd1[11]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ u8 s5u1; /* 0x21 - Enable USB1 in S5 */ u8 s3u0; /* 0x22 - Enable USB0 in S3 */ u8 s3u1; /* 0x23 - Enable USB1 in S3 */ - u8 rsvd2[12]; + u8 tact; /* 0x24 - Thermal Active trip point */ + u8 tpsv; /* 0x25 - Thermal Passive trip point */ + u8 tcrt; /* 0x26 - Thermal Critical trip point */ + u8 dpte; /* 0x27 - Enable DPTF */ + u8 rsvd2[8]; /* Base Addresses */ u32 cmem; /* 0x30 - CBMEM TOC */
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