Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4976
-gerrit
commit 2cb99f0b27ec5c00f94782850965cf1c6c200168
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Nov 18 11:16:20 2013 -0600
baytrail: enable caching and prefetching in spi controller
The default mode of the SPI controller has prefetching disabled.
That obviously has a performance impact. Enable both caching
and prefetching to make booting faster. This has a significant
impact on streaming data out of SPI.
BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted rambi. Payload loading step went from ~285ms
to ~54ms.
Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177220
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/baytrail/baytrail/spi.h | 31 ++++++++++++++++++++++++++++++
src/soc/intel/baytrail/romstage/romstage.c | 10 ++++++++++
2 files changed, 41 insertions(+)
diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/baytrail/spi.h
new file mode 100644
index 0000000..abe9e14
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/spi.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_SPI_H_
+#define _BAYTRAIL_SPI_H_
+
+/* These registers live behind SPI_BASE_ADDRESS. */
+#define BCR 0xfc
+# define SRC_MASK (0x3 << 2)
+# define SRC_CACHE_NO_PREFETCH (0x0 << 2)
+# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2)
+# define SRC_CACHE_PREFETCH (0x2 << 2)
+
+#endif /* _BAYTRAIL_SPI_H_ */
+
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 0416a52..2cc70ae 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -42,6 +42,7 @@
#include <baytrail/reset.h>
#include <baytrail/romstage.h>
#include <baytrail/smm.h>
+#include <baytrail/spi.h>
static inline uint64_t timestamp_get(void)
{
@@ -95,6 +96,13 @@ static void program_base_addresses(void)
pci_write_config32(lpc_dev, GBASE, reg);
}
+static void spi_init(void)
+{
+ const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
+ /* Enable caching and prefetching in the SPI controller. */
+ write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
+}
+
static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
{
struct romstage_timestamps *rt = &rp->ts;
@@ -125,6 +133,8 @@ void * asmlinkage romstage_main(unsigned long bist,
console_init();
+ spi_init();
+
set_max_freq();
punit_init();
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4974
-gerrit
commit d042bb003900a757c57d2de0a23e0e17bc4a4785
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 14 13:47:08 2013 -0600
baytrail: ensure init_chromeos() is called in romstage
The TPM needs to have the TPM_Startup command sent to it
on all boot paths. The call init_chromeos() in romstage_common()
fulfills this requirement.
BUG=chrome-os-partner:24057
BRANCH=None
TEST=Built and booted. Was able to suspend to ram multiple times
in a row.
Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176803
Reviewed-by: Todd Broch <tbroch(a)chromium.org>
Tested-by: Todd Broch <tbroch(a)chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/baytrail/romstage/romstage.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 19a7153..0416a52 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -181,6 +181,16 @@ static int chipset_prev_sleep_state(void)
return prev_sleep_state;
}
+#if CONFIG_CHROMEOS
+static inline void chromeos_init(int prev_sleep_state)
+{
+ /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */
+ init_chromeos(prev_sleep_state == 3 ? 2 : 0);
+}
+#else
+static inline void chromeos_init(int prev_sleep_state) {}
+#endif
+
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
@@ -208,6 +218,8 @@ void romstage_common(struct romstage_params *params)
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+ chromeos_init(prev_sleep_state);
+
/* Save timestamp information. */
timestamp_init(ts64_to_tsc(params->ts.times[0]));
timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4973
-gerrit
commit 894b8720468006eba7c8c3f84a0888017e2bfc0a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 14 11:15:43 2013 -0600
rambi: distribute IRQs away from PIRQA on pci devices
Some of the drivers in the kernel were not so happy about
having shared IRQs. Also, sharing IRQs means more code
needs to be run in interrupt context to determine if the IRQ
was meant for a particular device. Fix this.
No more 'mmc1: got irq while runtime suspended' messages.
BUG=chrome-os-partner:24056
BRANCH=None
TEST=Built and booted. Looked at /proc/interrupts and noted no
more sharing between pci devices.
Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176792
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/rambi/irqroute.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index fa7a6c3..eaafff9 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -23,17 +23,17 @@
#define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SD_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(MMC_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
- PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
#define PIRQ_PIC_ROUTES \
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4972
-gerrit
commit 3f86b0347a479500596d78772ec9d5183edc304f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 14 11:06:17 2013 -0600
baytrail: don't allow PCIE wake ups
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.
BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
cause wakeups.
Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/baytrail/smm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index c654c85..e10c70b 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events */
- enable_pm1(PWRBTN_EN | GBL_EN);
+ /* Configure events Disable pcie wake. */
+ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */