Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4950
-gerrit
commit 71612c09a63aae1ddea589e59ad01a7c602e24cf
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 7 08:13:58 2013 -0600
rambi: include the EC devices normally on superio
The superio.asl file allows for the mainboard to hang
devices off of the LPC bus in ACPI. Include the keyboard
controller, EC memory map, and host interface's resources.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted resource reservations in dmesg.
Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176134
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/rambi/acpi/superio.asl | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl
index 9092a6c..f40611c 100644
--- a/src/mainboard/google/rambi/acpi/superio.asl
+++ b/src/mainboard/google/rambi/acpi/superio.asl
@@ -17,4 +17,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* Values should match those defined in devicetree.cb */
+/* mainboard configuration */
+#include <mainboard/google/rambi/ec.h>
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4949
-gerrit
commit 90c190b356a82bd54023830e5211b8c4d083130f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 7 14:33:21 2013 -0600
baytrail: include mainboard's superio.asl
The mainboard needs an opportunity to hang devices off of
the LPC device. Therefore, provide this opportunity for the
mainboard.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Buit and booted with keyboard. Keys work.
Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176133
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/acpi/lpc.asl | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 24fa9c7..408d2b4 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -138,6 +138,9 @@ Device (LPCB)
})
}
+ // Include mainboard's superio.asl file.
+ #include "acpi/superio.asl"
+
#ifdef ENABLE_TPM
Device (TPM) // Trusted Platform Module
{
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4942
-gerrit
commit 96f9c9f27a7d1f37b3cc0540ed73b3b385cd1569
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 5 17:07:44 2013 -0600
libpayload: adjust max number of memranges
Rambi currently has more than 16 memory ranges. Because of
this libpayload is silently dropping them and the full amount
of memory is not being properly wiped. Correct this by bumping
the number of ranges to 32.
BUG=None
BRANCH=None
TEST=Built and booted rambi. Noted that the full amount of memory
was being properly wiped.
Change-Id: Ida456decf2498cb1547c0ceef23df446a975606b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175792
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
payloads/libpayload/include/sysinfo.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index fd60dc3..a66c1e7 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -30,8 +30,8 @@
#ifndef _SYSINFO_H
#define _SYSINFO_H
-/* Allow a maximum of 16 memory range definitions. */
-#define SYSINFO_MAX_MEM_RANGES 16
+/* Maximum number of memory range definitions. */
+#define SYSINFO_MAX_MEM_RANGES 32
/* Allow a maximum of 8 GPIOs */
#define SYSINFO_MAX_GPIOS 8