Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5020
-gerrit
commit 979cb019a04e2cc3f9a00e51f1c1123a202de1a3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Dec 13 16:01:56 2013 -0800
rambi: Disable HSUART2 and SPI interfaces
Not used currently on rambi board. Disable in case it
saves power.
BUG=chrome-os-partner:23862
BRANCH=none
TEST=build and boot on rambi
Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180084
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index bfb9e30..fe5ec7b 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -75,8 +75,8 @@ chip soc/intel/baytrail
device pci 1e.1 off end # PWM1
device pci 1e.2 off end # PWM2
device pci 1e.3 off end # HSUART1
- device pci 1e.4 on end # HSUART2
- device pci 1e.5 on end # SPI
+ device pci 1e.4 off end # HSUART2
+ device pci 1e.5 off end # SPI
device pci 1f.0 on
chip ec/google/chromeec
# We only have one init function that
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5014
-gerrit
commit c7193c5a0044bda4a6a862a9cbdf4251e89772dd
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Dec 12 10:42:31 2013 -0800
baytrail: Add header include wrapper and offset define
Since this file will get added to payloads it is useful if it
exports what offset in NVS it lives.
BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode
Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179848
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/baytrail/device_nvs.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h
index dcb05d2..f8f831b 100644
--- a/src/soc/intel/baytrail/baytrail/device_nvs.h
+++ b/src/soc/intel/baytrail/baytrail/device_nvs.h
@@ -17,8 +17,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef _BAYTRAIL_DEVICE_NVS_H_
+#define _BAYTRAIL_DEVICE_NVS_H_
+
#include <stdint.h>
+/* Offset in Global NVS where this structure lives */
+#define DEVICE_NVS_OFFSET 0x1000
+
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
@@ -57,3 +63,5 @@ typedef struct {
/* Extra */
u32 lpe_fw; /* LPE Firmware */
} __attribute__((packed)) device_nvs_t;
+
+#endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5012
-gerrit
commit 9fe9ccb64069faa7d02c04fd72f121b7aad8747f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Dec 12 10:27:11 2013 -0800
baytrail: allow ramstage_cache_location() usage in ramstage
To prepare for caching reference code for S3 resume the
ramstage cache needs to be accesible in ramstage as well.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179776
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 2 ++
src/soc/intel/baytrail/romstage/romstage.c | 14 ------------
src/soc/intel/baytrail/stage_cache.c | 35 ++++++++++++++++++++++++++++++
3 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index f601c7e..eafa65f 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -45,6 +45,8 @@ ramstage-y += lpss.c
ramstage-y += pcie.c
ramstage-y += sd.c
ramstage-y += perf_power.c
+ramstage-y += stage_cache.c
+romstage-y += stage_cache.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 2cc70ae..8f1f395 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -30,7 +30,6 @@
#endif
#include <elog.h>
#include <ramstage_cache.h>
-#include <ramstage_cache.h>
#include <romstage_handoff.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -359,19 +358,6 @@ static void *setup_stack_and_mttrs(void)
return slot;
}
-struct ramstage_cache *ramstage_cache_location(long *size)
-{
- char *smm_base;
- /* 1MiB cache size */
- const long cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- /* Ramstage cache lives in TSEG region which is the definition of
- * cbmem_top(). */
- smm_base = cbmem_top();
- *size = cache_size;
- return (void *)&smm_base[smm_region_size() - cache_size];
-}
-
void ramstage_cache_invalid(struct ramstage_cache *cache)
{
#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c
new file mode 100644
index 0000000..3bda56d
--- /dev/null
+++ b/src/soc/intel/baytrail/stage_cache.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <ramstage_cache.h>
+#include <baytrail/smm.h>
+
+struct ramstage_cache *ramstage_cache_location(long *size)
+{
+ char *smm_base;
+ /* 1MiB cache size */
+ const long cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+ /* Ramstage cache lives in TSEG region which is the definition of
+ * cbmem_top(). */
+ smm_base = cbmem_top();
+ *size = cache_size;
+ return (void *)&smm_base[smm_region_size() - cache_size];
+}