Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5050
-gerrit
commit 5a7783a4fa799c39814710fe9aad5f6b7caf2331
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Jan 15 11:59:10 2014 -0600
baytrail: enable graphics turbo
Though the limited documentation indicates the default is
0 for the gfx_turbo_disable bit, in practice that isn't
true. Knock down the gfs_turbo_disable bit to enable
graphics turbo mode.
BUG=chrome-os-partner:25044
BRANCH=baytrail
TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG.
Noted that bit 7 was set to 0.
Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182640
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/gfx.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 37fdc70..3c779e1 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -212,6 +212,10 @@ static const struct reg_script gfx_init_script[] = {
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0),
+
+ /* Enable Gfx Turbo. */
+ REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG,
+ ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0),
REG_SCRIPT_END
};
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5048
-gerrit
commit fab328c58e508f2206875016d5cf0bc9e9f8915d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jan 14 17:34:10 2014 -0600
baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
On baytrail, it appears that the turbo disable setting is
actually building-block scoped. One can see this on quad
core parts where if enable_turbo() is called only on the
BSP then only cpus 0 and 1 have turbo enabled. Fix this
by calling enable_turbo() on all non-bsp cpus.
BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and booted rambi. All cpus have bit 38 set to 0
in msr 0x1a0.
Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182406
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Kconfig | 1 +
src/soc/intel/baytrail/cpu.c | 9 ++++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index a17852d..5aacbdc 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select CAR_MIGRATION
select COLLECT_TIMESTAMPS
select CPU_MICROCODE_IN_CBFS
+ select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select DYNAMIC_CBMEM
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index cf32c54..aff6c55 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -92,7 +92,7 @@ void baytrail_init_cpus(device_t dev)
/* Set package MSRs */
reg_script_run(package_msr_script);
- /* Enable Turbo/Burst Mode */
+ /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */
enable_turbo();
if (mp_init(cpu_bus, &mp_params)) {
@@ -104,6 +104,13 @@ static void baytrail_core_init(device_t cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
+ /* On bay trail the turbo disable bit is actually scoped at building
+ * block level -- not package. For non-bsp cores that are within a
+ * building block enable turbo. The cores within the BSP's building
+ * block will just see it already enabled and move on. */
+ if (lapicid())
+ enable_turbo();
+
/* Set core MSRs */
reg_script_run(core_msr_script);
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5047
-gerrit
commit 52d9c03299ec5668485bc2a9bddec9703327c4cc
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jan 14 17:28:33 2014 -0600
cpu/intel: allow non-packaged scoped turbo setting
In the past the turbo disable setting (bit 38) of the
IA32_MISC_ENABLES msr has been package scoped. That means
knocking the turbo disable bit down enabled turbo for the
entire package. Sadly, that's no longer true on all Intel
processors. Therefore, allow non-packaged scoped turbo
setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
Kconfig option. It defaults to false which was the original
assumption.
BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and ran both ways successfully.
Change-Id: I71a31e76ff47878023081fc47da643187517b597
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182405
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/cpu/intel/Kconfig | 1 +
src/cpu/intel/turbo/Kconfig | 6 ++++++
src/cpu/intel/turbo/turbo.c | 27 +++++++++++++++++++++++++--
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 6f4f561..af03619 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -37,3 +37,4 @@ source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA989/Kconfig
# Architecture specific features
source src/cpu/intel/fit/Kconfig
+source src/cpu/intel/turbo/Kconfig
diff --git a/src/cpu/intel/turbo/Kconfig b/src/cpu/intel/turbo/Kconfig
new file mode 100644
index 0000000..5432c28
--- /dev/null
+++ b/src/cpu/intel/turbo/Kconfig
@@ -0,0 +1,6 @@
+
+config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+ def_bool n
+ help
+ This option indicates that the turbo mode setting is not package
+ scoped. i.e. enable_turbo() needs to be called on not just the bsp
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index 779550e..7599ff1 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -24,7 +24,28 @@
#include <cpu/x86/msr.h>
#include <arch/cpu.h>
-static int turbo_state = TURBO_UNKNOWN;
+#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+static inline int get_global_turbo_state(void)
+{
+ return TURBO_UNKNOWN;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+}
+#else
+static int g_turbo_state = TURBO_UNKNOWN;
+
+static inline int get_global_turbo_state(void)
+{
+ return g_turbo_state;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+ g_turbo_state = state;
+}
+#endif
static const char *turbo_state_desc[] = {
[TURBO_UNKNOWN] = "unknown",
@@ -43,6 +64,7 @@ int get_turbo_state(void)
struct cpuid_result cpuid_regs;
int turbo_en, turbo_cap;
msr_t msr;
+ int turbo_state = get_global_turbo_state();
/* Return cached state if available */
if (turbo_state != TURBO_UNKNOWN)
@@ -65,6 +87,7 @@ int get_turbo_state(void)
turbo_state = TURBO_ENABLED;
}
+ set_global_turbo_state(turbo_state);
printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]);
return turbo_state;
}
@@ -84,7 +107,7 @@ void enable_turbo(void)
wrmsr(MSR_IA32_MISC_ENABLES, msr);
/* Update cached turbo state */
- turbo_state = TURBO_ENABLED;
+ set_global_turbo_state(TURBO_ENABLED);
printk(BIOS_INFO, "Turbo has been enabled\n");
}
}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5046
-gerrit
commit 09322b51bc8398905c354b76bc3607d77c169a44
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jan 14 14:59:28 2014 -0800
baytrail: Add ACPI Device for XHCI
This will allow USB devices to wake the system (if 5V is not turned off)
and the controller to enter D3 at runtime. (if autosuspend is enabled)
BUG=chrome-os-partner:23629
BRANCH=baytrail
TEST=build and boot on baytrail
1) with modified EC to leave 5V on in S3 ensure that waking from suspend
with USB keyboard works.
2) with laptop-mode-tools usb autosuepend config updated see that device
enters D3 at runtime when no external devices attached.
Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182536
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/acpi/southcluster.asl | 3 +++
src/soc/intel/baytrail/acpi/xhci.asl | 36 ++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index ced1618..61642a5 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -252,6 +252,9 @@ Device (IOSF)
// LPC Bridge 0:1f.0
#include "lpc.asl"
+// USB XHCI 0:14.0
+#include "xhci.asl"
+
// IRQ routing for each PCI device
#include "irqroute.asl"
diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl
new file mode 100644
index 0000000..4d5367a
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/xhci.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (XHCI)
+{
+ Name (_ADR, 0x00140000)
+ Name (_PRW, Package () { 0x0d, 3 })
+ Name (_S3D, 3) /* Highest D state in S3 state */
+
+ Device (RHUB)
+ {
+ Name (_ADR, 0x00000000)
+ Device (PRT1) { Name (_ADR, 1) }
+ Device (PRT2) { Name (_ADR, 2) }
+ Device (PRT3) { Name (_ADR, 3) }
+ Device (PRT4) { Name (_ADR, 4) }
+ }
+}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5045
-gerrit
commit e46372e85bcb2dbca79f3be964d224715b382d68
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Jan 13 10:15:12 2014 -0800
rambi: Add ACPI table support for I2C devices
In order to support probing I2C devices when the controller is
in ACPI mode the mainboard needs to decalre them in the proper
scope with the address/interrupt information. The touchpad devices
are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can
be distinguished in userland scripts based on ID. There is also
a special "ISTP" node that indicates whether the devices is a
touchpad (=1) or touchscreen (=0) in case this is useful to drivers.
These names may not be final but they are a starting point and can
be easily changed.
Atmel devices also have a bootloader mode which needs to be
declared as a separate device. Unfortunately it does not work as
expected to have multiple I2cSerialBus() resources declared in a
single device and have it select properly, even with the use of
StartDependentFn(), so bootloader devices are declared separately.
The original devices are left in \_SB scope and are only enabled
if the I2C controllers are in PCI mode. The new devices are only
enabled if the I2C controllers are in ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual
1) Ensure there is no change in functionality by default and that
the devices are still probed by chromeos_laptop in the kernel.
2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to
add _HID entries for devices in appropriate drivers. Ensure that
the devices are probed successfully. Further changes are needed
to the chromeos-touch-firmware scripts to load config and update
firmware based on the new ACPI _HID entries.
3) Put touchpad in bootloader mode (by flashing bad firmware) and
ensure that it is detected at address 0x25 and the firmware is
able to be updated.
Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182259
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/acpi/mainboard.asl | 226 +++++++++++++++++++++++---
src/mainboard/google/rambi/dsdt.asl | 5 +-
2 files changed, 202 insertions(+), 29 deletions(-)
diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl
index 696d1aa..9b16272 100644
--- a/src/mainboard/google/rambi/acpi/mainboard.asl
+++ b/src/mainboard/google/rambi/acpi/mainboard.asl
@@ -40,71 +40,243 @@ Scope (\_SB)
Device (TPAD)
{
- Name (_ADR, 0x0)
+ Name (_HID, EisaId ("PNP0C0E"))
Name (_UID, 1)
- // Report as a Sleep Button device so Linux will
- // automatically enable it as a wake source
- Name (_HID, EisaId("PNP0C0E"))
-
Name (_CRS, ResourceTemplate()
{
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
BOARD_TRACKPAD_IRQ
}
+ })
+
+ Method (_STA)
+ {
+ /* Disable if I2C1 is in ACPI mode */
+ If (LEqual (\S1EN, 1)) {
+ Return (0x0)
+ } Else {
+ Return (0xF)
+ }
+ }
- VendorShort (ADDR)
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+ }
+
+ Device (TSCR)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 2)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
{
- BOARD_TRACKPAD_I2C_ADDR
+ BOARD_TOUCHSCREEN_IRQ
}
})
- Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+ Method (_STA)
+ {
+ /* Disable if I2C6 is in ACPI mode */
+ If (LEqual (\S6EN, 1)) {
+ Return (0x0)
+ } Else {
+ Return (0xF)
+ }
+ }
+
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+ }
+}
+
+Scope (\_SB.I2C1)
+{
+ Device (ATPB)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad Bootloader")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
- Method (_DSW, 3, NotSerialized)
+ Name (_CRS, ResourceTemplate()
{
- Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
+ I2cSerialBus (
+ 0x25, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- // \_SB.PCI0.LPCB.GWAK (Local0)
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
}
}
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
}
- Device (TSCR)
+ Device (ATPA)
{
- Name (_ADR, 0x0)
+ Name (_HID, "ATML0000")
+ Name (_CID, EisaId ("PNP0C0E"))
+ Name (_DDN, "Atmel Touchpad")
Name (_UID, 2)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4b, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
- // Report as a Sleep Button device so Linux will
- // automatically enable it as a wake source
- Name (_HID, EisaId("PNP0C0E"))
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+ }
+
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_CID, EisaId ("PNP0C0E"))
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
Name (_CRS, ResourceTemplate()
{
+ I2cSerialBus (
+ 0x15, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\_SB.I2C1", // ResourceSource
+ )
Interrupt (ResourceConsumer, Edge, ActiveLow)
{
- BOARD_TOUCHSCREEN_IRQ
+ BOARD_TRACKPAD_IRQ
}
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+ }
+}
+
+Scope (\_SB.I2C6)
+{
+ Device (ATSB)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen Bootloader")
+ Name (_UID, 4)
+ Name (ISTP, 0) /* TouchScreen */
- VendorShort (ADDR)
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x26, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
{
- BOARD_TOUCHSCREEN_I2C_ADDR
+ BOARD_TOUCHSCREEN_IRQ
}
})
- Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
- Method (_DSW, 3, NotSerialized)
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ATSA)
+ {
+ Name (_HID, "ATML0001")
+ Name (_CID, EisaId ("PNP0C0E"))
+ Name (_DDN, "Atmel Touchscreen")
+ Name (_UID, 5)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
{
- Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
+ I2cSerialBus (
+ 0x4a, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
- If (LEqual (Arg0, 1)) {
- // Enable GPIO as wake source
- // \_SB.PCI0.LPCB.GWAK (Local0)
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
}
}
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
}
}
diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl
index 53f2922..4165087 100644
--- a/src/mainboard/google/rambi/dsdt.asl
+++ b/src/mainboard/google/rambi/dsdt.asl
@@ -23,7 +23,7 @@
DefinitionBlock(
"dsdt.aml",
"DSDT",
- 0x02, // DSDT revision: ACPI v2.0
+ 0x05, // DSDT revision: ACPI v5.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
@@ -31,7 +31,6 @@ DefinitionBlock(
{
// Some generic macros
#include <soc/intel/baytrail/acpi/platform.asl>
- #include "acpi/mainboard.asl"
// global NVS and variables
#include <soc/intel/baytrail/acpi/globalnvs.asl>
@@ -56,4 +55,6 @@ DefinitionBlock(
/* Chipset specific sleep states */
#include <soc/intel/baytrail/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5044
-gerrit
commit f334fd148982d05aea37d597afa5ef655db3969b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 13 11:39:04 2014 -0600
baytrail: nvm: use proper types for checking erase
The current byte value was being converted to an int
when checking against literal 0xff. As the type of
the current pointer was char (signed) it was sign
extending the value leading to 0xffffffff != 0xff.
Fix this by using an unsigned type and using a
constant type for expected erase value.
BUG=chrome-os-partner:24916
BRANCH=baytrail
TEST=Booted after chromeos-firmwareupdate. Noted that MRC
cache doesn't think the erased region isn't erased.
Change-Id: If95425fe26da050acb25f52bea060e288ad3633c
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182154
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/nvm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c
index dccc801..843bc5a 100644
--- a/src/soc/intel/baytrail/nvm.c
+++ b/src/soc/intel/baytrail/nvm.c
@@ -54,10 +54,11 @@ static inline uint32_t to_flash_offset(void *p)
int nvm_is_erased(const void *start, size_t size)
{
- const char *cur = start;
+ const uint8_t *cur = start;
+ const uint8_t erased_value = 0xff;
while (size > 0) {
- if (*cur != 0xff)
+ if (*cur != erased_value)
return 0;
cur++;
size--;
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5043
-gerrit
commit 60a3cdc69519eda0216b905f5764876081de888c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 13 11:34:51 2014 -0600
baytrail: mrc_cache: check region erased before erasing
On a firmware update the MRC cache is destroyed. On the
subsequent boot the MRC region was attempted to be erased
even if it was already erased. This led to spi part taking
longer than it should have for an unnecessary erase
operation. Therefore, check that the region is erased
before issuing the erease command.
BUG=chrome-os-partner:24916
BRANCH=baytrail
TEST=Booted after chromeos-firmeareupdate. Noted no
error messages in this path.
Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182153
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/mrc_cache.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/soc/intel/baytrail/mrc_cache.c b/src/soc/intel/baytrail/mrc_cache.c
index 0ba1408..9f7676b 100644
--- a/src/soc/intel/baytrail/mrc_cache.c
+++ b/src/soc/intel/baytrail/mrc_cache.c
@@ -279,9 +279,12 @@ static void update_mrc_cache(void *unused)
next_slot = mrc_cache_next_slot(®ion, current_saved);
if (!mrc_slot_valid(®ion, next_slot, current_boot)) {
- if (nvm_erase(region.base, region.size) < 0) {
- printk(BIOS_DEBUG, "Could not erase MRC region.\n");
- return;
+ printk(BIOS_DEBUG, "Slot @ %p is invalid.\n", next_slot);
+ if (!nvm_is_erased(region.base, region.size)) {
+ if (nvm_erase(region.base, region.size) < 0) {
+ printk(BIOS_DEBUG, "Failure erasing region.\n");
+ return;
+ }
}
next_slot = region.base;
}