the following patch was just integrated into master:
commit 3b0d97e2b7cb99fb2997f679451a69756ffaf2f5
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Dec 28 19:29:36 2013 -0500
cpu/allwinner/a10: Add helper to configure CPU clock
Change-Id: I5a3bb3220aeefdd6822a7dbecf210ff77095dad6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4685 for details.
-gerrit
the following patch was just integrated into master:
commit 734683460d29c21862e2713f40c80bea1995d827
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Jan 13 00:49:49 2014 -0600
lib: Add log2 ceiling function
Change-Id: Ifb41050e729a0ce314e4d4918e46f82bc7e16bed
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4684 for details.
-gerrit
the following patch was just integrated into master:
commit a34cc32d7af7539186b0215fddc6cb137edf5906
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Dec 26 22:53:52 2013 -0500
lib/hexdump: Take const void * and size_t as arguments
Representing a memory location as an unsigned long is specific to
32-bit architectures. It also doesn't make sense to represent a length
assumed to be positive as a signed integer. With this change, it is no
longer necessary to cast a pointer to unsigned long when passing it to
hexdump.
Change-Id: I641777d940ceac6f37c363051f1e9c1b3ec3ed95
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4575 for details.
-gerrit
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4687
-gerrit
commit 0db3b7b8711e242627c73ab4e0fa857e1df76b91
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Dec 28 15:42:31 2013 -0500
cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.
Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/allwinner/a10/Kconfig | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig
index b782b9a..fab0022 100644
--- a/src/cpu/allwinner/a10/Kconfig
+++ b/src/cpu/allwinner/a10/Kconfig
@@ -34,14 +34,18 @@ config CBFS_HEADER_ROM_OFFSET
hex
default 0x10
+# This is the maximum size bootblock that the BROM will load. If the bootblock
+# gets larger, this will generate a build failure, rather than a silent
+# "coreboot won't run" failure.
+# Normally, we would place romstage at 0x5fe0, but we place it a little lower to
+# satisfy the 64 byte alignment.
config CBFS_ROM_OFFSET
- # Calculated by BL1 + max bootblock size.
- default 0x4c00
+ default 0x5fc0
-# FIXME: untested
+# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
- default SYS_SDRAM_BASE
+ default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4687
-gerrit
commit cab4da1b46a7cd1f7e26abb1f5d78a6bf9272ae7
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Dec 28 15:42:31 2013 -0500
cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.
Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/allwinner/a10/Kconfig | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig
index b782b9a..fb9e3d2 100644
--- a/src/cpu/allwinner/a10/Kconfig
+++ b/src/cpu/allwinner/a10/Kconfig
@@ -34,14 +34,16 @@ config CBFS_HEADER_ROM_OFFSET
hex
default 0x10
+# This is the maximum size bootblock that the BROM will load. If the bootblock
+# gets larger, this will generate a build failure, rather than a silent
+# "coreboot won't run" failure.
config CBFS_ROM_OFFSET
- # Calculated by BL1 + max bootblock size.
- default 0x4c00
+ default 0x5fe0
-# FIXME: untested
+# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
- default SYS_SDRAM_BASE
+ default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4687
-gerrit
commit 25a382ec27d3e0e2a3edc3a6eaabb5895e6ab1de
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Dec 28 15:42:31 2013 -0500
cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.
Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/allwinner/a10/Kconfig | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig
index b782b9a..347e315 100644
--- a/src/cpu/allwinner/a10/Kconfig
+++ b/src/cpu/allwinner/a10/Kconfig
@@ -34,14 +34,16 @@ config CBFS_HEADER_ROM_OFFSET
hex
default 0x10
+# This is the maximum size bootblock that the BROM will load. If the bootblock
+# gets larger, this will generate a build failure, rather than a silent
+# "coreboot won't run" failure.
config CBFS_ROM_OFFSET
- # Calculated by BL1 + max bootblock size.
- default 0x4c00
+ default 0x5fe0
-# FIXME: untested
+# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
- default SYS_SDRAM_BASE
+ default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4686
-gerrit
commit 29fe00a9915d1f8bf49a3cc1df38831b8d101cc9
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jan 3 01:27:23 2014 -0500
cubieboard: Setup CPU clock in romstage and load ramstage
This completes the romstage for the cubieboard.
Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/cubietech/cubieboard/romstage.c | 28 ++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c
index 1b4d886..199842b 100644
--- a/src/mainboard/cubietech/cubieboard/romstage.c
+++ b/src/mainboard/cubietech/cubieboard/romstage.c
@@ -1,10 +1,17 @@
/*
- * Placeholder for Cubieboard romstage
+ * Basic romstage for Cubieboard
+ *
+ * Set up system voltages, then increase the CPU clock, before turning control
+ * to ramstage. The CPU VDD needs to be properly set before it can run at full
+ * speed. Setting the CPU at full speed helps lzma-decompress ramstage a lot
+ * faster.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
* Subject to the GNU GPL v2, or (at your option) any later version.
*/
+#include <arch/stages.h>
+#include <cbfs.h>
#include <console/console.h>
#include <cpu/allwinner/a10/clock.h>
#include <cpu/allwinner/a10/gpio.h>
@@ -63,10 +70,25 @@ static enum cb_err cubieboard_setup_power(void)
void main(void)
{
+ void *entry;
+ enum cb_err err;
+
console_init();
- printk(BIOS_INFO, "You have managed to succesfully load romstage.\n");
/* Configure power rails */
- cubieboard_setup_power();
+ err = cubieboard_setup_power();
+
+ if (err == CB_SUCCESS) {
+ /* TODO: Get this clock from devicetree.cb */
+ a1x_set_cpu_clock(1008);
+ } else {
+ /* cubieboard_setup_power() prints more details */
+ printk(BIOS_WARNING, "Will run CPU at reduced speed\n");
+ a1x_set_cpu_clock(384);
+ }
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+ printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
+ stage_exit(entry);
}