the following patch was just integrated into master:
commit ec1c83d662fd323b127383d356cd688ca02cba68
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Jan 12 15:42:58 2014 -0600
lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline function in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.
Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4681 for details.
-gerrit
the following patch was just integrated into master:
commit 89cd903714b61684236d48833988aab8de036baf
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jan 10 23:06:03 2014 -0600
cpu/allwinner/a10: Provide utility to make a bootable image
Up until now, we relied on mksunxiboot to prepend the header which
makes coreboot.rom bootable on Allwinner SoCs. If that tool was not
present, the build silently failed.
Integrate this tool into our util/ package, so that we do not have to
rely on mksunxiboot being in PATH.
Our version of mksunxiboot also eliminates some limitations of the
original tool, so we no longer have to use 'dd' to limit the file
size.
Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4656 for details.
-gerrit
the following patch was just integrated into master:
commit d15eefdaa3010ce439194a3633e3ecf62accc7df
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Jan 9 20:42:13 2014 -0600
cpu/allwinner/a10: Clean up include order in Makefile.inc
Alphabetize the sources for each stage (bootblock, rom, ram), and
include twi.c in both romstage and ramstage.
Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4639 for details.
-gerrit
the following patch was just integrated into master:
commit 4688df68f90204a6d80ea8abce94db0d99e85ed0
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Thu Jan 9 20:07:10 2014 -0600
xpowers/axp209: Allow voltages to be sepecified in devicetree.cb
This allows system voltages to be specified uniformly, rather than
hardcoding them for each board. This will be used by cubieboard in an
upcoming patch.
Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4637 for details.
-gerrit
the following patch was just integrated into master:
commit 4297b8239f46b3654b7a9f3cba28e1b778f025b4
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Dec 30 01:21:55 2013 -0500
drivers: Add support for X-Powers AXP209 PMU
Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4591 for details.
-gerrit
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4681
-gerrit
commit ec1c83d662fd323b127383d356cd688ca02cba68
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Jan 12 15:42:58 2014 -0600
lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline function in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.
Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/include/arch/io.h | 6 +++++-
src/include/lib.h | 2 +-
src/lib/Makefile.inc | 1 +
src/northbridge/amd/amdk8/incoherent_ht.c | 1 +
src/northbridge/intel/e7505/raminit.c | 1 +
src/northbridge/intel/i3100/raminit.c | 1 +
src/northbridge/intel/i945/raminit.c | 1 +
7 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 955d8e2..b10fb8a 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -167,7 +167,8 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
*((volatile uint32_t *)(addr)) = value;
}
-#if defined(__PRE_RAM__) || defined(__SMM__)
+/* Conflicts with definition in lib.h */
+#if defined(__ROMCC__) || defined(__SMM__)
static inline int log2(int value)
{
unsigned int r = 0;
@@ -180,6 +181,9 @@ static inline int log2(int value)
return r;
}
+#endif
+
+#if defined(__PRE_RAM__) || defined(__SMM__)
static inline int log2f(int value)
{
unsigned int r = 0;
diff --git a/src/include/lib.h b/src/include/lib.h
index 5fc390a..3a51533 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -23,7 +23,7 @@
#define __LIB_H__
#include <stdint.h>
-#ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */
+#if !defined(__ROMCC__) /* Conflicts with inline function in arch/io.h */
/* Defined in src/lib/clog2.c */
unsigned long log2(unsigned long x);
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b09dace..37c7dea 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -88,6 +88,7 @@ ramstage-y += lzma.c
ramstage-y += stack.c
ramstage-$(CONFIG_ARCH_X86) += gcc.c
ramstage-y += clog2.c
+romstage-y += clog2.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 6cbe7dc..c1509f0 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -6,6 +6,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
+#include <lib.h>
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 3d4dfe2..455f3ab 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -16,6 +16,7 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
+#include <lib.h>
#include <stdlib.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 0292496..e83feaa 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -22,6 +22,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/intel/speedstep.h>
+#include <lib.h>
#include <stdlib.h>
#include "raminit.h"
#include "i3100.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 512d8e9..046f5f8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -24,6 +24,7 @@
#include <spd.h>
#include <string.h>
#include <arch/io.h>
+#include <lib.h>
#include "raminit.h"
#include "i945.h"
#include <cbmem.h>
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4681
-gerrit
commit 72bfad546ec1b438a099f689ea8aef5ca9bd032d
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Jan 12 15:42:58 2014 -0600
lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline functions in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.
Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/include/arch/io.h | 6 +++++-
src/include/lib.h | 2 +-
src/lib/Makefile.inc | 1 +
src/northbridge/amd/amdk8/incoherent_ht.c | 1 +
src/northbridge/intel/e7505/raminit.c | 1 +
src/northbridge/intel/i3100/raminit.c | 1 +
src/northbridge/intel/i945/raminit.c | 1 +
7 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 955d8e2..b10fb8a 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -167,7 +167,8 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
*((volatile uint32_t *)(addr)) = value;
}
-#if defined(__PRE_RAM__) || defined(__SMM__)
+/* Conflicts with definition in lib.h */
+#if defined(__ROMCC__) || defined(__SMM__)
static inline int log2(int value)
{
unsigned int r = 0;
@@ -180,6 +181,9 @@ static inline int log2(int value)
return r;
}
+#endif
+
+#if defined(__PRE_RAM__) || defined(__SMM__)
static inline int log2f(int value)
{
unsigned int r = 0;
diff --git a/src/include/lib.h b/src/include/lib.h
index 5fc390a..3a51533 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -23,7 +23,7 @@
#define __LIB_H__
#include <stdint.h>
-#ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */
+#if !defined(__ROMCC__) /* Conflicts with inline function in arch/io.h */
/* Defined in src/lib/clog2.c */
unsigned long log2(unsigned long x);
#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b09dace..37c7dea 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -88,6 +88,7 @@ ramstage-y += lzma.c
ramstage-y += stack.c
ramstage-$(CONFIG_ARCH_X86) += gcc.c
ramstage-y += clog2.c
+romstage-y += clog2.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 6cbe7dc..c1509f0 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -6,6 +6,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
+#include <lib.h>
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 3d4dfe2..455f3ab 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -16,6 +16,7 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
+#include <lib.h>
#include <stdlib.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 0292496..e83feaa 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -22,6 +22,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/intel/speedstep.h>
+#include <lib.h>
#include <stdlib.h>
#include "raminit.h"
#include "i3100.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 512d8e9..046f5f8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -24,6 +24,7 @@
#include <spd.h>
#include <string.h>
#include <arch/io.h>
+#include <lib.h>
#include "raminit.h"
#include "i945.h"
#include <cbmem.h>
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4683
-gerrit
commit aaea690053e90ae89028a6af018dc1a781985a13
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon Dec 30 10:11:33 2013 +0200
AMD (non-AGESA): Common header for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/car/post_cache_as_ram.c | 6 +-----
src/include/cpu/amd/car.h | 18 ++++++++++++++++++
src/include/lib.h | 8 --------
src/mainboard/digitallogic/msm800sev/romstage.c | 2 +-
src/mainboard/pcengines/alix1c/romstage.c | 2 +-
src/mainboard/pcengines/alix2d/romstage.c | 2 +-
6 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 81175da..1669da7 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -5,6 +5,7 @@
#include <arch/stages.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
+#include <cpu/amd/car.h>
#include "cbmem.h"
#include "cpu/amd/car/disable_cache_as_ram.c"
@@ -75,8 +76,6 @@ static void vErrata343(void)
#endif
}
-void cache_as_ram_switch_stack(void *resume_backup_memory);
-
void post_cache_as_ram(void)
{
void *resume_backup_memory = NULL;
@@ -113,9 +112,6 @@ void post_cache_as_ram(void)
}
void
-cache_as_ram_new_stack (void *resume_backup_memory);
-
-void
cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused)))
{
/* We can put data to stack again */
diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h
new file mode 100644
index 0000000..4bc7a03
--- /dev/null
+++ b/src/include/cpu/amd/car.h
@@ -0,0 +1,18 @@
+#ifndef _CPU_AMD_CAR_H
+#define _CPU_AMD_CAR_H
+
+#if CONFIG_CPU_AMD_GEODE_LX
+void done_cache_as_ram_main(void);
+#endif
+
+#if !(CONFIG_CPU_AMD_GEODE_LX || CONFIG_CPU_AMD_GEODE_GX1 || CONFIG_CPU_AMD_GEODE_GX2)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+#endif
+
+#if CONFIG_CPU_AMD_MODEL_FXX || CONFIG_CPU_AMD_MODEL_10XXX
+void cache_as_ram_switch_stack(void *resume_backup_memory);
+void cache_as_ram_new_stack(void *resume_backup_memory);
+void post_cache_as_ram(void);
+#endif
+
+#endif
diff --git a/src/include/lib.h b/src/include/lib.h
index 5fc390a..4fa9425 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -48,14 +48,6 @@ int checkstack(void *top_of_stack, int core);
extern unsigned char _estack[];
#endif
-/* Defined in romstage.c */
-#if CONFIG_CPU_AMD_GEODE_LX
-void cache_as_ram_main(void);
-#else
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#endif
-void post_cache_as_ram(void);
-
/* Defined in src/lib/hexdump.c */
void hexdump(unsigned long memory, int length);
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index cc2fc4b..b96f8ae 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -8,6 +8,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
@@ -75,6 +76,5 @@ void main(unsigned long bist)
/* we are finding the return does not work on this board. Explicitly call the label that is
* after the call to us. This is gross, but sometimes at this level it is the only way out
*/
- void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index c3f964d..1c4ae09 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -29,6 +29,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "northbridge/amd/lx/raminit.h"
@@ -162,6 +163,5 @@ void main(unsigned long bist)
* call the label that is after the call to us. This is gross, but
* sometimes at this level it is the only way out.
*/
- void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 6946900..18453ac 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -29,6 +29,7 @@
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
+#include <cpu/amd/car.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "northbridge/amd/lx/raminit.h"
@@ -186,6 +187,5 @@ void main(unsigned long bist)
* call the label that is after the call to us. This is gross, but
* sometimes at this level it is the only way out.
*/
- void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}