the following patch was just integrated into master:
commit 61b4003d0a1fc4ef7cf1e69a352bf6137c1300de
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon Jan 6 11:06:26 2014 +0200
Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.
Side-effects to consider:
Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.
With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.
Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/4625 for details.
-gerrit
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4650
-gerrit
commit 6e032fc83e1b4379ce930d87440f1715f8476212
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Jun 7 02:11:41 2013 +0200
Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.
Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +++++--
src/mainboard/lenovo/Kconfig | 4 ++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index a29fdbf..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -41,4 +41,8 @@ config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
the following patch was just integrated into master:
commit 7279d025d078da50dc99d1cf990fc37fdf99ae50
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Jan 12 19:25:00 2014 +0100
sandybridge: Allow skipping mrc.cache
On X230 MRC fails if cache is passed to it. Until better solution is found
do not create mrc.cache
Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/4680 for details.
-gerrit
the following patch was just integrated into master:
commit 0db3b7b8711e242627c73ab4e0fa857e1df76b91
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Dec 28 15:42:31 2013 -0500
cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.
Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4687 for details.
-gerrit
the following patch was just integrated into master:
commit 29fe00a9915d1f8bf49a3cc1df38831b8d101cc9
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jan 3 01:27:23 2014 -0500
cubieboard: Setup CPU clock in romstage and load ramstage
This completes the romstage for the cubieboard.
Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
See http://review.coreboot.org/4686 for details.
-gerrit