the following patch was just integrated into master:
commit 483abd815e81377be59c728cc9d812e4cf151706
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Jan 15 15:52:31 2014 +0100
ROMSIZE: Add option for 12M chips.
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.
Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/4688 for details.
-gerrit
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4688
-gerrit
commit 483abd815e81377be59c728cc9d812e4cf151706
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Jan 15 15:52:31 2014 +0100
ROMSIZE: Add option for 12M chips.
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.
Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 1e8d98f..73ca544 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -228,6 +228,8 @@ config BOARD_ROMSIZE_KB_4096
bool
config BOARD_ROMSIZE_KB_8192
bool
+config BOARD_ROMSIZE_KB_12288
+ bool
config BOARD_ROMSIZE_KB_16384
bool
@@ -242,6 +244,7 @@ choice
default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
+ default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288
default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
help
Select the size of the ROM chip you intend to flash coreboot on.
@@ -289,6 +292,11 @@ config COREBOOT_ROMSIZE_KB_8192
help
Choose this option if you have a 8192 KB (8 MB) ROM chip.
+config COREBOOT_ROMSIZE_KB_12288
+ bool "12288 KB (12 MB)"
+ help
+ Choose this option if you have a 12288 KB (12 MB) ROM chip.
+
config COREBOOT_ROMSIZE_KB_16384
bool "16384 KB (16 MB)"
help
@@ -307,6 +315,7 @@ config COREBOOT_ROMSIZE_KB
default 2048 if COREBOOT_ROMSIZE_KB_2048
default 4096 if COREBOOT_ROMSIZE_KB_4096
default 8192 if COREBOOT_ROMSIZE_KB_8192
+ default 12288 if COREBOOT_ROMSIZE_KB_12288
default 16384 if COREBOOT_ROMSIZE_KB_16384
# Map the config names to a hex value (bytes).
@@ -320,6 +329,7 @@ config ROM_SIZE
default 0x200000 if COREBOOT_ROMSIZE_KB_2048
default 0x400000 if COREBOOT_ROMSIZE_KB_4096
default 0x800000 if COREBOOT_ROMSIZE_KB_8192
+ default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
config ENABLE_POWER_BUTTON
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4650
-gerrit
commit 61b1f4f135aa186db4cb95999a0298aa34cea719
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Jun 7 02:11:41 2013 +0200
Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.
Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +++++--
src/mainboard/lenovo/Kconfig | 4 ++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index a29fdbf..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -41,4 +41,8 @@ config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
the following patch was just integrated into master:
commit 3003dac92009ead3c00f5eb60e2e09ea361301d3
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Jan 4 11:02:45 2014 +0200
Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
Delay the copying of MRC cache data from CAR to CBMEM until after
sdram_initialize() returns and cbmem_initialize() completes.
Calling cbmem_initialize() twice would complicate the decision logic
of when CBMEM area needs to be wiped clean.
Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/4666 for details.
-gerrit
the following patch was just integrated into master:
commit f18612fef48b1e872520194f76d716f54e375a6a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Oct 15 20:16:26 2013 +0300
google/stout: Add EARLY_CBMEM_INIT
Required for MRC cache and for HAVE_ACPI_RESUME to work.
Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/4665 for details.
-gerrit
the following patch was just integrated into master:
commit 67fdc78775cae877285dd2cf41097962ac801e68
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Oct 15 17:19:41 2013 +0300
CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.
Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.
Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/3993 for details.
-gerrit
the following patch was just integrated into master:
commit 3dc9128bf1df9ca0746a69eb7fa2175fa4d5fb03
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon Jan 6 11:08:01 2014 +0200
nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.
Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/4626 for details.
-gerrit