coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2712474 usbdebug: Fixes for LynxPoint LP
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3477 -gerrit commit 2712474ca442650123cfe92bec83bd4807092f89 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 13 09:10:31 2013 +0300 usbdebug: Fixes for LynxPoint LP Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 4 ++-- src/southbridge/intel/lynxpoint/early_usb.c | 10 ++++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 79aba6c..3cf9ffe 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select IOAPIC select HAVE_HARD_RESET - select HAVE_USBDEBUG + select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK @@ -42,7 +42,7 @@ config INTEL_LYNXPOINT_LP config EHCI_BAR hex - default 0xfef00000 + default 0xe8000000 config EHCI_DEBUG_OFFSET hex diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index d71467e..d65ca4a 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -24,8 +24,14 @@ #include <device/pci_def.h> #include "pch.h" -#define PCH_EHCI1_TEMP_BAR0 0xe8000000 -#define PCH_EHCI2_TEMP_BAR0 0xe8000400 + +#if CONFIG_USBDEBUG_HCD_INDEX != 2 +#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR +#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400) +#else +#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR +#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400) +#endif /* * Setup USB controller MMIO BAR to prevent the

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Patch set updated for coreboot: 5830fd0 Add pci_devfn_t and use with __SIMPLE_DEVICE__
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3508 -gerrit commit 5830fd042e7c72aead4f352c897315a29fb79abd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 20 20:25:21 2013 +0300 Add pci_devfn_t and use with __SIMPLE_DEVICE__ Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 22 ++++++++++++++-------- src/arch/x86/include/arch/pci_io_cfg.h | 12 ++++++------ src/arch/x86/include/arch/pci_mmio_cfg.h | 18 +++++++++--------- src/include/device/device.h | 1 + src/northbridge/intel/gm45/ram_calc.c | 2 +- src/southbridge/amd/cimx/sb700/reset.c | 2 +- src/southbridge/amd/cimx/sb800/reset.c | 2 +- src/southbridge/amd/cimx/sb900/early.c | 2 +- src/southbridge/amd/cimx/sb900/reset.c | 2 +- src/southbridge/amd/sb600/enable_usbdebug.c | 2 +- src/southbridge/amd/sb700/enable_usbdebug.c | 2 +- src/southbridge/amd/sb700/reset.c | 2 +- src/southbridge/intel/common/usb_debug.c | 2 +- src/southbridge/nvidia/ck804/enable_usbdebug.c | 4 ++-- src/southbridge/nvidia/mcp55/enable_usbdebug.c | 4 ++-- src/southbridge/sis/sis966/enable_usbdebug.c | 4 ++-- 16 files changed, 45 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 3b61e85..8591465 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -210,7 +210,10 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +/* FIXME: Sources for romstage still use device_t. */ +typedef u32 device_t; + +typedef u32 pci_devfn_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore @@ -220,23 +223,26 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> -static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) +void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value) { pci_write_config8(dev, where, pci_read_config8(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) +void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value) { pci_write_config16(dev, where, pci_read_config16(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) +void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) { pci_write_config32(dev, where, pci_read_config32(dev, where) | value); } #define PCI_DEV_INVALID (0xffffffffU) -static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) +static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -248,7 +254,7 @@ static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device(unsigned pci_id, device_t dev) +static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) { for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -260,9 +266,9 @@ static inline device_t pci_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static inline pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index fbe83a2..63e1ac9 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -21,7 +21,7 @@ #include <arch/io.h> static inline __attribute__((always_inline)) -uint8_t pci_io_read_config8(device_t dev, unsigned where) +uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -34,7 +34,7 @@ uint8_t pci_io_read_config8(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -uint16_t pci_io_read_config16(device_t dev, unsigned where) +uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -47,7 +47,7 @@ uint16_t pci_io_read_config16(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -uint32_t pci_io_read_config32(device_t dev, unsigned where) +uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -60,7 +60,7 @@ uint32_t pci_io_read_config32(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -73,7 +73,7 @@ void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) } static inline __attribute__((always_inline)) -void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +void pci_io_write_config16(pci_devfn_t dev, unsigned where, uint16_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -86,7 +86,7 @@ void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) } static inline __attribute__((always_inline)) -void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 545be23..b62a2166b 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -26,7 +26,7 @@ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) +u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -34,7 +34,7 @@ u8 pcie_read_config8(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) +u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~1); @@ -42,7 +42,7 @@ u16 pcie_read_config16(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) +u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~3); @@ -50,7 +50,7 @@ u32 pcie_read_config32(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) +void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -58,7 +58,7 @@ void pcie_write_config8(device_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) +void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~1); @@ -66,7 +66,7 @@ void pcie_write_config16(device_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) +void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~3); @@ -74,21 +74,21 @@ void pcie_write_config32(device_t dev, unsigned int where, u32 value) } static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) { u8 value = pcie_read_config8(dev, where); pcie_write_config8(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) { u16 value = pcie_read_config16(dev, where); pcie_write_config16(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) { u32 value = pcie_read_config32(dev, where); pcie_write_config32(dev, where, value | ormask); diff --git a/src/include/device/device.h b/src/include/device/device.h index 797e717..1056be7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -11,6 +11,7 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; +typedef u32 pci_devfn_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 4590544..28e947b 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -85,7 +85,7 @@ u32 decode_igd_gtt_size(const u32 gsm) u32 get_top_of_ram(void) { - const device_t dev = PCI_DEV(0, 0, 0); + const pci_devfn_t dev = PCI_DEV(0, 0, 0); u32 tor; diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 36f96d3..16c56a2 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -36,7 +36,7 @@ static inline void set_bios_reset(void) { u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 36f96d3..16c56a2 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -36,7 +36,7 @@ static inline void set_bios_reset(void) { u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 4879904..198066f 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -36,7 +36,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n"); diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 36f96d3..16c56a2 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -36,7 +36,7 @@ static inline void set_bios_reset(void) { u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 0e4b424..d20c8c4 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -34,7 +34,7 @@ void set_debug_port(unsigned int port) void enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ + pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ /* Select the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index f0efe41..00eb4d9 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -49,7 +49,7 @@ void set_debug_port(unsigned int port) */ void enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ + pci_devfn_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index e457368..ae79c4a 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -36,7 +36,7 @@ static void set_bios_reset(void) { u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index d140123..6b934f4 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -35,7 +35,7 @@ void set_debug_port(unsigned int port) void enable_usbdebug(unsigned int port) { u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ + pci_devfn_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 54b534e..90890e6 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -39,7 +39,7 @@ void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ + pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -50,7 +50,7 @@ void set_debug_port(unsigned int port) void enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ + pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index ec06653..069344b 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -33,7 +33,7 @@ void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -44,7 +44,7 @@ void set_debug_port(unsigned int port) void enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index 1ff04df..f38fe90 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -35,7 +35,7 @@ void set_debug_port(unsigned int port) { u32 dword; - device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ + pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -46,7 +46,7 @@ void set_debug_port(unsigned int port) void enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ + pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port);

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Patch set updated for coreboot: f5bb112 usbdebug: Support choice of EHCI controller
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3438 -gerrit commit f5bb112d0c7110cac85eeaa9eeaaec23120c5a5a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Aug 15 16:27:06 2013 +0300 usbdebug: Support choice of EHCI controller Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 19 ++++++++++++++++ src/include/usbdebug.h | 9 +++++--- src/lib/usbdebug.c | 21 ++++++++++++++++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 17 +++++++++------ src/southbridge/amd/sb600/enable_usbdebug.c | 13 ++++++----- src/southbridge/amd/sb700/enable_usbdebug.c | 25 ++++++++++++---------- src/southbridge/amd/sb800/enable_usbdebug.c | 17 +++++++++------ src/southbridge/intel/common/usb_debug.c | 16 ++++++++------ src/southbridge/nvidia/ck804/enable_usbdebug.c | 14 ++++++------ src/southbridge/nvidia/mcp55/enable_usbdebug.c | 14 ++++++------ src/southbridge/sis/sis966/enable_usbdebug.c | 14 ++++++------ 11 files changed, 120 insertions(+), 59 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 71e5725..a57ca58 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -131,6 +131,13 @@ config SPKMODEM # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG + bool + default y if HAVE_USBDEBUG_OPTIONS + default n + +# Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple +# EHCI controllers or multiple ports with Debug Port capability +config HAVE_USBDEBUG_OPTIONS def_bool n config USBDEBUG @@ -154,6 +161,18 @@ config USBDEBUG If unsure, say N. +config USBDEBUG_HCD_INDEX + int "Index for EHCI controller to use with usbdebug" + default 0 + depends on USBDEBUG + help + Some boards have multiple EHCI controllers with possibly only + one having the Debug Port capability on an external USB port. + + Mapping of this index to PCI device functions is southbridge + specific and mainboard level Kconfig should already provide + a working default value here. + config USBDEBUG_DEFAULT_PORT int "Default USB port to use as Debug Port" default 0 diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 2728be0..63013d5 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -22,6 +22,12 @@ #define USBDEBUG_H #define EHCI_BAR_INDEX 0x10 +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ + +typedef u32 pci_devfn_t; +pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx); +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base); #ifndef __PRE_RAM__ #if !CONFIG_USBDEBUG @@ -42,9 +48,6 @@ void pci_ehci_read_resources(struct device *dev); struct dbgp_pipe; -void enable_usbdebug(unsigned int port); -void set_debug_port(unsigned port); - int usbdebug_init(void); struct dbgp_pipe *dbgp_console_output(void); diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index cde19a1..ff59b78 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <arch/io.h> #include <device/pci.h> +#include <device/pci_def.h> #include <arch/byteorder.h> #include <cpu/x86/car.h> #include <string.h> @@ -397,6 +398,20 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) return -1; //-ENOTCONN; } +#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE +static void enable_usbdebug(void) +{ + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); +} +#endif + +static void set_debug_port(unsigned int port) +{ + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_ehci_dbg_set_port(dbg_dev, port); +} + static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; @@ -683,7 +698,9 @@ static void pci_ehci_set_resources(struct device *dev) void pci_ehci_read_resources(struct device *dev) { - if (!ehci_drv_ops) { + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + + if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); ehci_drv_ops = dev->ops; ehci_dbg_ops.set_resources = pci_ehci_set_resources; @@ -717,7 +734,7 @@ int usbdebug_init(void) struct ehci_debug_info *dbg_info = dbgp_ehci_info(); #if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE - enable_usbdebug(0); + enable_usbdebug(); #endif return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index bd62842..2fd2403 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -30,10 +30,15 @@ #define HUDSON_DEVN_BASE 0 #endif -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) +#define EHCI_EOR (base + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 reg32; @@ -46,14 +51,12 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, base); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 40c53ae..09fce2f 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -26,18 +26,21 @@ #include <device/pci_def.h> #include "sb600.h" +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ +} + /* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* TODO: Allow changing the physical USB port used as Debug Port. */ } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 6c46071..085bdd4 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,10 +27,20 @@ #include <device/pci_def.h> #include "sb700.h" -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) +#define EHCI_EOR (base + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) -void set_debug_port(unsigned int port) +/* + * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. + * This code currently only supports the first one, i.e., USB Debug devices + * attached to physical USB ports belonging to the first EHCI device. + */ +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 reg32; @@ -42,17 +52,10 @@ void set_debug_port(unsigned int port) write32(DEBUGPORT_MISC_CONTROL, reg32); } -/* - * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. - * This code currently only supports the first one, i.e., USB Debug devices - * attached to physical USB ports belonging to the first EHCI device. - */ -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index d17e955..71e8eb4 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -30,10 +30,15 @@ #define SB800_DEVN_BASE 0 #endif -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) +#define EHCI_EOR (base + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 reg32; @@ -46,14 +51,12 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, base); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 6b934f4..3fed2ab 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -26,25 +26,29 @@ #include <usbdebug.h> #include <device/pci_def.h> +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x1d, 7); +} + /* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { u32 dbgctl; - pci_devfn_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); + write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); } diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index d65fea2..d98bc98 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -36,10 +36,14 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -48,12 +52,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index f629c50..b0afec2 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -30,10 +30,14 @@ #include <device/pci_def.h> #include "mcp55.h" -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -42,12 +46,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index 04384ba..0d7503d 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -32,10 +32,14 @@ #include <device/pci_def.h> #include "sis966.h" -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -44,12 +48,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

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Patch set updated for coreboot: 961cdaa Add test to match struct device with pci_devfn_t
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3474 -gerrit commit 961cdaa6c24e94638e6da4074440422bb3432fda Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 17:16:56 2013 +0300 Add test to match struct device with pci_devfn_t Add a function to test if pci_devfn_t matches with a device instance of struct device, by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 13 +++++++++++++ src/include/device/pci.h | 1 + src/include/device/pci_def.h | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4c5a814..1d998ca 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1054,6 +1054,19 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) } /** + * Test for match between romstage and ramstage device instance. + * + * @param dev Pointer to the device structure. + * @param sdev Simple device model identifier, created with PCI_DEV(). + * @return Non-zero if bus:dev.fn of device matches. + */ +unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev) +{ + return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); +} + +/** * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are diff --git a/src/include/device/pci.h b/src/include/device/pci.h index be91ed3..1741c0d 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -79,6 +79,7 @@ unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); +unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index ac20659..dae4e68 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -474,4 +474,8 @@ #define PCI_FUNC(devfn) ((devfn) & 0x07) #define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8) +/* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ +#define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff) +#define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff) + #endif /* PCI_DEF_H */

1 0

New patch to review for coreboot: 4a18d8b kontron/ktqm77: Allow disabling onboard NICs
by Patrick Georgi 15 Aug '13

15 Aug '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3870 -gerrit commit 4a18d8b3cc971cc994af69e684438cab94807a11 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Aug 15 14:57:09 2013 +0200 kontron/ktqm77: Allow disabling onboard NICs Two new nvram variables control disabling the two non-ME NICs on the mainboard. This is implemented by disabling their PCIe bridge. Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/kontron/ktqm77/cmos.layout | 4 +++- src/mainboard/kontron/ktqm77/mainboard.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 15d8e45..47cd60f 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -99,7 +99,9 @@ entries 512 328 s 0 boot_devices 840 8 h 0 boot_default 848 1 e 9 cmos_defaults_loaded -#849 7 r 0 unused +849 1 e 2 ethernet1 +850 1 e 2 ethernet2 +#851 5 r 0 unused # coreboot config options: mainboard specific options 856 2 e 8 fan1_mode diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 454976c..3829d72 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -161,6 +161,23 @@ static void mainboard_enable(device_t dev) mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); + + unsigned disable = 0; + if ((get_option(&disable, "ethernet1") == 0) && disable) { + device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); + if (nic) { + printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); + nic->enabled = 0; + } + } + disable = 0; + if ((get_option(&disable, "ethernet2") == 0) && disable) { + device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); + if (nic) { + printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); + nic->enabled = 0; + } + } } struct chip_operations mainboard_ops = {

1 0

New patch to review for coreboot: a4ea749 kontron/ktqm77: Update MRC path
by Patrick Georgi 15 Aug '13

15 Aug '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3869 -gerrit commit a4ea74912e233ffe775116f5f9111ab890415a5a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Aug 15 14:43:13 2013 +0200 kontron/ktqm77: Update MRC path It still pointed to the old binary despite implementing the newer interface Change-Id: Iebd5dae98168f5568f3ad6a18c5ebde9abc3ece0 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/kontron/ktqm77/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 1665a25..58550e8 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config MRC_FILE string - default "3rdparty/northbridge/intel/sandybridge/systemagent-ivybridge.bin" + default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" config MAINBOARD_DIR string

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New patch to review for coreboot: 497ba2d usbdebug: Add optional quirk for old DIY debug part
by Kyösti Mälkki 14 Aug '13

14 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3868 -gerrit commit 497ba2d1e48b4bdefa6301a04f4b57a78ad048d7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 6 10:33:39 2013 +0300 usbdebug: Add optional quirk for old DIY debug part Not sure what this is about. Required for FX2. Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/usbdebug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index e84af5b..7e01a0f 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -594,10 +594,12 @@ try_next_port: } dprintk(BIOS_INFO, "EHCI debug port enabled.\n"); +#if 0 /* Completely transfer the debug device to the debug controller */ portsc = read32((unsigned long)&ehci_regs->port_status[debug_port - 1]); portsc &= ~PORT_PE; write32((unsigned long)&ehci_regs->port_status[debug_port - 1], portsc); +#endif dbgp_mdelay(100);

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New patch to review for coreboot: 3c82d4f usbdebug: Fix control messages
by Kyösti Mälkki 14 Aug '13

14 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3867 -gerrit commit 3c82d4f662b68aea475b165db5b7cbaea85eeeae Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 10 10:08:38 2013 +0300 usbdebug: Fix control messages Implementation did not have support for control messages with a write of non-zero length data stage. Implementation did not send out status stage after a read of non-zero length data stage. Change-Id: I16fb9ae39630b975af5461b63d050b9adaccef0f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/usbdebug.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 5f7a457..e84af5b 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -206,6 +206,11 @@ retry: ret = -DBGP_ERR_BAD; } + /* Abort on STALL handshake for endpoint 0.*/ + else if ((lpid == USB_PID_STALL) && (pipe->endpoint == 0x0)) { + ret = -DBGP_ERR_BAD; + } + dbgp_print_data(ehci_debug); return ret; @@ -342,10 +347,10 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i u32 pids, addr, ctrl; struct usb_ctrlrequest req; int read; - int ret; + int ret, ret2; read = (requesttype & USB_DIR_IN) != 0; - if (size > (read ? DBGP_MAX_PACKET:0)) + if (size > DBGP_MAX_PACKET) return -1; /* Compute the control message */ @@ -364,9 +369,8 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i ctrl = read32((unsigned long)&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req)); ctrl |= DBGP_OUT; - ctrl |= DBGP_GO; - /* Send the setup message */ + /* Setup stage */ dbgp_set_data(ehci_debug, &req, sizeof(req)); write32((unsigned long)&ehci_debug->address, addr); write32((unsigned long)&ehci_debug->pids, pids); @@ -374,8 +378,33 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i if (ret < 0) return ret; - /* Read the result */ - ret = dbgp_bulk_read(ehci_debug, pipe, data, size, DBGP_LOOPS); + /* Data stage (optional) */ + if (read && size) { + ret = dbgp_bulk_read(ehci_debug, pipe, data, size, DBGP_LOOPS); + if (ret <= 0) + return ret; + } + if (!read && size) { + ret = dbgp_bulk_write(ehci_debug, pipe, data, size); + } + + /* Status stage in opposite direction */ + pipe->pid = USB_PID_DATA1; + ctrl = read32((unsigned long)&ehci_debug->control); + ctrl = DBGP_LEN_UPDATE(ctrl, 0); + if (read) { + pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT); + ctrl |= DBGP_OUT; + } else { + pids = DBGP_PID_SET(pipe->pid, USB_PID_IN); + ctrl &= ~DBGP_OUT; + } + + write32((unsigned long)&ehci_debug->pids, pids); + ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, DBGP_LOOPS); + if (ret2 < 0) + return ret2; + return ret; }

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New patch to review for coreboot: 7b0358e usbdebug: Dump low-level protocol details
by Kyösti Mälkki 14 Aug '13

14 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3866 -gerrit commit 7b0358e979c7065d8c40f749abf5a355f1bc587b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 10 10:50:43 2013 +0300 usbdebug: Dump low-level protocol details Dumping these EHCI host controller registers is useful to solve problems with debug devices. Change-Id: I0610cecca57b1b952d4f87211dd00c8c0bc398b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/usbdebug.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 6e60950..5f7a457 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -61,10 +61,12 @@ struct ehci_debug_info { }; #if CONFIG_DEBUG_USBDEBUG +static void dbgp_print_data(struct ehci_dbg_port *ehci_debug); static int dbgp_enabled(void); # define dprintk(LEVEL, args...) \ do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0) #else +# define dbgp_print_data(x) do {} while(0) # define dprintk(LEVEL, args...) do {} while(0) #endif @@ -133,6 +135,9 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) break; } while (--loop > 0); + dprintk(BIOS_SPEW, "dbgp: godone (%d @ %4d) ctrl=%08x\n", + loop ? 0 : -1, 1000000-loop, ctrl); + if (!loop) return -1; @@ -152,15 +157,24 @@ static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pi unsigned ctrl, int loop) { u32 rd_ctrl, rd_pids; + u32 ctrl_prev = 0, pids_prev = 0; u8 lpid; int ret; + dprintk(BIOS_SPEW, "dbgp: start (0 @ %4d) ctrl=%08x\n", loop, ctrl | DBGP_GO); retry: write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO); ret = dbgp_wait_until_complete(ehci_debug); rd_ctrl = read32((unsigned long)&ehci_debug->control); rd_pids = read32((unsigned long)&ehci_debug->pids); + if (rd_ctrl != ctrl_prev || rd_pids != pids_prev) { + ctrl_prev = rd_ctrl; + pids_prev = rd_pids; + dprintk(BIOS_SPEW, "dbgp: status (%d @ %4d) ctrl=%08x pids=%08x\n", + ret, loop, rd_ctrl, rd_pids); + } + if (ret < 0) { if (ret == -DBGP_ERR_BAD && --loop > 0) goto retry; @@ -192,6 +206,8 @@ retry: ret = -DBGP_ERR_BAD; } + dbgp_print_data(ehci_debug); + return ret; } @@ -224,6 +240,25 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size) bytes[i] = (hi >> (8*(i - 4))) & 0xff; } +#if CONFIG_DEBUG_USBDEBUG +static void dbgp_print_data(struct ehci_dbg_port *ehci_debug) +{ + u32 ctrl = read32((unsigned long)&ehci_debug->control); + u32 lo = read32((unsigned long)&ehci_debug->data03); + u32 hi = read32((unsigned long)&ehci_debug->data47); + int len = DBGP_LEN(ctrl); + if (len) { + int i; + dprintk(BIOS_SPEW, "dbgp: buf:"); + for (i = 0; i < 4 && i < len; i++) + dprintk(BIOS_SPEW, " %02x", (lo >> (8*i)) & 0xff); + for (; i < 8 && i < len; i++) + dprintk(BIOS_SPEW, " %02x", (hi >> (8*(i - 4))) & 0xff); + dprintk(BIOS_SPEW, "\n"); + } +} +#endif + static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe, const char *bytes, int size) {

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New patch to review for coreboot: f411906 usbdebug: Use separate data toggle for each pipe
by Kyösti Mälkki 14 Aug '13

14 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3865 -gerrit commit f4119062b48cb990ca249af9706f40a60d5d28d4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 10 10:50:38 2013 +0300 usbdebug: Use separate data toggle for each pipe USB defines a mechanism to detect certain cases of lost handshakes using an alternating data sequence number, referred to as data toggling. This patch fixes each pipe to have its own tracking of the data toggle state. Change-Id: I62420bdaeadd0842da3189428a37eeb10c646900 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/usbdebug.c | 45 ++++++++++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 1576752..6e60950 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -41,6 +41,7 @@ struct dbgp_pipe { u8 devnum; u8 endpoint; + u8 pid; u8 status; u8 bufidx; char buf[8]; @@ -69,10 +70,6 @@ static int dbgp_enabled(void); #define USB_DEBUG_DEVNUM 127 -#define DBGP_DATA_TOGGLE 0x8800 -#define DBGP_PID_UPDATE(x, tok) \ - ((((x) ^ DBGP_DATA_TOGGLE) & 0xffff00) | ((tok) & 0xff)) - #define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f)) /* * USB Packet IDs (PIDs) @@ -154,14 +151,15 @@ static void dbgp_breath(void) static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe, unsigned ctrl, int loop) { - u32 pids, lpid; + u32 rd_ctrl, rd_pids; + u8 lpid; int ret; retry: write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO); ret = dbgp_wait_until_complete(ehci_debug); - pids = read32((unsigned long)&ehci_debug->pids); - lpid = DBGP_PID_GET(pids); + rd_ctrl = read32((unsigned long)&ehci_debug->control); + rd_pids = read32((unsigned long)&ehci_debug->pids); if (ret < 0) { if (ret == -DBGP_ERR_BAD && --loop > 0) @@ -169,16 +167,29 @@ retry: return ret; } + lpid = DBGP_PID_GET(rd_pids); + + /* If I get an ACK or in-sync DATA PID, we are done. */ + if ((lpid == USB_PID_ACK) || (lpid == pipe->pid)) { + if (DBGP_LEN(rd_ctrl)) + pipe->pid ^= USB_PID_DATA_TOGGLE; + } + /* If the port is getting full or it has dropped data * start pacing ourselves, not necessary but it's friendly. */ - if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET)) + else if (lpid == USB_PID_NYET) { dbgp_breath(); + if (--loop > 0) + goto retry; + ret = -DBGP_ERR_BAD; + } - /* If I get a NACK reissue the transmission */ - if (lpid == USB_PID_NAK) { + /* If I get a NACK or out-of-sync DATA PID, reissue the transmission. */ + else if ((lpid == USB_PID_NAK) || (lpid == (pipe->pid ^ USB_PID_DATA_TOGGLE))) { if (--loop > 0) goto retry; + ret = -DBGP_ERR_BAD; } return ret; @@ -223,14 +234,11 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *p return -1; addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint); - - pids = read32((unsigned long)&ehci_debug->pids); - pids = DBGP_PID_UPDATE(pids, USB_PID_OUT); + pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT); ctrl = read32((unsigned long)&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl |= DBGP_OUT; - ctrl |= DBGP_GO; dbgp_set_data(ehci_debug, bytes, size); write32((unsigned long)&ehci_debug->address, addr); @@ -257,14 +265,11 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi return -1; addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint); - - pids = read32((unsigned long)&ehci_debug->pids); - pids = DBGP_PID_UPDATE(pids, USB_PID_IN); + pids = DBGP_PID_SET(pipe->pid, USB_PID_IN); ctrl = read32((unsigned long)&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl &= ~DBGP_OUT; - ctrl |= DBGP_GO; write32((unsigned long)&ehci_debug->address, addr); write32((unsigned long)&ehci_debug->pids, pids); @@ -317,8 +322,9 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i pipe->devnum = devnum; pipe->endpoint = 0; + pipe->pid = USB_PID_DATA0; addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint); - pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP); + pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP); ctrl = read32((unsigned long)&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req)); @@ -586,6 +592,7 @@ try_next_port: /* Prepare endpoint pipes. */ for (i=1; i<DBGP_MAX_ENDPOINTS; i++) { info->ep_pipe[i].devnum = USB_DEBUG_DEVNUM; + info->ep_pipe[i].pid = USB_PID_DATA0; } info->ep_pipe[DBGP_CONSOLE_EPOUT].endpoint = dbgp_desc.bDebugOutEndpoint; info->ep_pipe[DBGP_CONSOLE_EPIN].endpoint = dbgp_desc.bDebugInEndpoint;

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coreboot-gerrit August 2013