coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 81c70fb dmp/vortex86ex: Initialize Reatek ALC262 audio codec
by gerrit＠coreboot.org 13 Aug '13

13 Aug '13

the following patch was just integrated into master: commit 81c70fb142326fe9e5ac5391cdd45f93c984e3e6 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Aug 13 16:37:56 2013 +0800 dmp/vortex86ex: Initialize Reatek ALC262 audio codec Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone did not work. With the new logic it does. Now line-in,line-out and microphone all work. The verb data table is generated by Realtek. Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3855 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> See http://review.coreboot.org/3855 for details. -gerrit

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Patch set updated for coreboot: 75bb09e dmp/vortex86ex: Initialize Reatek ALC262 audio codec
by Andrew Wu 13 Aug '13

13 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3855 -gerrit commit 75bb09e60b88e400965ff00bf7b85e0b144fd82c Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Aug 13 16:37:56 2013 +0800 dmp/vortex86ex: Initialize Reatek ALC262 audio codec Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone did not work. With the new logic it does. Now line-in,line-out and microphone all work. The verb data table is generated by Realtek. Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/hda_verb.h | 107 ++++++++++++++++++++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 +++ src/southbridge/dmp/vortex86ex/Kconfig | 1 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 29 ++++++++ 5 files changed, 146 insertions(+) diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} static void mainboard_enable(device_t dev) { + verb_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Kconfig b/src/southbridge/dmp/vortex86ex/Kconfig index e12477c..1da75fa 100644 --- a/src/southbridge/dmp/vortex86ex/Kconfig +++ b/src/southbridge/dmp/vortex86ex/Kconfig @@ -19,4 +19,5 @@ config SOUTHBRIDGE_DMP_VORTEX86EX bool + select AZALIA_PLUGIN_SUPPORT select HAVE_HARD_RESET diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..6ad9ba4 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia_device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +/* RDC HD audio controller */ +static const struct pci_driver rdc_audio __pci_driver = { + .ops = &default_azalia_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};

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New patch to review for coreboot: 0eef6b0 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F
by Bruce Griffith 13 Aug '13

13 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3857 -gerrit commit 0eef6b01c15ca03d6ff7ff84d96f9389d715a189 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Mon Jul 8 18:19:08 2013 -0600 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 56 ++++++++++++++-------- 1 file changed, 35 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 5eccf43..70633f2 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1135,27 +1135,41 @@ u32 map_oprom_vendev(u32 vendev) u32 new_vendev=vendev; switch(vendev) { - //case 0x10029900: //FS1r2 - case 0x10029901: //FM2 - case 0x10029903: //FS1r2 - case 0x10029904: //FM2 - case 0x10029906: //FM2 - case 0x10029907: //FP2 - case 0x10029908: //FP2 - case 0x1002990A: //FP2 - case 0x10029910: //FS1r2 - case 0x10029913: //FS1r2 - case 0x10029917: //FP2 - case 0x10029918: //FP2 - case 0x10029919: //FP2 - case 0x10029990: //FS1r2 - case 0x10029991: //FM2 - case 0x10029992: //FS1r2 - case 0x10029993: //FM2 - case 0x10029994: //FP2 - case 0x100299A0: //FS1r2 - case 0x100299A2: //FS1r2 - case 0x100299A4: //FP2 + case 0x10029900: + case 0x10029901: + case 0x10029902: + case 0x10029903: + case 0x10029904: + case 0x10029906: + case 0x10029907: + case 0x10029908: + case 0x1002990A: + case 0x1002990B: + case 0x1002990C: + case 0x1002990D: + case 0x1002990E: + case 0x1002990F: + case 0x10029910: + case 0x10029913: + case 0x10029917: + case 0x10029918: + case 0x10029919: + case 0x1002991C: + case 0x10029990: + case 0x10029991: + case 0x10029992: + case 0x10029993: + case 0x10029994: + case 0x10029995: + case 0x10029996: + case 0x10029997: + case 0x10029998: + case 0x10029999: + case 0x1002999A: + case 0x1002999B: + case 0x100299A0: + case 0x100299A2: + case 0x100299A4: new_vendev=0x10029900; break; }

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New patch to review for coreboot: e9eb37d AMD AGESA: Remove INVD instruction when transitioning from CAR
by Bruce Griffith 13 Aug '13

13 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3856 -gerrit commit e9eb37d1b5ccbb78ed88a90d4e07d1af5615e4a1 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Mon Aug 12 01:53:13 2013 -0600 AMD AGESA: Remove INVD instruction when transitioning from CAR The AMD AGESA function to move the stack from cache-as-ram to actual RAM doesn't need any help. The current implementation has an INVD instruction just before cache-as-RAM is torn down. It isn't needed for Trinity processors and makes Kabini boot unreliable. Change-Id: I0688b3183371a9b14da6ff3303fa27c5147d59cd Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> --- src/cpu/amd/agesa/cache_as_ram.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index c645a1e..449cf69 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -85,6 +85,7 @@ stop: disable_cache_as_ram: /* Save return stack */ + movd 0(%esp), %xmm1 movd %esp, %xmm0 /* Disable cache */ @@ -92,8 +93,6 @@ disable_cache_as_ram: orl $CR0_CacheDisable, %eax movl %eax, %cr0 - invd - AMD_DISABLE_STACK /* enable cache */ @@ -103,7 +102,9 @@ disable_cache_as_ram: xorl %eax, %eax /* Restore the return stack */ + wbinvd movd %xmm0, %esp + movd %xmm1, (%esp) ret cache_as_ram_setup_out:

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Patch set updated for coreboot: 6af5fa0 AMD Hudson: Add wrapper functions to enable LPC Super I/O ports
by Bruce Griffith 13 Aug '13

13 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3842 -gerrit commit 6af5fa0ee0ea0a22ef0f92056c3b4be7a8e2a966 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Mon Jul 29 20:59:06 2013 -0600 AMD Hudson: Add wrapper functions to enable LPC Super I/O ports The current method for AMD platforms is to add 0xCD6/0xCD7 calls I/O writes into the mainboard code. Wrapper code was added at some point to enable Port 80s using a function. This change does the same, providing a call to enable the Super I/O ports with a similar function [hudson_lpc_superio()]. Change-Id: I796c0b2321af07da1b15645ba6d541fea614112f Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/early_setup.c | 46 ++++++++++++++---- src/southbridge/amd/agesa/hudson/hudson.c | 65 +++++++++++++------------- src/southbridge/amd/agesa/hudson/hudson.h | 55 ++++++++++++++++++++-- 3 files changed, 119 insertions(+), 47 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..89523d4 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -29,20 +29,46 @@ #include <cbmem.h> #include "hudson.h" -void hudson_lpc_port80(void) +static device_t hudson_lpc_enable(void) { - u8 byte; + #define PMxEC_LPC_GATING_REG 0xEC + #define PMxEC_LPC_ENABLE_VALUE (1 << 0) + #define LPC_BUS_NUMBER 0 + #define LPC_DEVICE_NUMBER 0x14 + #define LPC_FUNCTION_NUMBER 3 + device_t dev; /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + pm_iowrite( + PMxEC_LPC_GATING_REG, + pm_ioread(PMxEC_LPC_GATING_REG) | PMxEC_LPC_ENABLE_VALUE + ); + + /* Locate the LPC controller (0x1022, 0x780E) */ + dev = PCI_DEV(LPC_BUS_NUMBER, LPC_DEVICE_NUMBER, LPC_FUNCTION_NUMBER); + + return dev; +} + + +void hudson_lpc_superio(void) +{ + const device_t dev = hudson_lpc_enable(); + u8 byte; + + /* Enable Super I/O configuration in LPC configuration space. */ + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */ + pci_write_config8(dev, 0x48, byte); +} + +void hudson_lpc_port80(void) +{ + const device_t dev = hudson_lpc_enable(); + u8 byte; + + /* Enable port 80 LPC decode in LPC configuration space. */ byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..7729c40 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -53,6 +53,38 @@ void set_cbmem_toc(struct cbmem_entry *toc) } } +//inline static void pmio_write_index(u16 port_base, u8 reg, u8 value) +//{ +// outb(reg, port_base); +// outb(value, port_base + 1); +//} +// +//inline static u8 pmio_read_index(u16 port_base, u8 reg) +//{ +// outb(reg, port_base); +// return inb(port_base + 1); +//} +// +//void pm_iowrite(u8 reg, u8 value) +//{ +// pmio_write_index(PM_INDEX, reg, value); +//} +// +//u8 pm_ioread(u8 reg) +//{ +// return pmio_read_index(PM_INDEX, reg); +//} +// +//void pm2_iowrite(u8 reg, u8 value) +//{ +// pmio_write_index(PM2_INDEX, reg, value); +//} +// +//u8 pm2_ioread(u8 reg) +//{ +// return pmio_read_index(PM2_INDEX, reg); +//} +// void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -64,39 +96,6 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) } } -static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} - - void hudson_enable(device_t dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 686dbb5..c7bf7d1 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -20,6 +20,8 @@ #ifndef HUDSON_H #define HUDSON_H +#include <config.h> +#include <arch/io.h> #include <device/pci_ids.h> #include "chip.h" @@ -39,10 +41,10 @@ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ -void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); +//void pm_iowrite(u8 reg, u8 value); +//u8 pm_ioread(u8 reg); +//void pm2_iowrite(u8 reg, u8 value); +//u8 pm2_ioread(u8 reg); void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define REV_HUDSON_A11 0x11 @@ -57,6 +59,7 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #ifdef __PRE_RAM__ +void hudson_lpc_superio(void); void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); @@ -71,4 +74,48 @@ void hudson_enable(device_t dev); void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev); #endif +#if IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7) || IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8) +#define PMIO_OPTIMIZATION_PREFIX __attribute__((optimize("O0"))) +#define PMIO_STORAGE_PREFIX volatile +#else +#define PMIO_OPTIMIZATION_PREFIX +#define PMIO_STORAGE_PREFIX register +#endif + +static inline void PMIO_OPTIMIZATION_PREFIX pmio_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static inline u8 PMIO_OPTIMIZATION_PREFIX pmio_read_index(u16 port_base, u8 reg) +{ + PMIO_STORAGE_PREFIX u8 value; + outb(reg, port_base); + value = inb(port_base + 1); + return value; +} + +static inline void PMIO_OPTIMIZATION_PREFIX pm_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM_INDEX, reg, value); +} + +static inline u8 PMIO_OPTIMIZATION_PREFIX pm_ioread(u8 reg) +{ + PMIO_STORAGE_PREFIX const u8 value = pmio_read_index(PM_INDEX, reg); + return value; +} + +static inline void PMIO_OPTIMIZATION_PREFIX pm2_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM2_INDEX, reg, value); +} + +static inline u8 PMIO_OPTIMIZATION_PREFIX pm2_ioread(u8 reg) +{ + PMIO_STORAGE_PREFIX const u8 value = pmio_read_index(PM2_INDEX, reg); + return value; +} + #endif /* HUDSON_H */

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Patch set updated for coreboot: 9e9ac4a dmp/vortex86ex: Initialize Reatek ALC262 audio codec
by Andrew Wu 13 Aug '13

13 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3855 -gerrit commit 9e9ac4a43c3ce449558aba4475f4090eb2d81d6e Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Aug 13 16:37:56 2013 +0800 dmp/vortex86ex: Initialize Reatek ALC262 audio codec Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone did not work. With the new logic it does. Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/hda_verb.h | 107 ++++++++++++++++++++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 +++ src/southbridge/dmp/vortex86ex/Kconfig | 1 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 29 ++++++++ 5 files changed, 146 insertions(+) diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} static void mainboard_enable(device_t dev) { + verb_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Kconfig b/src/southbridge/dmp/vortex86ex/Kconfig index e12477c..1da75fa 100644 --- a/src/southbridge/dmp/vortex86ex/Kconfig +++ b/src/southbridge/dmp/vortex86ex/Kconfig @@ -19,4 +19,5 @@ config SOUTHBRIDGE_DMP_VORTEX86EX bool + select AZALIA_PLUGIN_SUPPORT select HAVE_HARD_RESET diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..6ad9ba4 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia_device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +/* RDC HD audio controller */ +static const struct pci_driver rdc_audio __pci_driver = { + .ops = &default_azalia_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};

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New patch to review for coreboot: b9f6e0f dmp/vortex86ex: Initialize Reatek ALC262 audio codec
by Andrew Wu 13 Aug '13

13 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3855 -gerrit commit b9f6e0f2576f02d431be212a184829b0c1ff8c8f Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Aug 13 16:37:56 2013 +0800 dmp/vortex86ex: Initialize Reatek ALC262 audio codec Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone does not work. With the new logic it does. Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/hda_verb.h | 107 ++++++++++++++++++++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 +++ src/southbridge/dmp/vortex86ex/Kconfig | 1 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 29 ++++++++ 5 files changed, 146 insertions(+) diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} static void mainboard_enable(device_t dev) { + verb_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Kconfig b/src/southbridge/dmp/vortex86ex/Kconfig index e12477c..1da75fa 100644 --- a/src/southbridge/dmp/vortex86ex/Kconfig +++ b/src/southbridge/dmp/vortex86ex/Kconfig @@ -19,4 +19,5 @@ config SOUTHBRIDGE_DMP_VORTEX86EX bool + select AZALIA_PLUGIN_SUPPORT select HAVE_HARD_RESET diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..6ad9ba4 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia_device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +/* RDC HD audio controller */ +static const struct pci_driver rdc_audio __pci_driver = { + .ops = &default_azalia_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};

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Patch merged into coreboot/master: b7bb70d Add a generic Intel HD audio (Azalia) module azalia_device.c
by gerrit＠coreboot.org 13 Aug '13

13 Aug '13

the following patch was just integrated into master: commit b7bb70d3de1653275413f4b4e88bc01f9c570d48 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Mon Aug 12 20:07:47 2013 +0800 Add a generic Intel HD audio (Azalia) module azalia_device.c This module uses cim_verb_data to detect and initialize HD audio codecs. The module source code is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c. Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3844 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> See http://review.coreboot.org/3844 for details. -gerrit

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Patch merged into coreboot/master: 9361daf Fix some wait_for_valid functions return value from 1 to -1.
by gerrit＠coreboot.org 13 Aug '13

13 Aug '13

the following patch was just integrated into master: commit 9361daf7fdaa6a4fa81c06e4cdfb7b42b2915051 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Aug 2 14:45:03 2013 +0800 Fix some wait_for_valid functions return value from 1 to -1. codec_init expects wait_for_valid returns -1 for timeout, not 1. Change-Id: I0f2a3ebb1934d0adaf13765434526bbc9efca9a3 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> Reviewed-on: http://review.coreboot.org/3843 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3843 for details. -gerrit

1 0

Patch set updated for coreboot: 502f230 Add a generic Intel HD audio (Azalia) module azalia_device.c
by Paul Menzel 13 Aug '13

13 Aug '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3844 -gerrit commit 502f230c36f33e4e736e49b4ac14cc76caf1d467 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Mon Aug 12 20:07:47 2013 +0800 Add a generic Intel HD audio (Azalia) module azalia_device.c This module uses cim_verb_data to detect and initialize HD audio codecs. The module source code is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c. Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/device/Kconfig | 5 + src/device/Makefile.inc | 1 + src/device/azalia_device.c | 276 +++++++++++++++++++++++++++++++++++++ src/include/device/azalia_device.h | 28 ++++ 4 files changed, 310 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index ca2fb33..4087f6f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -226,6 +226,11 @@ config CARDBUS_PLUGIN_SUPPORT depends on PCI default y +config AZALIA_PLUGIN_SUPPORT + bool + depends on PCI + default n + config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" bool diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 9fe156b..96e2cd9 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -8,6 +8,7 @@ ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c +ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c new file mode 100644 index 0000000..cbc878d --- /dev/null +++ b/src/device/azalia_device.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/azalia_device.h> +#include <arch/io.h> +#include <delay.h> + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u32 reg32; + int count; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* clear STATESTS bits (BAR + 0xE)[2:0] */ + reg32 = read32(base + 0x0E); + reg32 |= 7; + write32(base + 0x0E, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(base + 0x0E); + } while ((reg32 != 0) && --count); + /* Timeout occured */ + if (!count) + goto no_codec; + + /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 0) == -1) + goto no_codec; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + 0xe); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); + return 0; +} + +const u32 *cim_verb_data = NULL; +u32 cim_verb_data_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev)); + printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid); + + int idx = 0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx + 3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 25; + + write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY); + while (timeout--) { + udelay(1); + } + timeout = 50; + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == + HDA_ICII_VALID) + return 0; + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) + return; + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) + return; + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "azalia_audio: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + + for (i = 2; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } +} + +void azalia_audio_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + + res = find_resource(dev, 0x10); + if (!res) + return; + + // NOTE this will break as soon as the azalia_audio get's a bar above + // 4G. Is there anything we can do about it? + base = (u32) res->base; + printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", + codec_mask); + codecs_init(dev, base, codec_mask); + } +} + +struct pci_operations azalia_audio_pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations default_azalia_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_audio_init, + .scan_bus = 0, + .ops_pci = &azalia_audio_pci_ops, +}; diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h new file mode 100644 index 0000000..10bc77d --- /dev/null +++ b/src/include/device/azalia_device.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DEVICE_AZALIA_H +#define DEVICE_AZALIA_H + +#include <device/device.h> + +void azalia_audio_init(struct device *dev); +extern struct device_operations default_azalia_audio_ops; + +#endif /* DEVICE_AZALIA_H */

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coreboot-gerrit August 2013