coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: da940c5 Make EARLY_CONSOLE optional
by gerrit＠coreboot.org 07 Aug '13

07 Aug '13

the following patch was just integrated into master: commit da940c58357eb45232d808a334879474c33be886 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 31 20:52:04 2013 +0300 Make EARLY_CONSOLE optional This change brings back the possibility to disable console output while in romstage, like before commit d2f45c65. For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM CONSOLE do not work correctly for romstage due the way cache-as-ram is set up, but might already work for ramstage. Change-Id: Id8d830e02a18129af419d3b5860866acf315d531 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3846 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3846 for details. -gerrit

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Patch set updated for coreboot: df1cb64 dmp/vortex86ex: Initialize Reatek ALC262 audio codec.
by Andrew Wu 07 Aug '13

07 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3844 -gerrit commit df1cb640ba8c00296125b89bd38569f660f4de13 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Aug 7 19:45:38 2013 +0800 dmp/vortex86ex: Initialize Reatek ALC262 audio codec. Added azalia_device.c : A generic Intel HD audio (Azalia) module. It is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/device/Kconfig | 5 + src/device/Makefile.inc | 1 + src/device/azalia_device.c | 276 ++++++++++++++++++++++++++++ src/include/device/azalia_device.h | 28 +++ src/mainboard/dmp/vortex86ex/hda_verb.h | 107 +++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 + src/southbridge/dmp/vortex86ex/Kconfig | 1 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 29 +++ 9 files changed, 456 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index ca2fb33..4087f6f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -226,6 +226,11 @@ config CARDBUS_PLUGIN_SUPPORT depends on PCI default y +config AZALIA_PLUGIN_SUPPORT + bool + depends on PCI + default n + config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" bool diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 9fe156b..96e2cd9 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -8,6 +8,7 @@ ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c +ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c new file mode 100644 index 0000000..cbc878d --- /dev/null +++ b/src/device/azalia_device.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/azalia_device.h> +#include <arch/io.h> +#include <delay.h> + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u32 reg32; + int count; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* clear STATESTS bits (BAR + 0xE)[2:0] */ + reg32 = read32(base + 0x0E); + reg32 |= 7; + write32(base + 0x0E, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(base + 0x0E); + } while ((reg32 != 0) && --count); + /* Timeout occured */ + if (!count) + goto no_codec; + + /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 0) == -1) + goto no_codec; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + 0xe); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); + return 0; +} + +const u32 *cim_verb_data = NULL; +u32 cim_verb_data_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev)); + printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid); + + int idx = 0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx + 3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 25; + + write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY); + while (timeout--) { + udelay(1); + } + timeout = 50; + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == + HDA_ICII_VALID) + return 0; + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) + return; + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) + return; + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "azalia_audio: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + + for (i = 2; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } +} + +void azalia_audio_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + + res = find_resource(dev, 0x10); + if (!res) + return; + + // NOTE this will break as soon as the azalia_audio get's a bar above + // 4G. Is there anything we can do about it? + base = (u32) res->base; + printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", + codec_mask); + codecs_init(dev, base, codec_mask); + } +} + +struct pci_operations azalia_audio_pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations default_azalia_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_audio_init, + .scan_bus = 0, + .ops_pci = &azalia_audio_pci_ops, +}; diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h new file mode 100644 index 0000000..10bc77d --- /dev/null +++ b/src/include/device/azalia_device.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DEVICE_AZALIA_H +#define DEVICE_AZALIA_H + +#include <device/device.h> + +void azalia_audio_init(struct device *dev); +extern struct device_operations default_azalia_audio_ops; + +#endif /* DEVICE_AZALIA_H */ diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} static void mainboard_enable(device_t dev) { + verb_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Kconfig b/src/southbridge/dmp/vortex86ex/Kconfig index e12477c..1da75fa 100644 --- a/src/southbridge/dmp/vortex86ex/Kconfig +++ b/src/southbridge/dmp/vortex86ex/Kconfig @@ -19,4 +19,5 @@ config SOUTHBRIDGE_DMP_VORTEX86EX bool + select AZALIA_PLUGIN_SUPPORT select HAVE_HARD_RESET diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..6ad9ba4 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia_device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +/* RDC HD audio controller */ +static const struct pci_driver rdc_audio __pci_driver = { + .ops = &default_azalia_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};

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Patch merged into coreboot/master: cec611a AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER`
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit cec611a0ea6dc3bb79e409f3f49a58ec1db81dc1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 30 04:17:37 2013 -0600 AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER` Copied from a similar commit for Family 10h AGESA [1] Remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments [2] fc47bfa Revert "AMD f14 vendorcode: Fix warning" Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> See http://review.coreboot.org/3840 for details. -gerrit

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Patch merged into coreboot/master: 5697df2 AMD AGESA: Add missing breaks to switch statement in one file
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit 5697df2a84b52f0979d4807fc293dea311e46662 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:14:14 2013 -0600 AMD AGESA: Add missing breaks to switch statement in one file This is the same patch as an earlier one applied to family 15 [1]. Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". [1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ... Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> See http://review.coreboot.org/3839 for details. -gerrit

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Patch merged into coreboot/master: ee7cd8d AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit ee7cd8d85d3339291d8f5e72d2d35798164ac0bb Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Tue Jul 23 21:43:52 2013 -0600 AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override) Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3819 for details. -gerrit

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Patch merged into coreboot/master: 4e08a95 AMD Olive Hill: Change SB800 references to Yangtze
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit 4e08a95d2601d7b9ec05f0cb15746d7afb7100d9 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Sun Jul 7 02:04:16 2013 -0600 AMD Olive Hill: Change SB800 references to Yangtze Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3815 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> See http://review.coreboot.org/3815 for details. -gerrit

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Patch merged into coreboot/master: effc8d0 AMD Olive Hill: Add HUDSON_LEGACY_FREE flag
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit effc8d087d56fbdd79fabe77c30146f1e0edb2a7 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Aug 6 03:50:28 2013 -0600 AMD Olive Hill: Add HUDSON_LEGACY_FREE flag Olive Hill does not have a Super I/O or keyboard controller. Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3848 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> See http://review.coreboot.org/3848 for details. -gerrit

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Patch merged into coreboot/master: 2b56e85 AMD Olive Hill: Remove default VBIOS vendor/device ID
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit 2b56e85a50a6383480a5f4d696ff51b04c72a9a6 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Mon Jul 8 11:33:45 2013 -0600 AMD Olive Hill: Remove default VBIOS vendor/device ID The VBIOS device ID is set by processor family using the map_oprom_vendev() function in the northbridge code. There is rarely a reason why this should be overridden by the mainboard. Since Kabini includes a default VBIOS vendor/device ID in the northbridge Kconfig code, remove the setting from the Olive Hill mainboard settings. Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3816 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3816 for details. -gerrit

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New patch to review for coreboot: f6108d9 AMD Olive Hill: Add HUDSON_LEGACY_FREE flag
by Bruce Griffith 06 Aug '13

06 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3848 -gerrit commit f6108d96cd121604c78a49ec83271d163bfe72a8 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Aug 6 03:50:28 2013 -0600 AMD Olive Hill: Add HUDSON_LEGACY_FREE flag Olive Hill does not have a Super I/O or keyboard controller. Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 05d6a53..78b3514 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -93,6 +93,10 @@ config ONBOARD_VGA_IS_PRIMARY bool default y +config HUDSON_LEGACY_FREE + bool + default y + config WARNINGS_ARE_ERRORS bool default n

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Patch set updated for coreboot: a04801e AMD Olive Hill: Remove default VBIOS vendor/device ID
by Bruce Griffith 06 Aug '13

06 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3816 -gerrit commit a04801e9dab01c2fcd05ae0d5406370252bd76ed Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Mon Jul 8 11:33:45 2013 -0600 AMD Olive Hill: Remove default VBIOS vendor/device ID The VBIOS device ID is set by processor family using the map_oprom_vendev() function in the northbridge code. There is rarely a reason why this should be overridden by the mainboard. Since Kabini includes a default VBIOS vendor/device ID in the northbridge Kconfig code, remove the setting from the Olive Hill mainboard settings. Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 20acba9..05d6a53 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -93,10 +93,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config VGA_BIOS_ID - string - default "1002,9832" - config WARNINGS_ARE_ERRORS bool default n

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coreboot-gerrit August 2013