coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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247 discussions

New patch to review for coreboot: 269b4ec usbdebug: Fix AMD cimx/sb700 cimx/sb800
by Kyösti Mälkki 09 Aug '13

09 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3849 -gerrit commit 269b4ec09e2163583ea368a8258a9c2e3ce9e6a1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 9 02:24:05 2013 +0300 usbdebug: Fix AMD cimx/sb700 cimx/sb800 These Kconfig entries were forgotten from the commit that re-enabled usbdebug for these southbridges. Change-Id: Ia17f1dd3340408da7c033c2c949404d2636bed44 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb700/Kconfig | 9 +++++++++ src/southbridge/amd/cimx/sb800/Kconfig | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 0a22296..570f3c2 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -49,6 +49,15 @@ config ACPI_SCI_IRQ default 0x9 help Set SCI IRQ to 9. + +config EHCI_BAR + hex + default 0xfef00000 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb700/bootblock.c" diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 92027b1..8ccbe4d 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -205,6 +205,14 @@ config SB800_FWM_POSITION endif #SB800_IMC_FWM +config EHCI_BAR + hex + default 0xfef00000 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 + choice prompt "Fan Control" default SB800_NO_FAN_CONTROL

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Patch set updated for coreboot: a630311 usbdebug: Add option for verbose logging of connection
by Kyösti Mälkki 09 Aug '13

09 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3387 -gerrit commit a630311beb05c3f79e36e6932800d61ed46aef2b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 6 10:46:37 2013 +0300 usbdebug: Add option for verbose logging of connection Add option to log changes in USB 2.0 EHCI debug port connection. For romstage move usbdebug as the last initialised console so one actually can see these messages. Init order of consoles in ramstage is undetermined and unchanged. Change-Id: I3aceec8a93064bd952886839569e9f5beb6c5720 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 10 ++++++++++ src/console/console.c | 6 +++--- src/lib/usbdebug.c | 11 ++--------- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f65c8e3..ce4488d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -937,6 +937,16 @@ config DEBUG_SPI_FLASH help This option enables additional SPI flash related debug messages. +config DEBUG_USBDEBUG + bool "Output verbose USB 2.0 EHCI debug dongle messages" + default n + depends on USBDEBUG + help + This option enables additional USB 2.0 debug dongle related messages. + + Select this to debug the connection of usbdebug dongle. Note that + you need some other working console to receive the messages. + if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8 # Only visible with the right southbridge and loglevel. config DEBUG_INTEL_ME diff --git a/src/console/console.c b/src/console/console.c index 6ebcd8b..b2b06b3 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -104,9 +104,6 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_USBDEBUG - usbdebug_init(); -#endif #if CONFIG_CONSOLE_SERIAL uart_init(); #endif @@ -122,6 +119,9 @@ void console_init(void) #if CONFIG_SPKMODEM spkmodem_init(); #endif +#if CONFIG_USBDEBUG + usbdebug_init(); +#endif static const char console_test[] = "\n\ncoreboot-" diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 0d50201..9e6fcac 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -57,19 +57,12 @@ struct ehci_debug_info { struct dbgp_pipe ep_pipe[DBGP_MAX_ENDPOINTS]; }; -/* Set this to 1 to debug the start-up of EHCI debug port hardware. You need - * to modify console_init() to initialise some other console before usbdebug - * to receive the printk lines from here. - * There will be no real usbdebug console output while DBGP_DEBUG is set. - */ -#define DBGP_DEBUG 0 -#if DBGP_DEBUG +#if CONFIG_DEBUG_USBDEBUG # define dbgp_printk(fmt_arg...) printk(BIOS_DEBUG, fmt_arg) #else -#define dbgp_printk(fmt_arg...) do {} while(0) +# define dbgp_printk(fmt_arg...) do {} while(0) #endif - #define USB_DEBUG_DEVNUM 127 #define DBGP_DATA_TOGGLE 0x8800

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Patch set updated for coreboot: 3a43ad1 dmp/vortex86ex: Initialize Reatek ALC262 audio codec
by Paul Menzel 08 Aug '13

08 Aug '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3844 -gerrit commit 3a43ad109526f5501dda694167bff927e5962e7c Author: Andrew Wu <arw(a)dmp.com.tw> Date: Wed Aug 7 19:45:38 2013 +0800 dmp/vortex86ex: Initialize Reatek ALC262 audio codec Add the generic Intel HD audio (Azalia) module azalia_device.c, which is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c. Hook this up into the DMP Vortex86EX. Before under Windows XP the microphone does not work. With the new logic it does. Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/device/Kconfig | 5 + src/device/Makefile.inc | 1 + src/device/azalia_device.c | 276 ++++++++++++++++++++++++++++ src/include/device/azalia_device.h | 28 +++ src/mainboard/dmp/vortex86ex/hda_verb.h | 107 +++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 + src/southbridge/dmp/vortex86ex/Kconfig | 1 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 29 +++ 9 files changed, 456 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index ca2fb33..4087f6f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -226,6 +226,11 @@ config CARDBUS_PLUGIN_SUPPORT depends on PCI default y +config AZALIA_PLUGIN_SUPPORT + bool + depends on PCI + default n + config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" bool diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 9fe156b..96e2cd9 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -8,6 +8,7 @@ ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c +ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c new file mode 100644 index 0000000..cbc878d --- /dev/null +++ b/src/device/azalia_device.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/azalia_device.h> +#include <arch/io.h> +#include <delay.h> + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u32 reg32; + int count; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* clear STATESTS bits (BAR + 0xE)[2:0] */ + reg32 = read32(base + 0x0E); + reg32 |= 7; + write32(base + 0x0E, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(base + 0x0E); + } while ((reg32 != 0) && --count); + /* Timeout occured */ + if (!count) + goto no_codec; + + /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 0) == -1) + goto no_codec; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + 0xe); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); + return 0; +} + +const u32 *cim_verb_data = NULL; +u32 cim_verb_data_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev)); + printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid); + + int idx = 0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx + 3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 25; + + write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY); + while (timeout--) { + udelay(1); + } + timeout = 50; + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == + HDA_ICII_VALID) + return 0; + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) + return; + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) + return; + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "azalia_audio: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + + for (i = 2; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } +} + +void azalia_audio_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + + res = find_resource(dev, 0x10); + if (!res) + return; + + // NOTE this will break as soon as the azalia_audio get's a bar above + // 4G. Is there anything we can do about it? + base = (u32) res->base; + printk(BIOS_DEBUG, "azalia_audio: base = %08x\n", (u32) base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", + codec_mask); + codecs_init(dev, base, codec_mask); + } +} + +struct pci_operations azalia_audio_pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations default_azalia_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_audio_init, + .scan_bus = 0, + .ops_pci = &azalia_audio_pci_ops, +}; diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h new file mode 100644 index 0000000..10bc77d --- /dev/null +++ b/src/include/device/azalia_device.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DEVICE_AZALIA_H +#define DEVICE_AZALIA_H + +#include <device/device.h> + +void azalia_audio_init(struct device *dev); +extern struct device_operations default_azalia_audio_ops; + +#endif /* DEVICE_AZALIA_H */ diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} static void mainboard_enable(device_t dev) { + verb_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Kconfig b/src/southbridge/dmp/vortex86ex/Kconfig index e12477c..1da75fa 100644 --- a/src/southbridge/dmp/vortex86ex/Kconfig +++ b/src/southbridge/dmp/vortex86ex/Kconfig @@ -19,4 +19,5 @@ config SOUTHBRIDGE_DMP_VORTEX86EX bool + select AZALIA_PLUGIN_SUPPORT select HAVE_HARD_RESET diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..6ad9ba4 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia_device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +/* RDC HD audio controller */ +static const struct pci_driver rdc_audio __pci_driver = { + .ops = &default_azalia_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};

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Patch set updated for coreboot: df9a3fc AMD Fam16: Add OSC method to PCI0
by Paul Menzel 08 Aug '13

08 Aug '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3823 -gerrit commit df9a3fcef74fdeb8b82939eeef495582bfabeb13 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jul 18 10:30:47 2013 -0600 AMD Fam16: Add OSC method to PCI0 This patch is adapted from previously merged changes for Family 14 [1] and Family 15. The _OSC method is required for PCIe devices and an error is logged to dmesg under Linux if _OSC is not found. _OSC is described in chapter 6.2.9 of the ACPI spec v3.0. [1] 00a0e76 AMD Fam14 DSDT: Add OSC method Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 5d3a29c..06b4fe7 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -21,6 +21,25 @@ /* South Bridge */ /* _SB.PCI0 */ +/* Operating System Capabilities Method */ +Method(_OSC,4) +{ + // Create DWord-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } +} + /* Describe the Southbridge devices */ /* 0:11.0 - SATA */

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Patch set updated for coreboot: 174f1ae AMD Fam16: Add OSC method to PCI0
by Bruce Griffith 08 Aug '13

08 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3823 -gerrit commit 174f1aee466e4d5903905bb6b6ed98d555b33855 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jul 18 10:30:47 2013 -0600 AMD Fam16: Add OSC method to PCI0 This patch is adapted from previously merged changes for Family 14 [1] and Family 15. The _OSC method is required for PCIe devices and an error is logged to dmesg under Linux if _OSC is not found. _OSC is described in chapter 6.2.9 of the ACPI spec v3.0. [1] 00a0e76 AMD Fam14 DSDT: Add OSC method Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 5d3a29c..06b4fe7 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -21,6 +21,25 @@ /* South Bridge */ /* _SB.PCI0 */ +/* Operating System Capabilities Method */ +Method(_OSC,4) +{ + // Create DWord-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } +} + /* Describe the Southbridge devices */ /* 0:11.0 - SATA */

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Patch set updated for coreboot: 94b9a25 AMD Fam16: Add OSC method to PCI0
by Bruce Griffith 08 Aug '13

08 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3823 -gerrit commit 94b9a25a45c05bb0f276b08c9df3ae1db811c5ad Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jul 18 10:30:47 2013 -0600 AMD Fam16: Add OSC method to PCI0 This patch is adapted from previously merged changes for Family 14 [1] and Family 15. The _OSC method is required for PCIe devices and an error is logged to dmesg under Linux if _OSC is not found. _OSC is described in chapter 6.2.9 of the ACPI spec v3.0. [1] 00a0e76 AMD Fam14 DSDT: Add OSC method Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 5d3a29c..06b4fe7 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -21,6 +21,25 @@ /* South Bridge */ /* _SB.PCI0 */ +/* Operating System Capabilities Method */ +Method(_OSC,4) +{ + // Create DWord-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } +} + /* Describe the Southbridge devices */ /* 0:11.0 - SATA */

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Patch merged into coreboot/master: 0cc33da ASUS F2A85-M: Split DSDT into common sections (as per Parmer)
by gerrit＠coreboot.org 08 Aug '13

08 Aug '13

the following patch was just integrated into master: commit 0cc33da5530cf2ef776fc9fa2dbb80bb4dc4c830 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Sat Jul 20 14:28:10 2013 -0600 ASUS F2A85-M: Split DSDT into common sections (as per Parmer) Rearranged the F2A85-M DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the F2A85-M dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for F2A85-M. Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3805 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> See http://review.coreboot.org/3805 for details. -gerrit

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Patch merged into coreboot/master: 436a375 AMD Thatcher: Split DSDT into common sections (as per Parmer)
by gerrit＠coreboot.org 08 Aug '13

08 Aug '13

the following patch was just integrated into master: commit 436a3753ec14f8bde3eb3063b6563e32c1dd72e7 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Sat Jul 20 11:20:18 2013 -0600 AMD Thatcher: Split DSDT into common sections (as per Parmer) Rearranged the Thatcher DSDT file to match the functionality found on Parmer. As with the Parmer implementation, the Thatcher dsdt.asl file in the mainboard directory contains only #include references to the appropriate files. As with Parmer, some include files have no content but are left as a template for other platforms and as placeholders for completing the ACPI implementation for Thatcher. Change-Id: Ie44a32959cc547840914365e872416d4624d33df Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin(a)se-eng.com> See http://review.coreboot.org/3804 for details. -gerrit

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Patch merged into coreboot/master: 0010bf6 usbdebug: Support AMD cimx/sb700 cimx/sb800 once again
by gerrit＠coreboot.org 07 Aug '13

07 Aug '13

the following patch was just integrated into master: commit 0010bf60a63298700292de40e437d5927a73d49f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 11 16:32:01 2013 +0300 usbdebug: Support AMD cimx/sb700 cimx/sb800 once again Support code for sb700 and sb800 existed already, but Kconfig and compile-time issues prevented from enabling USBDEBUG for boards with the affected AMD southbridges. Change-Id: I49e955fcc6e54927320b9dc7f62ea00c55c3cedf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3439 for details. -gerrit

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Patch merged into coreboot/master: 1fd7508 usbdebug: Use __SIMPLE_DEVICE__ on early enable
by gerrit＠coreboot.org 07 Aug '13

07 Aug '13

the following patch was just integrated into master: commit 1fd750812193cbaab7f54696b97a91bf727e87e3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 11 16:32:01 2013 +0300 usbdebug: Use __SIMPLE_DEVICE__ on early enable With USBDEBUG selected, the file is built for both romstage and ramstage. For the ramstage build, we need to explicitly use the simple PCI config operations without devicetree. Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3437 for details. -gerrit

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coreboot-gerrit August 2013