coreboot-gerrit August 2013

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Patch set updated for coreboot: 4e34264 AMD Olive Hill: Change SB800 references to Yangtze
by Bruce Griffith 06 Aug '13

06 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3815 -gerrit commit 4e3426458b4b49ad3f7a55f19533b13e2a655290 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Sun Jul 7 02:04:16 2013 -0600 AMD Olive Hill: Change SB800 references to Yangtze Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/get_bus_conf.c | 30 +++++++++---------- src/mainboard/amd/olivehill/irq_tables.c | 10 +++---- src/mainboard/amd/olivehill/mptable.c | 48 +++++++++++++++--------------- src/mainboard/amd/olivehill/romstage.c | 2 +- 4 files changed, 45 insertions(+), 45 deletions(-) diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index fca2625..0d379d5 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -30,8 +30,8 @@ * and acpi_tables busnum is default. */ u8 bus_isa; -u8 bus_sb800[3]; -u32 apicid_sb800; +u8 bus_yangtze[3]; +u32 apicid_yangtze; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -43,7 +43,7 @@ u32 pci1234x[] = { }; u32 bus_type[256]; -u32 sbdn_sb800; +u32 sbdn_yangtze; static u32 get_bus_conf_done = 0; @@ -98,10 +98,10 @@ void get_bus_conf(void) pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - sbdn_sb800 = 0; + sbdn_yangtze = 0; for (i = 0; i < 3; i++) { - bus_sb800[i] = 0; + bus_yangtze[i] = 0; } for (i = 0; i < 256; i++) { @@ -110,34 +110,34 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; - /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + /* yangtze */ + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); if (dev) { - bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - for (j = bus_sb800[1]; j < bus_isa; j++) + for (j = bus_yangtze[1]; j < bus_isa; j++) bus_type[j] = 1; } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); if (dev) { - bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } } - for (j = bus_sb800[2]; j < bus_isa; j++) + for (j = bus_yangtze[2]; j < bus_isa; j++) bus_type[j] = 1; /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + apicid_yangtze = apicid_base; } diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 2c3b671..9779153 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, } extern u8 bus_isa; -extern u8 bus_sb800[2]; -extern unsigned long sbdn_sb800; +extern u8 bus_yangtze[2]; +extern unsigned long sbdn_yangtze; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = bus_yangtze[0]; + pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 7db7160..118f860 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -30,11 +30,11 @@ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS -extern u8 bus_sb800[3]; +extern u8 bus_yangtze[3]; extern u32 bus_type[256]; -extern u32 sbdn_sb800; -extern u32 apicid_sb800; +extern u32 sbdn_yangtze; +extern u32 apicid_yangtze; u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, @@ -103,10 +103,10 @@ static void *smp_write_config_table(void *v) /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); - apicid_sb800 = IO_APIC_ID; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + apicid_yangtze = IO_APIC_ID; + smp_write_ioapic(mc, apicid_yangtze, 0x21, dword); - smp_write_ioapic(mc, apicid_sb800+1, 0x21, 0xFEC20000); + smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); @@ -160,13 +160,13 @@ static void *smp_write_config_table(void *v) /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -195,26 +195,26 @@ static void *smp_write_config_table(void *v) /* PCI slots */ /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14); + PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15); + PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16); + PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15); + PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16); + PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17); + PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16); + PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17); + PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14); + PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12); + PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13); + PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 8a967e1..afb701c 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39);

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Patch merged into coreboot/master: aea318f AMD Kabini: Add "const" modifier to AGESA function parameters
by gerrit＠coreboot.org 06 Aug '13

06 Aug '13

the following patch was just integrated into master: commit aea318f35d13e1859efa82f664df01c8c13657c1 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Mon Jul 29 02:34:26 2013 -0600 AMD Kabini: Add "const" modifier to AGESA function parameters Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. This same change was made for AMD Trinity APUs (Family15tn) [1]. [1] 283ba78 AGESA: Add "const" modifier to function parameters Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3837 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/3837 for details. -gerrit

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Patch merged into coreboot/master: abebe80 AMD SATA: Correct "them implement" to "then implement" in comments
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit abebe80161a03c65b22088c7151f01b6681559a5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Apr 28 14:44:08 2013 +0200 AMD SATA: Correct "them implement" to "then implement" in comments This changelist was cherry-picked from merged community code for Parmer [1] and the paths modified so that the Parmer modification is applied against Olive Hill. [1] 0086162 AMD SATA: Correct _them implement_ ... in comments Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3841 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3841 for details. -gerrit

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Patch merged into coreboot/master: 76db07e AMD Kabini: Add map_oprom() function for Vendor/Device IDs
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 76db07e8c20b1e419ceeaf14eb23c7675839067a Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Sun Jul 7 02:06:53 2013 -0600 AMD Kabini: Add map_oprom() function for Vendor/Device IDs Change-Id: I14285f0677003fbf8b9b112207af202658807894 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3806 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3806 for details. -gerrit

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Patch merged into coreboot/master: 17933e8 AMD Olive Hill: Enable HDMI audio setting in build options
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 17933e8bc17f04a876a51198dabcc2363f4ee334 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Jul 10 01:26:26 2013 -0600 AMD Olive Hill: Enable HDMI audio setting in build options Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3814 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3814 for details. -gerrit

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Patch merged into coreboot/master: 5912125 AMD Olive Hill: Eliminate unnecessary memory copy
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 5912125dffcbe8a1b1ab4d1198c5ff2c9bc0771c Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Jul 10 22:24:47 2013 -0600 AMD Olive Hill: Eliminate unnecessary memory copy Eliminate an unnecessary copy of the DDI descriptor list and the PCIe port descriptor list. As descriptor tables, these tables do not need dynamic updating and should be used from ROM without runtime copying. There will be a corresponding patch for AGESA that adds CONST modifiers to function parameters that are pass-by-reference "IN" values (read-only pointers). Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3818 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3818 for details. -gerrit

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Patch merged into coreboot/master: 80cf7d5 AMD Olive Hill: Add new AMD mainboard using Kabini processor
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 80cf7d5956283b5c79b293d2ffac82f329f6203c Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Jul 9 17:42:43 2013 +0800 AMD Olive Hill: Add new AMD mainboard using Kabini processor Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3784 for details. -gerrit

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Patch merged into coreboot/master: 37a1d6c AMD Hudson/Yangtze: Enable support for SATA port multipliers
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 37a1d6c9552b267c06c471cced5928d2385767e2 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Tue Jul 23 11:50:12 2013 -0600 AMD Hudson/Yangtze: Enable support for SATA port multipliers This patch sets a bit in the Yangtze southbridge to enable the extra protocol necessary to handle port multiplier chips. This has been turned on during most of Kabini development without any notable impact. Olive Hill has an optional daughter board that incorporates Silicon Image Steel Vines chips. This change has been tested with and without the daughter board. This change can be regression tested using any Hudson-based motherboard, although it has no impact on boards with discreet Hudson/Bolton southbridges. This was tested for impact on SATA performance in the absence of a port multiplier using the IOZone benchmarks within the Phoronix Test Suite. A SATA 3 hard drive (6.0 Gbps) and an SSD were connected to the ports on Olive Hill without using the port multiplier card. The test results contained more run-to-run variation within the same configuration than was seen in the aggregate results comparing the interface with and without the port multiplier protocol additions. In other words, the test had less accuracy than the impact caused by turning on port multiplier support. Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3808 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3808 for details. -gerrit

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Patch merged into coreboot/master: 9157145 AMD Kabini: Modify Hudson southbridge to support new AMD processor
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 915714501bc411f83717b41ebf269fc82a5e9657 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Jul 9 17:32:42 2013 +0800 AMD Kabini: Modify Hudson southbridge to support new AMD processor Yangtze uses Hudson AGESA wrapper code but has some changes. The changes are necessary and have no effects on Hudson. Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3783 for details. -gerrit

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Patch merged into coreboot/master: 3e32cc0 AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
by gerrit＠coreboot.org 05 Aug '13

05 Aug '13

the following patch was just integrated into master: commit 3e32cc00d1984e7a0d01039577e5aa6ae3b2aa81 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Jul 9 17:16:20 2013 +0800 AMD Kabini: Add northbridge AGESA wrapper (new AMD processor) src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also changed because these two files depend on F16kb northbridge macros Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3782 for details. -gerrit

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coreboot-gerrit August 2013