coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 8bfd3e2 Make EARLY_CONSOLE optional
by Kyösti Mälkki 02 Aug '13

02 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3846 -gerrit commit 8bfd3e281e5db6bed5dd1f85ad17eac748a5ad4f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 31 20:52:04 2013 +0300 Make EARLY_CONSOLE optional This change brings back the possibility to disable console output while in romstage, like before commit d2f45c65. For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM CONSOLE do not work correctly for romstage due the way cache-as-ram is set up, but might already work for ramstage. Change-Id: Id8d830e02a18129af419d3b5860866acf315d531 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 1 + src/cpu/Kconfig | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 013b72f..1d050f7 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -9,6 +9,7 @@ config BOOTBLOCK_CONSOLE config EARLY_CONSOLE bool "Enable early (pre-RAM) console output." + default y if CACHE_AS_RAM default n help Use console during early (pre-RAM) boot stages diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 9d268e4..e48fe87 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -20,7 +20,6 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE

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Patch set updated for coreboot: cab76b5 AMD AGESA: Place CAR_GLOBAL in BSP stack
by Kyösti Mälkki 02 Aug '13

02 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3832 -gerrit commit cab76b5048dd2bda53d257afac85d8039a1eeb9d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 29 10:16:14 2013 +0300 AMD AGESA: Place CAR_GLOBAL in BSP stack Use BSP CPU's stack space to store CAR GLOBALS for the duration of romstage before CAR migration. NOTE: Such globals can only be accessed from BSP CPU due the way AMD platform has memory architecture set up. Change-Id: Ica4700433268f484ce69a24d934732f9cfd4ba41 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index c660470..a20280f 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -50,6 +50,17 @@ config UDELAY_LAPIC_FIXED_FSB int default 200 +# DCACHE_RAM_BASE and DCACHE_RAM_SIZE here need to match with the +# implementation of BSP_STACK under AGESA vendorcode. + +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig

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Patch set updated for coreboot: 61339b0 usbdebug: Support AMD cimx/sb700 cimx/sb800 once again
by Kyösti Mälkki 02 Aug '13

02 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3439 -gerrit commit 61339b0cf5e514c9196ea3f5d40476a8f07d653a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 11 16:32:01 2013 +0300 usbdebug: Support AMD cimx/sb700 cimx/sb800 once again Support code for sb700 and sb800 existed already, but Kconfig and compile-time issues prevented from enabling USBDEBUG for boards with the affected AMD southbridges. Change-Id: I49e955fcc6e54927320b9dc7f62ea00c55c3cedf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb700/Kconfig | 1 + src/southbridge/amd/cimx/sb700/Makefile.inc | 3 ++- src/southbridge/amd/cimx/sb800/Kconfig | 1 + src/southbridge/amd/cimx/sb800/Makefile.inc | 4 ++-- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 97cdf1c..0a22296 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB700 bool select IOAPIC + select HAVE_USBDEBUG select AMD_SB_CIMX select HAVE_HARD_RESET diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc index 268629f..f6f0d86 100644 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -30,4 +30,5 @@ ramstage-y += reset.c ramstage-y += smbus.c ramstage-y += lpc.c - +romstage-$(CONFIG_USBDEBUG) += ../../sb700/enable_usbdebug.c +ramstage-$(CONFIG_USBDEBUG) += ../../sb700/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index b82409d..92027b1 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 bool default n select IOAPIC + select HAVE_USBDEBUG select AMD_SB_CIMX select HAVE_HARD_RESET diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 831cc2e..0ff9e1e 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -34,8 +34,8 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c -romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c +ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c ramstage-y += smbus.c ramstage-y += lpc.c

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Patch set updated for coreboot: 1dbc848 usbdebug: Use __SIMPLE_DEVICE__ on early enable
by Kyösti Mälkki 02 Aug '13

02 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3437 -gerrit commit 1dbc8487fea12d35960d2b5763976fbaa9818163 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 11 16:32:01 2013 +0300 usbdebug: Use __SIMPLE_DEVICE__ on early enable With USBDEBUG selected, the file is built for both romstage and ramstage. For the ramstage build, we need to explicitly use the simple PCI config operations without devicetree. Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 4 ++++ src/southbridge/amd/sb600/enable_usbdebug.c | 3 +++ src/southbridge/amd/sb700/enable_usbdebug.c | 3 +++ src/southbridge/amd/sb800/enable_usbdebug.c | 4 ++++ src/southbridge/nvidia/ck804/enable_usbdebug.c | 3 +++ src/southbridge/nvidia/mcp55/enable_usbdebug.c | 3 +++ src/southbridge/sis/sis966/enable_usbdebug.c | 3 +++ 7 files changed, 23 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 128885a..147056d 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -16,6 +16,10 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h> diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 305362f..0e4b424 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h> diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 2a7fc38..f0efe41 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h> diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 28a1665..8b80b37 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -16,6 +16,10 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h> diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 659fdc6..54b534e 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -21,6 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h> diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index f753c78..ec06653 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -21,6 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h> diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index 78a3838..1ff04df 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -23,6 +23,9 @@ /* TODO: Check whether this actually works (might be copy-paste leftover). */ +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <usbdebug.h>

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New patch to review for coreboot: 33e21f6 Revert "intel/i945: Use MMCONF_SUPPORT_DEFAULT"
by Gerd Hoffmann 02 Aug '13

02 Aug '13

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3845 -gerrit commit 33e21f68d713f325a2c24661cae946c05f7570f7 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Aug 2 09:40:35 2013 +0200 Revert "intel/i945: Use MMCONF_SUPPORT_DEFAULT" This reverts commit 032c23db08e6f0c6a2937092edafa26339aa4921. Lenovo T60 is broken in master. Bisected down to this patch. Reverting it unbreaks T60 support. Change-Id: Ie58f5f8d390775cbc031205f95308a86d9695b1c Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/ibase/mb899/Kconfig | 1 + src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/roda/rk886ex/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 6 ------ src/northbridge/intel/i945/bootblock.c | 24 ------------------------ src/northbridge/intel/i945/early_init.c | 1 + 10 files changed, 8 insertions(+), 30 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 3fdf6f7..e7f3c95 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -36,6 +36,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_SLIC + select MMCONF_SUPPORT select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select GFXUMA diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 36353b3..6b3bdfa 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 0a9de1a..cc9ceb5 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index e8b7225..0dd28da 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME + select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_1024 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index e5d17b8..1ea0e96 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select MMCONF_SUPPORT select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1a765fb..fdd9e20 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select MMCONF_SUPPORT select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 2113deb..84a8543 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select MMCONF_SUPPORT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 135cbe3..fbc9988 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -24,8 +24,6 @@ if NORTHBRIDGE_INTEL_I945 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER @@ -34,10 +32,6 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/i945/bootblock.c" - config VGA_BIOS_ID string default "8086,27a2" diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c deleted file mode 100644 index 4571446..0000000 --- a/src/northbridge/intel/i945/bootblock.c +++ /dev/null @@ -1,24 +0,0 @@ -#include <arch/io.h> - -/* Just re-define this instead of including i945.h. It blows up romcc. */ -#define PCIEXBAR 0x48 - -static void bootblock_northbridge_init(void) -{ - uint32_t reg; - - /* - * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to - * to true. That way all subsequent non-explicit config accesses use - * MCFG. This code also assumes that bootblock_northbridge_init() is - * the first thing called in the non-asm boot block code. The final - * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. - * - * The PCIEXBAR is assumed to live in the memory mapped IO space under - * 4GiB. - */ - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); -} diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 946f7aa..435d64d 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -172,6 +172,7 @@ static void i945_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);

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New patch to review for coreboot: 90d3933 Initialize Vortex86EX Realtek ALC262 audio codec.
by Andrew Wu 02 Aug '13

02 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3844 -gerrit commit 90d393308a85ccccfe01455e471ad32ad5cdbc33 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Aug 2 15:22:29 2013 +0800 Initialize Vortex86EX Realtek ALC262 audio codec. southbridge/dmp/vortex86ex/audio.c is based on southbridge/intel/sch/audio.c Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/mainboard/dmp/vortex86ex/hda_verb.h | 107 ++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 314 ++++++++++++++++++++++++++++ 4 files changed, 430 insertions(+) diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +} static void mainboard_enable(device_t dev) { + verb_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..7eede07 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u32 reg32; + int count; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* clear STATESTS bits (BAR + 0xE)[2:0] */ + reg32 = read32(base + 0x0E); + reg32 |= 7; + write32(base + 0x0E, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(base + 0x0E); + } while ((reg32 != 0) && --count); + /* Timeout occured */ + if (!count) + goto no_codec; + + /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 0) == -1) + goto no_codec; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + 0xe); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "sch_audio: No codec!\n"); + return 0; +} + +const u32 *cim_verb_data = NULL; +u32 cim_verb_data_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + printk(BIOS_DEBUG, "sch_audio: dev=%s\n", dev_path(dev)); + printk(BIOS_DEBUG, "sch_audio: Reading viddid=%x\n", viddid); + + int idx = 0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx + 3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 25; + + write32(base + 0x68, 1); + while (timeout--) { + udelay(1); + } + timeout = 50; + while (timeout--) { + u32 reg32 = read32(base + 0x68); + if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) { + + write32(base + 0x68, 2); + return 0; + } + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "sch_audio: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) + return; + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) + return; + + reg32 = read32(base + 0x0); + printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32); + + reg32 = read32(base + 0x4); + printk(BIOS_DEBUG, "sch_audio: OUTPAY: %08x\n", reg32); + reg32 = read32(base + 0x6); + printk(BIOS_DEBUG, "sch_audio: INPAY: %08x\n", reg32); + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "sch_audio: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "sch_audio: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "sch_audio: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "sch_audio: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + + for (i = 2; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } +} + +static void sch_audio_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + u32 reg32; + + res = find_resource(dev, 0x10); + if (!res) + return; + + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MEMORY); + + // NOTE this will break as soon as the sch_audio get's a bar above + // 4G. Is there anything we can do about it? + base = (u32) res->base; + printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n", + codec_mask); + codecs_init(dev, base, codec_mask); + } else { + /* No audio codecs found disable HD audio controller */ + pci_write_config32(dev, 0x10, 0); + pci_write_config32(dev, PCI_COMMAND, 0); + reg32 = pci_read_config32(dev, 0xFC); + pci_write_config32(dev, 0xFC, reg32 | 1); + } +} + +static void sch_audio_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations sch_audio_pci_ops = { + .set_subsystem = sch_audio_set_subsystem, +}; + +static struct device_operations sch_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sch_audio_init, + .scan_bus = 0, + .ops_pci = &sch_audio_pci_ops, +}; + +/* SCH audio function */ +static const struct pci_driver sch_audio __pci_driver = { + .ops = &sch_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};

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Patch set updated for coreboot: 09fae63 Fix some wait_for_valid functions return value from 1 to -1.
by Andrew Wu 02 Aug '13

02 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3843 -gerrit commit 09fae63bd9a1894a42a89b2fd416a24b380ac136 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Aug 2 14:45:03 2013 +0800 Fix some wait_for_valid functions return value from 1 to -1. codec_init expects wait_for_valid returns -1 for timeout, not 1. Change-Id: I0f2a3ebb1934d0adaf13765434526bbc9efca9a3 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/amd/sb600/hda.c | 2 +- src/southbridge/amd/sb700/hda.c | 2 +- src/southbridge/amd/sb800/hda.c | 2 +- src/southbridge/intel/sch/audio.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c index 3b118af..26adf11 100644 --- a/src/southbridge/amd/sb600/hda.c +++ b/src/southbridge/amd/sb600/hda.c @@ -208,7 +208,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(u32 base, int addr) diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index 98cb75f..bf4c754 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -130,7 +130,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(u32 base, int addr) diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c index 1be44fb..e2d6960 100644 --- a/src/southbridge/amd/sb800/hda.c +++ b/src/southbridge/amd/sb800/hda.c @@ -132,7 +132,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(u32 base, int addr) diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c index 701c944..f3eb034 100644 --- a/src/southbridge/intel/sch/audio.c +++ b/src/southbridge/intel/sch/audio.c @@ -187,7 +187,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(struct device *dev, u32 base, int addr)

1 0

New patch to review for coreboot: 416fbd6 Some wait_for_valid functions return 1 incorrectly. Fixed to return -1.
by Andrew Wu 02 Aug '13

02 Aug '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3843 -gerrit commit 416fbd60034f1b9fbc09761b4b6a3293ca7854ab Author: Andrew Wu <arw(a)dmp.com.tw> Date: Fri Aug 2 14:45:03 2013 +0800 Some wait_for_valid functions return 1 incorrectly. Fixed to return -1. codec_init expects wait_for_valid returns -1 for timeout, not 1. Change-Id: I0f2a3ebb1934d0adaf13765434526bbc9efca9a3 Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- src/southbridge/amd/sb600/hda.c | 2 +- src/southbridge/amd/sb700/hda.c | 2 +- src/southbridge/amd/sb800/hda.c | 2 +- src/southbridge/intel/sch/audio.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c index 3b118af..26adf11 100644 --- a/src/southbridge/amd/sb600/hda.c +++ b/src/southbridge/amd/sb600/hda.c @@ -208,7 +208,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(u32 base, int addr) diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index 98cb75f..bf4c754 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -130,7 +130,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(u32 base, int addr) diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c index 1be44fb..e2d6960 100644 --- a/src/southbridge/amd/sb800/hda.c +++ b/src/southbridge/amd/sb800/hda.c @@ -132,7 +132,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(u32 base, int addr) diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c index 701c944..f3eb034 100644 --- a/src/southbridge/intel/sch/audio.c +++ b/src/southbridge/intel/sch/audio.c @@ -187,7 +187,7 @@ static int wait_for_valid(u32 base) udelay(1); } - return 1; + return -1; } static void codec_init(struct device *dev, u32 base, int addr)

1 0

Patch set updated for coreboot: d7cc030 AMD Hudson/Yangtze: Enable support for SATA port multipliers
by Bruce Griffith 02 Aug '13

02 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3808 -gerrit commit d7cc030684b9957306a893628456196abf39de1d Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Tue Jul 23 11:50:12 2013 -0600 AMD Hudson/Yangtze: Enable support for SATA port multipliers This patch sets a bit in the Yangtze southbridge to enable the extra protocol necessary to handle port multiplier chips. This has been turned on during most of Kabini development without any notable impact. Olive Hill has an optional daughter board that incorporates Silicon Image Steel Vines chips. This change has been tested with and without the daughter board. This change can be regression tested using any Hudson-based motherboard, although it has no impact on boards with discreet Hudson/Bolton southbridges. This was tested for impact on SATA performance in the absence of a port multiplier using the IOZone benchmarks within the Phoronix Test Suite. A SATA 3 hard drive (6.0 Gbps) and an SSD were connected to the ports on Olive Hill without using the port multiplier card. The test results contained more run-to-run variation within the same configuration than was seen in the aggregate results comparing the interface with and without the port multiplier protocol additions. In other words, the test had less accuracy than the impact caused by turning on port multiplier support. Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/sata.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index bc1cd92..7499370 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -29,7 +29,35 @@ static void sata_init(struct device *dev) { -} +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) + /************************************** + * Configure the SATA port multiplier * + **************************************/ + #define BYTE_TO_DWORD_OFFSET(x) (x/4) + #define AHCI_BASE_ADDRESS_REG 0x24 + #define MISC_CONTROL_REG 0x40 + #define UNLOCK_BIT (1<<0) + #define SATA_CAPABILITIES_REG 0xFC + #define CFG_CAP_SPM (1<<12) + + volatile u32 *ahci_ptr = + (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); + u32 temp; + + /* unlock the write-protect */ + temp = pci_read_config32(dev, MISC_CONTROL_REG); + temp |= UNLOCK_BIT; + pci_write_config32(dev, MISC_CONTROL_REG, temp); + + /* set the SATA AHCI mode to allow port expanders */ + *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; + + /* lock the write-protect */ + temp = pci_read_config32(dev, MISC_CONTROL_REG); + temp &= ~UNLOCK_BIT; + pci_write_config32(dev, MISC_CONTROL_REG, temp); +#endif +}; static struct pci_operations lops_pci = { /* .set_subsystem = pci_dev_set_subsystem, */

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Patch set updated for coreboot: d71234f AMD Hudson: Add wrapper functions to enable LPC Super I/O ports
by Bruce Griffith 02 Aug '13

02 Aug '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3842 -gerrit commit d71234fcb2d422e72b5a5daa61d3e7b65d6de3a4 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Mon Jul 29 20:59:06 2013 -0600 AMD Hudson: Add wrapper functions to enable LPC Super I/O ports The current method for AMD platforms is to add 0xCD6/0xCD7 I/O writes into the mainboard code. Wrapper code was added at some point to enable Port 80s using a function. This change does the same, providing a call to enable the Super I/O ports with a similar function [hudson_lpc_superio()]. Change-Id: I796c0b2321af07da1b15645ba6d541fea614112f Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/early_setup.c | 33 ++++++++++++++++++++------ src/southbridge/amd/agesa/hudson/hudson.h | 1 + 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..df5835c 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -29,17 +29,36 @@ #include <cbmem.h> #include "hudson.h" -void hudson_lpc_port80(void) +static device_t hudson_lpc_enable(void) { - u8 byte; device_t dev; /* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + outb(0xEC, PM_INDEX); + outb(inb(PM_DATA) | 1, PM_DATA); + + /* Locate the LPC controller (0x1002, 0x439D) */ + dev = PCI_DEV(0, 0x14, 3); + + return dev; +} + + +void hudson_lpc_superio(void) +{ + device_t dev = hudson_lpc_enable(); + u8 byte; + + /* Enable Super I/O configuration in pci function 3 configuration space. */ + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */ + pci_write_config8(dev, 0x48, byte); +} + +void hudson_lpc_port80(void) +{ + device_t dev = hudson_lpc_enable(); + u8 byte; /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 686dbb5..7a6ed57 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -57,6 +57,7 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 #ifdef __PRE_RAM__ +void hudson_lpc_superio(void); void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

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coreboot-gerrit August 2013