New patch to review for coreboot: 90d3933 Initialize Vortex86EX Realtek ALC262 audio codec.
Andrew Wu (arw@dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3844
-gerrit
commit 90d393308a85ccccfe01455e471ad32ad5cdbc33 Author: Andrew Wu arw@dmp.com.tw Date: Fri Aug 2 15:22:29 2013 +0800
Initialize Vortex86EX Realtek ALC262 audio codec.
southbridge/dmp/vortex86ex/audio.c is based on southbridge/intel/sch/audio.c
Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu arw@dmp.com.tw --- src/mainboard/dmp/vortex86ex/hda_verb.h | 107 ++++++++++ src/mainboard/dmp/vortex86ex/mainboard.c | 8 + src/southbridge/dmp/vortex86ex/Makefile.inc | 1 + src/southbridge/dmp/vortex86ex/audio.c | 314 ++++++++++++++++++++++++++++ 4 files changed, 430 insertions(+)
diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h new file mode 100644 index 0000000..0556315 --- /dev/null +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks + + /* ===== HDA Codec Subsystem ID Verb-table ===== */ + /* HDA Codec Subsystem ID : 0x10EC0000 */ + 0x00172000, + 0x00172100, + 0x001722ec, + 0x00172310, + + /* ===== Pin Widget Verb-table ===== */ + /* Widget node 0x01 : */ + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + 0x0017ff00, + /* Pin widget 0x11 - S/PDIF-OUT2 */ + 0x01171c00, + 0x01171d00, + 0x01171e00, + 0x01171f40, + /* Pin widget 0x12 - DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + /* Pin widget 0x14 - LINE-OUT (Port-D) */ + 0x01471c10, + 0x01471d41, + 0x01471e01, + 0x01471f01, + /* Pin widget 0x15 - HP-OUT (Port-A) */ + 0x01571cf0, + 0x01571d11, + 0x01571e11, + 0x01571f41, + /* Pin widget 0x16 - MONO-OUT */ + 0x01671cf0, + 0x01671d11, + 0x01671e11, + 0x01671f41, + /* Pin widget 0x18 - MIC1 (Port-B) */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971c30, + 0x01971d91, + 0x01971ea1, + 0x01971f02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01a71c40, + 0x01a71d31, + 0x01a71e81, + 0x01a71f01, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + /* Pin widget 0x1C - CD-IN */ + 0x01c71cf0, + 0x01c71d11, + 0x01c71e11, + 0x01c71f41, + /* Pin widget 0x1D - BEEP-IN */ + 0x01d71c29, + 0x01d71d46, + 0x01d71e35, + 0x01d71f40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01e71c20, + 0x01e71d11, + 0x01e71e56, + 0x01e71f18, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01f71cf0, + 0x01f71d11, + 0x01f71e11, + 0x01f71f41, +}; + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index dfeb5f4..c824963 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -23,9 +23,17 @@ #include <arch/io.h> #include <boot/tables.h> #include <device/pci_def.h> +#include "hda_verb.h" + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); +}
static void mainboard_enable(device_t dev) { + verb_setup(); }
struct chip_operations mainboard_ops = { diff --git a/src/southbridge/dmp/vortex86ex/Makefile.inc b/src/southbridge/dmp/vortex86ex/Makefile.inc index 6d2a921..5471faa 100644 --- a/src/southbridge/dmp/vortex86ex/Makefile.inc +++ b/src/southbridge/dmp/vortex86ex/Makefile.inc @@ -20,3 +20,4 @@ ramstage-y += southbridge.c ramstage-y += hard_reset.c ramstage-y += ide_sd_sata.c +ramstage-y += audio.c diff --git a/src/southbridge/dmp/vortex86ex/audio.c b/src/southbridge/dmp/vortex86ex/audio.c new file mode 100644 index 0000000..7eede07 --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/audio.c @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u32 reg32; + int count; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* clear STATESTS bits (BAR + 0xE)[2:0] */ + reg32 = read32(base + 0x0E); + reg32 |= 7; + write32(base + 0x0E, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(base + 0x0E); + } while ((reg32 != 0) && --count); + /* Timeout occured */ + if (!count) + goto no_codec; + + /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 0) == -1) + goto no_codec; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0] */ + reg32 = read32(base + 0xe); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "sch_audio: No codec!\n"); + return 0; +} + +const u32 *cim_verb_data = NULL; +u32 cim_verb_data_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + printk(BIOS_DEBUG, "sch_audio: dev=%s\n", dev_path(dev)); + printk(BIOS_DEBUG, "sch_audio: Reading viddid=%x\n", viddid); + + int idx = 0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx + 3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while (timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 25; + + write32(base + 0x68, 1); + while (timeout--) { + udelay(1); + } + timeout = 50; + while (timeout--) { + u32 reg32 = read32(base + 0x68); + if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) { + + write32(base + 0x68, 2); + return 0; + } + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "sch_audio: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) + return; + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) + return; + + reg32 = read32(base + 0x0); + printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32); + + reg32 = read32(base + 0x4); + printk(BIOS_DEBUG, "sch_audio: OUTPAY: %08x\n", reg32); + reg32 = read32(base + 0x6); + printk(BIOS_DEBUG, "sch_audio: INPAY: %08x\n", reg32); + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "sch_audio: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "sch_audio: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "sch_audio: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "sch_audio: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + + for (i = 2; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } +} + +static void sch_audio_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + u32 reg32; + + res = find_resource(dev, 0x10); + if (!res) + return; + + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MEMORY); + + // NOTE this will break as soon as the sch_audio get's a bar above + // 4G. Is there anything we can do about it? + base = (u32) res->base; + printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n", + codec_mask); + codecs_init(dev, base, codec_mask); + } else { + /* No audio codecs found disable HD audio controller */ + pci_write_config32(dev, 0x10, 0); + pci_write_config32(dev, PCI_COMMAND, 0); + reg32 = pci_read_config32(dev, 0xFC); + pci_write_config32(dev, 0xFC, reg32 | 1); + } +} + +static void sch_audio_set_subsystem(device_t dev, unsigned vendor, + unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations sch_audio_pci_ops = { + .set_subsystem = sch_audio_set_subsystem, +}; + +static struct device_operations sch_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sch_audio_init, + .scan_bus = 0, + .ops_pci = &sch_audio_pci_ops, +}; + +/* SCH audio function */ +static const struct pci_driver sch_audio __pci_driver = { + .ops = &sch_audio_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = 0x3010, +};
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Andrew Wu