coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

1 participants
247 discussions

Patch merged into coreboot/master: c66f1cb Include boot_cpu.c for romstage builds
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit c66f1cbdae6dced6410c0fc108cb0a1e3b3aa1e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 12 16:09:00 2013 +0300 Include boot_cpu.c for romstage builds ROMCC boards were left unmodified. Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3853 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3853 for details. -gerrit

1 0

Patch merged into coreboot/master: f040858 payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variable
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit f040858ec31ffef5b746bb9856be6395a20c98ce Author: Peter Stuge <peter(a)stuge.se> Date: Tue Jul 9 19:43:09 2013 +0200 payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variable This allows mainboards to preconfigure a ps2-keyboard-spinup timeout when SeaBIOS is chosen as the payload. The Kconfig option can be changed manually if CONFIG_EXPERT is set. Change-Id: I5732b18ef04f4bdef6236f35039656ad02011aec Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/3734 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3734 for details. -gerrit

1 0

Patch merged into coreboot/master: 3bfd5b8 cbfstool: Add an add-int command that adds a raw 64-bit integer CBFS file
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 3bfd5b8252c4a188988c7f3441a3ba608ff46822 Author: Peter Stuge <peter(a)stuge.se> Date: Tue Jul 9 19:39:13 2013 +0200 cbfstool: Add an add-int command that adds a raw 64-bit integer CBFS file This simplifies storing SeaBIOS parameters in CBFS. Change-Id: I301644ba0d7a9cb5917c37a3b4ceddfa59e34e77 Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/3733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3733 for details. -gerrit

1 0

Patch set updated for coreboot: 31028e7 Sandybridge/Ivybridge: Unify and fix Kconfig defaults
by Patrick Georgi 15 Aug '13

15 Aug '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3830 -gerrit commit 31028e71910f23eb5c00bcbecdbc1926123292dc Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 29 13:00:03 2013 -0700 Sandybridge/Ivybridge: Unify and fix Kconfig defaults Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/Kconfig | 53 ++----------------------------- 1 file changed, 2 insertions(+), 51 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 1834b71..5b6285f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -31,7 +31,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX -if NORTHBRIDGE_INTEL_SANDYBRIDGE +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE config VGA_BIOS_ID string @@ -39,53 +39,8 @@ config VGA_BIOS_ID config CACHE_MRC_SIZE_KB int - default 256 - -# FIXME: build from rom size -config MRC_CACHE_BASE - hex - default 0xff800000 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x1ec000 - -config MRC_CACHE_SIZE - hex - depends on !CHROMEOS - default 0x10000 - -config DCACHE_RAM_BASE - hex - default 0xff7f0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -endif - -if NORTHBRIDGE_INTEL_IVYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0166" - -config CACHE_MRC_SIZE_KB - int default 512 -# FIXME: build from rom size -config MRC_CACHE_BASE - hex - default 0xff800000 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x370000 - config MRC_CACHE_SIZE hex depends on !CHROMEOS @@ -99,10 +54,6 @@ config DCACHE_RAM_SIZE hex default 0x20000 -endif - -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE - config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c" @@ -122,7 +73,7 @@ config HAVE_MRC config MRC_FILE string "Intel System Agent path and filename" depends on HAVE_MRC - default "systemagent-r6.bin" + default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" help The path and filename of the file to use as System Agent binary.

1 0

New patch to review for coreboot: 3beceac emulation/qemu-i440fx: style cleanup
by Patrick Georgi 15 Aug '13

15 Aug '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3873 -gerrit commit 3beceac1be1d5378c97026d9ce5fda80e8e88c2c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Aug 15 20:41:15 2013 +0200 emulation/qemu-i440fx: style cleanup Drop unused and commented out variable, and fix a comment while at it. Change-Id: I1bd7d10aca949c8579433ea1c91264fd816a3fb4 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index c08d59e..2ea4a68 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -54,7 +54,6 @@ static void cpu_pci_domain_read_resources(struct device *dev) { u16 nbid = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID); int i440fx = (nbid == 0x1237); -// int q35 = (nbid == 0x29c0); struct resource *res; unsigned long tomk = 0, high; int idx = 10; @@ -94,7 +93,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) if (i440fx) { /* Reserve space for the IOAPIC. This should be in - * the Southbridge, but I couldn't tell which device + * the southbridge, but I couldn't tell which device * to put it in. */ res = new_resource(dev, 2); res->base = IO_APIC_ADDR;

1 0

Patch merged into coreboot/master: a4e7057 qemu: fix ioapic reservation
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit a4e70578db9268c4f9847ba43e754f3e95d7a4e5 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri Aug 9 10:02:22 2013 +0200 qemu: fix ioapic reservation The slightly hackish ioapic ressource reservation is needed for i440fx emulation only, for q35 the ich9 southbridge driver handles this just fine. [ Side note: The i440fx chipset emulated by qemu is pimped up with alot of stuff which never existed on real hardware, which leads to tweaks like this one. ] Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3850 for details. -gerrit

1 0

Patch merged into coreboot/master: 1e1a179 ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VD
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 1e1a1798faf9715ceb2bd34b619c3c21f03ce89a Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 2 20:51:15 2013 +0200 ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VD Use the same HD Audio [1] verb table for the Realtek ALC887-VD audio chip as the one set up by the proprietary vendor BIOS. Linux’ ALSA exposes this pin configuration under the virtual filesystem sysfs. /sys/class/sound/hwC1D0/init_pin_configs The script `alsa-info.sh` [2][3] is able to decode the table. Only one channel audio playback (rear connectors) is tested [4], which worked already before. [1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html [3] http://alsa-project.org/main/index.php/Help_To_Debug [4] http://review.coreboot.org/#/c/3170/2//COMMIT_MSG Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3170 for details. -gerrit

1 0

Patch merged into coreboot/master: 1ae7d47 AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 1ae7d475a82327b6a0f26f9ee34308a85c437b24 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat May 4 18:41:54 2013 +0200 AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList` The board name in that variable name is not necessary, as it is not board dependent, that means using the file as a template for making a new coreboot port for another motherboard the variable does not need to be changed, and just increases the code differences between AMD Parmer, AMD Thather and ASUS F2A85-M. So use a generic name. The same was done for AMD Persimmon (and inherited by the LiPPERT FrontRunner/Toucan-AF) in the following commit. commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt Reviewed-on: http://review.coreboot.org/2529 The board name is *not* removed from the `CODEC_ENTRY` variable name as the verb table not only depends on the codec but also on the board [1]. Having the board name in the variable name is a good indicator that the pin configuration needs to be adapted when taking this file as a template for a new port. If it was board independent, a default chip configuration could be used and shared between all boards, which is unfortunately not the case. [1] Unfortunately I was not able to find Jens’ comment in my mail archive and in the Gerrit Web interface. Not sure where it is, but I am sure he made that comment. Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3199 for details. -gerrit

1 0

Patch merged into coreboot/master: dc92d68 w83627hf/acpi: Fix logical device power down in ACPI
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit dc92d682ff8d5d2439f4c5cdc4e449bba6d651bb Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Thu Jul 4 03:41:39 2013 +0200 w83627hf/acpi: Fix logical device power down in ACPI As Nico noticed for the W83627DHG, the power management bits to power down individual logical devices on Winbond superios are named counterintuitively and need to be set when the logical device should be powered. This corrects the power management methods for the W83627HF. Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3605 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3605 for details. -gerrit

1 0

Patch merged into coreboot/master: ec3a462 CBFS: Change how the bss is zeroed when loading a stage.
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit ec3a462d03527b2f4e620f43a5fa8fe518c5dee7 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 04:34:29 2013 -0700 CBFS: Change how the bss is zeroed when loading a stage. For reasons explained in a previous CL, it might be necessary to "load" a file from CBFS in place. The loading code in CBFS was, however, zeroing the area of memory the stage was about to be loaded into. When the CBFS data is located elsewhere this works fine, but when it isn't you end up clobbering the data you're trying to load. Also, there's no reason to zero memory we're about to load something into or have just loaded something into. This change makes it so that we only zero out the portion of the memory between what was loaded/decompressed and the final size of the stage in memory. Change-Id: If34df16bd74b2969583e11ef6a26eb4065842f57 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3579 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3579 for details. -gerrit

1 0

← Newer
1
...
8
9
10
11
12
13
14
...
25
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2013