coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

1 participants
247 discussions

Patch merged into coreboot/master: 0c605a5 CBFS: Change the signature of cbfs_decompress.
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 0c605a5a6cf0b5a7bdaa6068168581dc8fb24d22 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Jul 1 04:57:37 2013 -0700 CBFS: Change the signature of cbfs_decompress. Instead of returning 0 on success and -1 on error, return the decompressed size of the data on success and 0 on error. The decompressed size is useful information to have that was being thrown away in that function. Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3578 for details. -gerrit

1 0

Patch merged into coreboot/master: f31eacc lenovo/t60 lenovo/x60: Default SEABIOS_PS2_TIMEOUT to 3 seconds
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit f31eacca62bb9fda9ed05be941a336163f1ce146 Author: Peter Stuge <peter(a)stuge.se> Date: Tue Jul 9 20:17:28 2013 +0200 lenovo/t60 lenovo/x60: Default SEABIOS_PS2_TIMEOUT to 3 seconds The ThinkPad keyboard controller sometimes needs a while in order to initialize, so let's ask SeaBIOS to wait for it. This change ensures that the internal keyboard always functions correctly on the ThinkPad when coreboot is built with SeaBIOS as payload. Change-Id: I562475ec98b0c1f5d0debf6e9b597748a420f068 Signed-off-by: Peter Stuge <peter(a)stuge.se> Reviewed-on: http://review.coreboot.org/3735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3735 for details. -gerrit

1 0

Patch merged into coreboot/master: 05d3f49 qemu: reserve ports
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 05d3f49fc67f6023f9bc64dbbce56cf4613c4ab9 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Tue Aug 6 10:48:41 2013 +0200 qemu: reserve ports QEMU has a bunch of non-standard virtual devices on various I/O ports. Allocate resources for them so the coreboot resource management knows those ports are used. Change-Id: I51a85967cf2dcd634b0c883210bb52c0c34c8283 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-on: http://review.coreboot.org/3851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3851 for details. -gerrit

1 0

Patch merged into coreboot/master: 42e11f5 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 42e11f5a03480f6bc4a7dc54dd87bea4e850042a Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Mon Jul 8 18:19:08 2013 -0600 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3857 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/3857 for details. -gerrit

1 0

Patch merged into coreboot/master: 9e8690b AMD Fam16: Add OSC method to PCI0
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 9e8690b43f4978760ba9464ffdd63d36506fc06a Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jul 18 10:30:47 2013 -0600 AMD Fam16: Add OSC method to PCI0 The _OSC method is used to tell the OS what capabilities it can take control over from the firmware. This method is described in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4 inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and returns a Capabilites Buffer the same size as the input Buffer. This Buffer is generally 3 Dwords long consisting of an Errors Dword, a Supported Capabilities Dword, and a Control Dword. The OS will request control of certain capabilities and the firmware must grant or deny control of those features. We do not want to have control over anything so let the OS control as much as it can. The _OSC method is required for PCIe devices. During Linux boot, an error is logged to dmesg if _OSC is not found. Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3823 for details. -gerrit

1 0

Patch merged into coreboot/master: 6cf5c8e AMD Fam16: Add secondary bus number to CRES method
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit 6cf5c8ee655ab80d897b7a86bfc4dbde6fb462d5 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jul 18 10:16:31 2013 -0600 AMD Fam16: Add secondary bus number to CRES method Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the AMD FCH ACPI code. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses. Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3822 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3822 for details. -gerrit

1 0

Patch merged into coreboot/master: ac90d80 AMD Kabini: Split DSDT into common sections
by gerrit＠coreboot.org 15 Aug '13

15 Aug '13

the following patch was just integrated into master: commit ac90d8013a26d99df21cb555bb313506ce32979c Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Wed Jul 17 15:14:59 2013 -0600 AMD Kabini: Split DSDT into common sections Split the Family16 (Kabini) DSDT file into logical regions. Olive Hill is the only mainboard and Kabini is the only NB/CPU currently using Family16 AGESA code. Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3821 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3821 for details. -gerrit

1 0

New patch to review for coreboot: 23b8a54 usbdebug: Change debug port scanning
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3872 -gerrit commit 23b8a54f351f15740215154504b5e8bdba24c2b6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 12 20:40:37 2013 +0300 usbdebug: Change debug port scanning On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 25 ++++++++-------------- src/lib/usbdebug.c | 19 ++++++++++++---- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 1 - src/southbridge/amd/sb600/Kconfig | 4 ---- src/southbridge/amd/sb600/enable_usbdebug.c | 3 --- src/southbridge/amd/sb700/enable_usbdebug.c | 5 ----- src/southbridge/amd/sb800/enable_usbdebug.c | 1 - src/southbridge/intel/i82801gx/Kconfig | 4 ---- src/southbridge/intel/i82801ix/Kconfig | 4 ---- src/southbridge/nvidia/ck804/enable_usbdebug.c | 3 --- src/southbridge/nvidia/mcp55/enable_usbdebug.c | 3 --- src/southbridge/sis/sis966/enable_usbdebug.c | 3 --- 12 files changed, 24 insertions(+), 51 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 1d050f7..71e5725 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -134,9 +134,6 @@ config HAVE_USBDEBUG def_bool n config USBDEBUG - def_bool n - -config USBDEBUG bool "USB 2.0 EHCI debug dongle support" default n depends on HAVE_USBDEBUG @@ -157,25 +154,21 @@ config USBDEBUG If unsure, say N. -# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges -# as those hardcode the physical USB port to be used as Debug Port to 1. -# It cannot be changed by coreboot. config USBDEBUG_DEFAULT_PORT int "Default USB port to use as Debug Port" - default 1 - depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600 + default 0 + depends on USBDEBUG help - This option selects which physical USB port coreboot will try to - use as EHCI Debug Port first (valid values are: 1-15). + Selects which physical USB port usbdebug dongle is connected to. + Setting of 0 means to scan possible ports starting from 1. - If coreboot doesn't detect an EHCI Debug Port dongle on this port, - it will try all the other ports one after the other. This will take - a few seconds of time though, and thus slow down the booting process. + Intel platforms have hardwired the debug port location and this + setting makes no difference there. Hence, if you select the correct port here, you can speed up - your boot time. Which USB port number (1-15) refers to which - actual port on your mainboard (potentially also USB pin headers - on your mainboard) is highly board-specific, and you'll likely + your boot time. Which USB port number refers to which actual + port on your mainboard (potentially also USB pin headers on + your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error. # TODO: Deps? diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 9e6fcac..cde19a1 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -417,8 +417,13 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; - memset(&info->ep_pipe, 0, sizeof (info->ep_pipe)); + + if (CONFIG_USBDEBUG_DEFAULT_PORT > 0) + set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT); + else + set_debug_port(1); + try_next_time: port_map_tried = 0; @@ -591,6 +596,7 @@ err: //return ret; next_debug_port: +#if CONFIG_USBDEBUG_DEFAULT_PORT==0 port_map_tried |= (1 << (debug_port - 1)); new_debug_port = ((debug_port-1 + 1) % n_ports) + 1; if (port_map_tried != ((1 << n_ports) - 1)) { @@ -598,10 +604,15 @@ next_debug_port: goto try_next_port; } if (--playtimes) { - //set_debug_port(new_debug_port); - set_debug_port(debug_port); + set_debug_port(new_debug_port); goto try_next_time; } +#else + if (0) + goto try_next_port; + if (--playtimes) + goto try_next_time; +#endif return -10; } @@ -706,7 +717,7 @@ int usbdebug_init(void) struct ehci_debug_info *dbg_info = dbgp_ehci_info(); #if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE - enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + enable_usbdebug(0); #endif return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 147056d..bd62842 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -56,5 +56,4 @@ void enable_usbdebug(unsigned int port) EHCI_BAR_INDEX, CONFIG_EHCI_BAR); pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - set_debug_port(port); } diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 4ae4641..fe9468d 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET hex default 0xe0 -config USBDEBUG_DEFAULT_PORT - int - default 0 - choice prompt "SATA Mode" default SATA_MODE_IDE diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index d20c8c4..40c53ae 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -36,9 +36,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ - /* Select the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 00eb4d9..6c46071 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -57,9 +57,4 @@ void enable_usbdebug(unsigned int port) /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - /* - * Select the requested physical USB port (1-15) as the Debug Port. - * Must be called after the EHCI BAR has been set up (see above). - */ - set_debug_port(port); } diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 8b80b37..d17e955 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -56,5 +56,4 @@ void enable_usbdebug(unsigned int port) EHCI_BAR_INDEX, CONFIG_EHCI_BAR); pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - set_debug_port(port); } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d4a6baa..62c6b43 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 -config USBDEBUG_DEFAULT_PORT - int - default 1 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801gx/bootblock.c" diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index dd07dac..8a4a53e 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -37,10 +37,6 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 -config USBDEBUG_DEFAULT_PORT - int - default 1 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801ix/bootblock.c" diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 90890e6..d65fea2 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -52,9 +52,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index 069344b..f629c50 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -46,9 +46,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index f38fe90..04384ba 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -48,9 +48,6 @@ void enable_usbdebug(unsigned int port) { pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Mark the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); - /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);

1 0

New patch to review for coreboot: cac2ecf Add pnp_devfn_t and use with __SIMPLE_DEVICE__
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3871 -gerrit commit cac2ecf29b40118857cfeaa4c975dc4dcf400b34 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 20 20:25:21 2013 +0300 Add pnp_devfn_t and use with __SIMPLE_DEVICE__ Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PNP access functions for ramstage using the inlined functions from romstage. Change-Id: I2a0bd8194acaf9c4c7252a29376eec363397e3a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 26 +++++++++++++++++--------- src/include/device/device.h | 1 + 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 8591465..50264f6 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -214,6 +214,7 @@ static inline int log2f(int value) typedef u32 device_t; typedef u32 pci_devfn_t; +typedef u32 pnp_devfn_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore @@ -284,53 +285,60 @@ static inline pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus } /* Generic functions for pnp devices */ -static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) +static inline __attribute__((always_inline)) void pnp_write_config(pnp_devfn_t dev, uint8_t reg, uint8_t value) { unsigned port = dev >> 8; outb(reg, port ); outb(value, port +1); } -static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) +static inline __attribute__((always_inline)) uint8_t pnp_read_config(pnp_devfn_t dev, uint8_t reg) { unsigned port = dev >> 8; outb(reg, port); return inb(port +1); } -static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) +static inline __attribute__((always_inline)) +void pnp_set_logical_device(pnp_devfn_t dev) { unsigned device = dev & 0xff; pnp_write_config(dev, 0x07, device); } -static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) +static inline __attribute__((always_inline)) +void pnp_set_enable(pnp_devfn_t dev, int enable) { pnp_write_config(dev, 0x30, enable?0x1:0x0); } -static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) +static inline __attribute__((always_inline)) +int pnp_read_enable(pnp_devfn_t dev) { return !!pnp_read_config(dev, 0x30); } -static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) +static inline __attribute__((always_inline)) +void pnp_set_iobase(pnp_devfn_t dev, unsigned index, unsigned iobase) { pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); pnp_write_config(dev, index + 1, iobase & 0xff); } -static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) +static inline __attribute__((always_inline)) +uint16_t pnp_read_iobase(pnp_devfn_t dev, unsigned index) { return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); } -static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) +static inline __attribute__((always_inline)) +void pnp_set_irq(pnp_devfn_t dev, unsigned index, unsigned irq) { pnp_write_config(dev, index, irq); } -static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) +static inline __attribute__((always_inline)) +void pnp_set_drq(pnp_devfn_t dev, unsigned index, unsigned drq) { pnp_write_config(dev, index, drq & 0xff); } diff --git a/src/include/device/device.h b/src/include/device/device.h index 1056be7..c0e6e0f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -12,6 +12,7 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; typedef u32 pci_devfn_t; +typedef u32 pnp_devfn_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations;

1 0

Patch set updated for coreboot: f7b1d7b intel usbdebug: Add choice of EHCI controller
by Kyösti Mälkki 15 Aug '13

15 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3440 -gerrit commit f7b1d7b50a8572867349aeb6917a861d51e9c81f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 13 13:51:14 2013 +0300 intel usbdebug: Add choice of EHCI controller Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/bd82x6x/Kconfig | 2 +- src/southbridge/intel/common/usb_debug.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index bf020f8..c2720ef 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -30,7 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select IOAPIC select HAVE_HARD_RESET - select HAVE_USBDEBUG + select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 3fed2ab..9fe22cd 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -28,7 +28,32 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - return PCI_DEV(0, 0x1d, 7); + u32 class; + pci_devfn_t dev; + +#if CONFIG_HAVE_USBDEBUG_OPTIONS + if (hcd_idx==2) + dev = PCI_DEV(0, 0x1a, 0); + else + dev = PCI_DEV(0, 0x1d, 0); +#else + dev = PCI_DEV(0, 0x1d, 7); +#endif + + class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; +#if CONFIG_HAVE_USBDEBUG_OPTIONS + if (class != PCI_EHCI_CLASSCODE) { + /* If we enter here before RCBA programming, EHCI function may + * appear with the highest function number instead. + */ + dev |= PCI_DEV(0, 0, 7); + class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; + } +#endif + if (class != PCI_EHCI_CLASSCODE) + return 0; + + return dev; } /* Required for successful build, but currently empty. */ @@ -41,6 +66,10 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { u32 dbgctl; + /* Bail out. No console to complain in. */ + if (!dev) + return; + /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, base);

1 0

← Newer
1
...
9
10
11
12
13
14
15
...
25
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2013