coreboot-gerrit August 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 27a2e2e Fix up Stumpy/Lumpy PEI data for system agent r6
by Patrick Georgi 17 Aug '13

17 Aug '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3831 -gerrit commit 27a2e2e6c49301be6f95e0cca34996dd64fbd1a1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 29 14:02:06 2013 -0700 Fix up Stumpy/Lumpy PEI data for system agent r6 Change-Id: I79937fd1671af23184ab830d5ba6242c8067d944 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/lumpy/romstage.c | 46 ++++++++++++++++----------------- src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/romstage.c | 3 ++- 4 files changed, 26 insertions(+), 25 deletions(-) diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 778ce71..91dc3b6 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_MEC1308 select DRIVERS_GENERIC_IOAPIC select EARLY_CBMEM_INIT + select HAVE_MRC config MAINBOARD_DIR string diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index be1411e..449a81c 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -146,33 +146,33 @@ void main(unsigned long bist) .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; #endif - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0x50, 0x00,0xf0,0x00 }, - .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, - .ec_present = 1, + pei_version: PEI_VERSION, + mchbar: DEFAULT_MCHBAR, + dmibar: DEFAULT_DMIBAR, + epbar: DEFAULT_EPBAR, + pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + smbusbar: SMBUS_IO_BASE, + wdbbar: 0x4000000, + wdbsize: 0x1000, + hpet_address: CONFIG_HPET_ADDRESS, + rcba: DEFAULT_RCBABASE, + pmbase: DEFAULT_PMBASE, + gpiobase: DEFAULT_GPIOBASE, + thermalbase: 0xfed08000, + system_type: 0, // 0 Mobile, 1 Desktop/Server + tseg_size: CONFIG_SMM_TSEG_SIZE, + spd_addresses: { 0xa0, 0x00,0x00,0x00 }, + ts_addresses: { 0x30, 0x00, 0x00, 0x00 }, + ec_present: 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .usb_port_config = { + dimm_channel0_disabled: 2, + dimm_channel1_disabled: 2, + max_ddr3_freq: 1333, + usb_port_config: { { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ @@ -188,8 +188,6 @@ void main(unsigned long bist) { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, - .spd_data = { - } }; typedef const uint8_t spd_blob[256]; diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 5300be5..f4f8e4d 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F select EARLY_CBMEM_INIT + select HAVE_MRC config MAINBOARD_DIR string diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index f64e860..daa8d55 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -198,7 +198,7 @@ void main(unsigned long bist) thermalbase: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0x50, 0x00,0x52,0x00 }, + spd_addresses: { 0xa0, 0x00,0xa4,0x00 }, ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, ec_present: 0, // 0 = leave channel enabled @@ -207,6 +207,7 @@ void main(unsigned long bist) // 3 = disable dimm 0+1 on channel dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, + max_ddr3_freq: 1333, usb_port_config: { { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */

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Patch set updated for coreboot: 5125154 Sandybridge/Ivybridge: Unify and fix Kconfig defaults
by Patrick Georgi 17 Aug '13

17 Aug '13

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3830 -gerrit commit 5125154dc2a171a787a72cd51e8c613508bd8fda Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 29 13:00:03 2013 -0700 Sandybridge/Ivybridge: Unify and fix Kconfig defaults Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/Kconfig | 53 ++----------------------------- 1 file changed, 2 insertions(+), 51 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 1834b71..5b6285f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -31,7 +31,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX -if NORTHBRIDGE_INTEL_SANDYBRIDGE +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE config VGA_BIOS_ID string @@ -39,53 +39,8 @@ config VGA_BIOS_ID config CACHE_MRC_SIZE_KB int - default 256 - -# FIXME: build from rom size -config MRC_CACHE_BASE - hex - default 0xff800000 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x1ec000 - -config MRC_CACHE_SIZE - hex - depends on !CHROMEOS - default 0x10000 - -config DCACHE_RAM_BASE - hex - default 0xff7f0000 - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -endif - -if NORTHBRIDGE_INTEL_IVYBRIDGE - -config VGA_BIOS_ID - string - default "8086,0166" - -config CACHE_MRC_SIZE_KB - int default 512 -# FIXME: build from rom size -config MRC_CACHE_BASE - hex - default 0xff800000 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x370000 - config MRC_CACHE_SIZE hex depends on !CHROMEOS @@ -99,10 +54,6 @@ config DCACHE_RAM_SIZE hex default 0x20000 -endif - -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE - config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c" @@ -122,7 +73,7 @@ config HAVE_MRC config MRC_FILE string "Intel System Agent path and filename" depends on HAVE_MRC - default "systemagent-r6.bin" + default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" help The path and filename of the file to use as System Agent binary.

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Patch merged into coreboot/master: 4159a80 Correct spelling of shadow, setting and memory
by gerrit＠coreboot.org 16 Aug '13

16 Aug '13

the following patch was just integrated into master: commit 4159a8012eb7e0f492457b789999bbc56efc4713 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 00:24:31 2013 +0200 Correct spelling of shadow, setting and memory Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3768 for details. -gerrit

1 0

Patch set updated for coreboot: acf01fb Correct spelling of shadow, setting and memory
by Ronald G. Minnich 16 Aug '13

16 Aug '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3768 -gerrit commit acf01fb832c340889aaab8df59a86f7280c7ef53 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 00:24:31 2013 +0200 Correct spelling of shadow, setting and memory Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/dsdt.asl | 2 +- src/mainboard/amd/bimini_fam10/dsdt.asl | 2 +- src/mainboard/amd/dbm690t/dsdt.asl | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 2 +- src/mainboard/amd/pistachio/dsdt.asl | 2 +- src/mainboard/amd/tilapia_fam10/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/acpi/smbus.asl | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 2 +- src/mainboard/asus/m5a88-v/dsdt.asl | 2 +- src/mainboard/avalue/eax-785e/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 2 +- src/mainboard/gigabyte/ma78gm/dsdt.asl | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 2 +- src/mainboard/kontron/kt690/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/lippert/toucan-af/dsdt.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 2 +- src/mainboard/tyan/s8226/dsdt.asl | 2 +- src/northbridge/via/vx800/examples/romstage.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- util/cbfstool/cbfs_image.c | 2 +- 33 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 7f83bf1..94757b5 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 6642680..03a00e0 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index d5eddfc..32df673 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 8de013f..01cb8dd 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -1653,7 +1653,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 94e1635..f55480d 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 060b6e3..3e5ba54 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -1565,7 +1565,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index ed0c4c2..e6816b0 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -1716,7 +1716,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asrock/e350m1/acpi/smbus.asl b/src/mainboard/asrock/e350m1/acpi/smbus.asl index e4ccfe3..ebf7ddb 100644 --- a/src/mainboard/asrock/e350m1/acpi/smbus.asl +++ b/src/mainboard/asrock/e350m1/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index c0835c4..5449d01 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -1618,7 +1618,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 11684c4..6e1ccd1 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 672af6f..dd766f7 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 26c9024..923a828 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index edbd2e5..848d43e 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 89d8e29..c221e0a 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index b393a61..a02366e 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1685,7 +1685,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 7f6dec3..53e12af 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1684,7 +1684,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 9d64e89..7890df7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -1222,7 +1222,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8, /* SMBUS slave data */ SMK1, 8, diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index aa889a3..c854067 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1638,7 +1638,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 4aef6a2..5e18375 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -1649,7 +1649,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index 6184bde..13e5620 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -1751,7 +1751,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 598dca0..20fe2d7 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index d24c379..53be887 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index 1efb3b5..79bc096 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -1639,7 +1639,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 7c3fb7a..b629137 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -431,7 +431,7 @@ g) Rx73h = 32h if (boot_mode == 3) { /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ - /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ + /* setting mtrr before back memory save s3 resume time about 0.14 seconds */ /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 4ab7212..5352705 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -52,7 +52,7 @@ static void nic_init(struct device *dev) mmio = resource->base; /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Reseting PHY... "); + printk(BIOS_DEBUG, "Resetting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index 19ae92b..4055174 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index b627af6..4a0c36c 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -101,7 +101,7 @@ static void log_msg(const char *fmt, va_list args) static void fatal_error(void) { - printk(BIOS_ERR, "vboot encountered fatal error. Reseting.\n"); + printk(BIOS_ERR, "vboot encountered fatal error. Resetting.\n"); hard_reset(); } diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 44a9fe8..eb9d574 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -395,7 +395,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, cbfs_print_entry_info(image, entry, stderr); // setup new entry - DEBUG("Seting new empty entry.\n"); + DEBUG("Setting new empty entry.\n"); entry = cbfs_find_next_entry(image, entry); new_size = (cbfs_get_entry_addr(image, next) - cbfs_get_entry_addr(image, entry));

1 0

Patch set updated for coreboot: af49896 Correct spelling of shadow, setting and memory
by Ronald G. Minnich 16 Aug '13

16 Aug '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3768 -gerrit commit af498963f19b6ff8b6efe024785dbee4adb12d60 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Jul 14 00:24:31 2013 +0200 Correct spelling of shadow, setting and memory Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/advansus/a785e-i/dsdt.asl | 2 +- src/mainboard/amd/bimini_fam10/dsdt.asl | 2 +- src/mainboard/amd/dbm690t/dsdt.asl | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 2 +- src/mainboard/amd/pistachio/dsdt.asl | 2 +- src/mainboard/amd/tilapia_fam10/dsdt.asl | 2 +- src/mainboard/asrock/e350m1/acpi/smbus.asl | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 2 +- src/mainboard/asus/m5a88-v/dsdt.asl | 2 +- src/mainboard/avalue/eax-785e/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 2 +- src/mainboard/gigabyte/ma78gm/dsdt.asl | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 2 +- src/mainboard/kontron/kt690/dsdt.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 2 +- src/mainboard/lippert/toucan-af/dsdt.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm/dsdt.asl | 2 +- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 2 +- src/mainboard/tyan/s8226/dsdt.asl | 2 +- src/northbridge/via/vx800/examples/romstage.c | 2 +- src/southbridge/amd/amd8111/nic.c | 2 +- src/southbridge/amd/cimx/sb800/acpi/smbus.asl | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- util/cbfstool/cbfs_image.c | 2 +- 33 files changed, 33 insertions(+), 33 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 7f83bf1..94757b5 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 6642680..03a00e0 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index d5eddfc..32df673 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 8de013f..01cb8dd 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -1653,7 +1653,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 94e1635..f55480d 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 060b6e3..3e5ba54 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -1565,7 +1565,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index ed0c4c2..e6816b0 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -1716,7 +1716,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asrock/e350m1/acpi/smbus.asl b/src/mainboard/asrock/e350m1/acpi/smbus.asl index e4ccfe3..ebf7ddb 100644 --- a/src/mainboard/asrock/e350m1/acpi/smbus.asl +++ b/src/mainboard/asrock/e350m1/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index c6b04d2..a844640 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index c0835c4..5449d01 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -1618,7 +1618,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 11684c4..6e1ccd1 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 672af6f..dd766f7 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -1668,7 +1668,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 5b9359f..faf2171 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 26c9024..923a828 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -1713,7 +1713,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index edbd2e5..848d43e 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -1695,7 +1695,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 89d8e29..c221e0a 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index b393a61..a02366e 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1685,7 +1685,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 7f6dec3..53e12af 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1684,7 +1684,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 9d64e89..7890df7 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -1222,7 +1222,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8, /* SMBUS slave data */ SMK1, 8, diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index aa889a3..c854067 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1638,7 +1638,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 4aef6a2..5e18375 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -1649,7 +1649,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index 6184bde..13e5620 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -1751,7 +1751,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 598dca0..20fe2d7 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index d24c379..53be887 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -1637,7 +1637,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index 1efb3b5..79bc096 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -1639,7 +1639,7 @@ DefinitionBlock ( DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 7c3fb7a..b629137 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -431,7 +431,7 @@ g) Rx73h = 32h if (boot_mode == 3) { /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html I want move the 1M data, I have to set some MTRRs myself. */ - /* seting mtrr before back memoy save s3 resume time about 0.14 seconds */ + /* setting mtrr before back memory save s3 resume time about 0.14 seconds */ /*because CAR stack use cache, and here to use cache , must be careful, 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) 2 before stack switch, no use variable that have value set before this diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 4ab7212..5352705 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -52,7 +52,7 @@ static void nic_init(struct device *dev) mmio = resource->base; /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Reseting PHY... "); + printk(BIOS_DEBUG, "Resetting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index 19ae92b..4055174 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -30,7 +30,7 @@ OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) DAT1, 8, /* SMBUS data1 */ BLKD, 8, /* SMBUS block data */ SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ + SCMD, 8, /* SMBUS shadow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8 /* SMBUS slave data */ } diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 10fa52d..cb3b486 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -101,7 +101,7 @@ static void log_msg(const char *fmt, va_list args) static void fatal_error(void) { - printk(BIOS_ERR, "vboot encountered fatal error. Reseting.\n"); + printk(BIOS_ERR, "vboot encountered fatal error. Resetting.\n"); hard_reset(); } diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 44a9fe8..eb9d574 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -395,7 +395,7 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, cbfs_print_entry_info(image, entry, stderr); // setup new entry - DEBUG("Seting new empty entry.\n"); + DEBUG("Setting new empty entry.\n"); entry = cbfs_find_next_entry(image, entry); new_size = (cbfs_get_entry_addr(image, next) - cbfs_get_entry_addr(image, entry));

1 0

New patch to review for coreboot: 4ae6a7e usbdebug: Change reference to EHCI BAR
by Kyösti Mälkki 16 Aug '13

16 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3875 -gerrit commit 4ae6a7e8ef88048f283e579c65991a86c6bf099a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Aug 16 06:34:04 2013 +0300 usbdebug: Change reference to EHCI BAR Change the defines, as follow-up patch will replace use of constant CONFIG_EHCI_BAR. Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 9 +++++---- src/southbridge/amd/sb700/enable_usbdebug.c | 9 +++++---- src/southbridge/amd/sb800/enable_usbdebug.c | 9 +++++---- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index bd62842..6fa1781 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -30,19 +30,20 @@ #define HUDSON_DEVN_BASE 0 #endif -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) -#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +#define EHCI_EOR 0x20 +#define DEBUGPORT_MISC_CONTROL 0x80 void set_debug_port(unsigned int port) { + u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(DEBUGPORT_MISC_CONTROL, reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 6c46071..0712d2a 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,19 +27,20 @@ #include <device/pci_def.h> #include "sb700.h" -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) -#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +#define EHCI_EOR 0x20 +#define DEBUGPORT_MISC_CONTROL 0x80 void set_debug_port(unsigned int port) { + u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(DEBUGPORT_MISC_CONTROL, reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } /* diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index d17e955..6422fa2 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -30,19 +30,20 @@ #define SB800_DEVN_BASE 0 #endif -#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) -#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) +#define EHCI_EOR 0x20 +#define DEBUGPORT_MISC_CONTROL 0x80 void set_debug_port(unsigned int port) { + u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); reg32 &= ~(0xf << 28); reg32 |= (port << 28); reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(DEBUGPORT_MISC_CONTROL, reg32); + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); }

1 0

Patch set updated for coreboot: 35ad5c5 intel usbdebug: Add choice of EHCI controller
by Kyösti Mälkki 16 Aug '13

16 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3440 -gerrit commit 35ad5c51367d98ece69a9124210329b6924d6222 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 13 13:51:14 2013 +0300 intel usbdebug: Add choice of EHCI controller Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/bd82x6x/Kconfig | 2 +- src/southbridge/intel/common/usb_debug.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index bf020f8..c2720ef 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -30,7 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select IOAPIC select HAVE_HARD_RESET - select HAVE_USBDEBUG + select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 3fed2ab..9fe22cd 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -28,7 +28,32 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - return PCI_DEV(0, 0x1d, 7); + u32 class; + pci_devfn_t dev; + +#if CONFIG_HAVE_USBDEBUG_OPTIONS + if (hcd_idx==2) + dev = PCI_DEV(0, 0x1a, 0); + else + dev = PCI_DEV(0, 0x1d, 0); +#else + dev = PCI_DEV(0, 0x1d, 7); +#endif + + class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; +#if CONFIG_HAVE_USBDEBUG_OPTIONS + if (class != PCI_EHCI_CLASSCODE) { + /* If we enter here before RCBA programming, EHCI function may + * appear with the highest function number instead. + */ + dev |= PCI_DEV(0, 0, 7); + class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; + } +#endif + if (class != PCI_EHCI_CLASSCODE) + return 0; + + return dev; } /* Required for successful build, but currently empty. */ @@ -41,6 +66,10 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { u32 dbgctl; + /* Bail out. No console to complain in. */ + if (!dev) + return; + /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, base);

1 0

Patch set updated for coreboot: e35a510 usbdebug: Fixes for LynxPoint LP
by Kyösti Mälkki 16 Aug '13

16 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3477 -gerrit commit e35a5103f5d5c7bebd789e371dbab404c3402cf1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 13 09:10:31 2013 +0300 usbdebug: Fixes for LynxPoint LP Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 4 ++-- src/southbridge/intel/lynxpoint/early_usb.c | 10 ++++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 79aba6c..3cf9ffe 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select IOAPIC select HAVE_HARD_RESET - select HAVE_USBDEBUG + select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK @@ -42,7 +42,7 @@ config INTEL_LYNXPOINT_LP config EHCI_BAR hex - default 0xfef00000 + default 0xe8000000 config EHCI_DEBUG_OFFSET hex diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index d71467e..d65ca4a 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -24,8 +24,14 @@ #include <device/pci_def.h> #include "pch.h" -#define PCH_EHCI1_TEMP_BAR0 0xe8000000 -#define PCH_EHCI2_TEMP_BAR0 0xe8000400 + +#if CONFIG_USBDEBUG_HCD_INDEX != 2 +#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR +#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400) +#else +#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR +#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400) +#endif /* * Setup USB controller MMIO BAR to prevent the

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Patch set updated for coreboot: 30e930a usbdebug: Support choice of EHCI controller
by Kyösti Mälkki 16 Aug '13

16 Aug '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3438 -gerrit commit 30e930afe8d58315b80521b181c9b8a712facbdb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Aug 15 16:27:06 2013 +0300 usbdebug: Support choice of EHCI controller Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 19 +++++++++++++ src/include/usbdebug.h | 10 +++++-- src/lib/usbdebug.c | 32 ++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 18 ++++++------ src/southbridge/amd/sb600/enable_usbdebug.c | 13 +++++---- src/southbridge/amd/sb700/enable_usbdebug.c | 26 ++++++++++-------- src/southbridge/amd/sb800/enable_usbdebug.c | 18 ++++++------ src/southbridge/intel/common/usb_debug.c | 16 +++++++---- src/southbridge/nvidia/ck804/enable_usbdebug.c | 14 ++++++---- src/southbridge/nvidia/mcp55/enable_usbdebug.c | 14 ++++++---- src/southbridge/sis/sis966/enable_usbdebug.c | 14 ++++++---- 11 files changed, 132 insertions(+), 62 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 71e5725..a57ca58 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -131,6 +131,13 @@ config SPKMODEM # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG + bool + default y if HAVE_USBDEBUG_OPTIONS + default n + +# Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple +# EHCI controllers or multiple ports with Debug Port capability +config HAVE_USBDEBUG_OPTIONS def_bool n config USBDEBUG @@ -154,6 +161,18 @@ config USBDEBUG If unsure, say N. +config USBDEBUG_HCD_INDEX + int "Index for EHCI controller to use with usbdebug" + default 0 + depends on USBDEBUG + help + Some boards have multiple EHCI controllers with possibly only + one having the Debug Port capability on an external USB port. + + Mapping of this index to PCI device functions is southbridge + specific and mainboard level Kconfig should already provide + a working default value here. + config USBDEBUG_DEFAULT_PORT int "Default USB port to use as Debug Port" default 0 diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 2728be0..926d658 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -22,6 +22,13 @@ #define USBDEBUG_H #define EHCI_BAR_INDEX 0x10 +#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ + +typedef u32 pci_devfn_t; +pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx); +unsigned long pci_ehci_base_regs(pci_devfn_t dev); +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base); #ifndef __PRE_RAM__ #if !CONFIG_USBDEBUG @@ -42,9 +49,6 @@ void pci_ehci_read_resources(struct device *dev); struct dbgp_pipe; -void enable_usbdebug(unsigned int port); -void set_debug_port(unsigned port); - int usbdebug_init(void); struct dbgp_pipe *dbgp_console_output(void); diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index cde19a1..ba5d442 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <arch/io.h> #include <device/pci.h> +#include <device/pci_def.h> #include <arch/byteorder.h> #include <cpu/x86/car.h> #include <string.h> @@ -397,6 +398,20 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) return -1; //-ENOTCONN; } +#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE +static void enable_usbdebug(void) +{ + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); +} +#endif + +static void set_debug_port(unsigned int port) +{ + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_ehci_dbg_set_port(dbg_dev, port); +} + static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) { struct ehci_caps *ehci_caps; @@ -683,7 +698,9 @@ static void pci_ehci_set_resources(struct device *dev) void pci_ehci_read_resources(struct device *dev) { - if (!ehci_drv_ops) { + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + + if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); ehci_drv_ops = dev->ops; ehci_dbg_ops.set_resources = pci_ehci_set_resources; @@ -697,6 +714,17 @@ void pci_ehci_read_resources(struct device *dev) } #endif +unsigned long pci_ehci_base_regs(pci_devfn_t sdev) +{ +#ifdef __SIMPLE_DEVICE__ + unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; +#else + device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev)); + unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f; +#endif + return base + HC_LENGTH(read32(base)); +} + int dbgp_ep_is_active(struct dbgp_pipe *pipe) { return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); @@ -717,7 +745,7 @@ int usbdebug_init(void) struct ehci_debug_info *dbg_info = dbgp_ehci_info(); #if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE - enable_usbdebug(0); + enable_usbdebug(); #endif return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 6fa1781..459df6f 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -30,12 +30,16 @@ #define HUDSON_DEVN_BASE 0 #endif -#define EHCI_EOR 0x20 #define DEBUGPORT_MISC_CONTROL 0x80 -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; + return PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + u32 base_regs = pci_ehci_base_regs(dev); u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ @@ -47,14 +51,12 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, base); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 40c53ae..09fce2f 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -26,18 +26,21 @@ #include <device/pci_def.h> #include "sb600.h" +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ +} + /* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* TODO: Allow changing the physical USB port used as Debug Port. */ } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 0712d2a..3d44a1a 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -27,12 +27,21 @@ #include <device/pci_def.h> #include "sb700.h" -#define EHCI_EOR 0x20 #define DEBUGPORT_MISC_CONTROL 0x80 -void set_debug_port(unsigned int port) +/* + * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. + * This code currently only supports the first one, i.e., USB Debug devices + * attached to physical USB ports belonging to the first EHCI device. + */ +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { - u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; + u32 base_regs = pci_ehci_base_regs(dev); u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ @@ -43,17 +52,10 @@ void set_debug_port(unsigned int port) write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } -/* - * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. - * This code currently only supports the first one, i.e., USB Debug devices - * attached to physical USB ports belonging to the first EHCI device. - */ -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 6422fa2..9277869 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -30,12 +30,16 @@ #define SB800_DEVN_BASE 0 #endif -#define EHCI_EOR 0x20 #define DEBUGPORT_MISC_CONTROL 0x80 -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR; + return PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + u32 base_regs = pci_ehci_base_regs(dev); u32 reg32; /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ @@ -47,14 +51,12 @@ void set_debug_port(unsigned int port) } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), - PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config32(dev, EHCI_BAR_INDEX, base); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 6b934f4..3fed2ab 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -26,25 +26,29 @@ #include <usbdebug.h> #include <device/pci_def.h> +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, 0x1d, 7); +} + /* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { u32 dbgctl; - pci_devfn_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); + write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); } diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index d65fea2..d98bc98 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -36,10 +36,14 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -48,12 +52,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index f629c50..b0afec2 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -30,10 +30,14 @@ #include <device/pci_def.h> #include "mcp55.h" -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -42,12 +46,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index 04384ba..0d7503d 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -32,10 +32,14 @@ #include <device/pci_def.h> #include "sis966.h" -void set_debug_port(unsigned int port) +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + return PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ /* Write the port number to 0x74[15:12]. */ dword = pci_read_config32(dev, 0x74); @@ -44,12 +48,10 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -void enable_usbdebug(unsigned int port) +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, base); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

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Patch merged into coreboot/master: 95b573a AMD Southbridge CS5536: make use of #include <device/smbus_def.h>
by gerrit＠coreboot.org 16 Aug '13

16 Aug '13

the following patch was just integrated into master: commit 95b573a2db59c21cc60cd6802194beb999919e7f Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Wed Jun 5 16:40:34 2013 +0200 AMD Southbridge CS5536: make use of #include <device/smbus_def.h> Change-Id: Ia2dff49d3e2b086546785d992f2d92bcf4d1ef1c Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> Reviewed-on: http://review.coreboot.org/3376 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3376 for details. -gerrit

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coreboot-gerrit August 2013