coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: af9c07c pit: update I2C4 speed constant
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3705 -gerrit commit af9c07c97d629990e5da88cc81688b3028f74500 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 22 19:42:15 2013 -0700 pit: update I2C4 speed constant Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)… [View More]

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Patch set updated for coreboot: a707156 arm/exynos: Correct SPI session commands.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3706 -gerrit commit a70715639e20098911d0d8226b6e62c837696fad Author: Hung-Te Lin <hungte(a)chromium.org> Date: Sun Jun 23 08:14:30 2013 +0800 arm/exynos: Correct SPI session commands. Some initialization / shutdown commands should be paired correctly in a SPI I/O session. For example, setting CS should be enabled and disabled in each read; … [View More] and the bus width (byte or word) should be configured only when opening / closing the SPI device. Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/spi.c | 13 +++++++------ src/cpu/samsung/exynos5420/spi.c | 13 +++++++------ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c index 503cee9..642ae23 100644 --- a/src/cpu/samsung/exynos5250/spi.c +++ b/src/cpu/samsung/exynos5250/spi.c @@ -102,7 +102,6 @@ int exynos_spi_open(struct exynos_spi *regs) /* now set rx and tx channel ON */ setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ return 0; } @@ -110,6 +109,8 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + /* Send read instruction (0x3h) followed by a 24 bit addr */ writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data); @@ -123,6 +124,11 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + return len; +} + +int exynos_spi_close(struct exynos_spi *regs) +{ /* * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet @@ -131,11 +137,6 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); writel(0, &regs->swap_cfg); - return len; -} - -int exynos_spi_close(struct exynos_spi *regs) -{ /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 503cee9..642ae23 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -102,7 +102,6 @@ int exynos_spi_open(struct exynos_spi *regs) /* now set rx and tx channel ON */ setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ return 0; } @@ -110,6 +109,8 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; + clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + /* Send read instruction (0x3h) followed by a 24 bit addr */ writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data); @@ -123,6 +124,11 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + return len; +} + +int exynos_spi_close(struct exynos_spi *regs) +{ /* * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet @@ -131,11 +137,6 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); writel(0, &regs->swap_cfg); - return len; -} - -int exynos_spi_close(struct exynos_spi *regs) -{ /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel [View Less]

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Patch set updated for coreboot: 77a8bcd armv7/pit: Setup EC on SPI2.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3707 -gerrit commit 77a8bcd0d18255b7fc00b86e92c3cc32c0f8466a Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Jun 24 20:02:01 2013 +0800 armv7/pit: Setup EC on SPI2. The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: … [View More]

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Patch set updated for coreboot: 3af4032 pit: Enable the ps8625 driver.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3722 -gerrit commit 3af403223fa20a06e18523da7cac938a7b72b524 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 30 06:09:12 2013 -0700 pit: Enable the ps8625 driver. Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/Kconfig | 1 + 1 file … [View More]

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Patch set updated for coreboot: 254a3eb pit: Redo the display port bridge initialization code.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3723 -gerrit commit 254a3eb5b5b4b9aa3fd5813bb10d90bb66699d8b Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 30 05:19:53 2013 -0700 pit: Redo the display port bridge initialization code. The display port bridge on pit is different from the one on snow and needs to be initialized differently. Instead of waiting for the chip to come … [View More]up on its own and assert the hotplug detect, we need to access it over i2c and get it up and running ourselves. Change-Id: I4bc911cb8e4463edff7beabd2f356cb70ae9f507 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/mainboard.c | 71 +++++++++--------------------------- 1 file changed, 17 insertions(+), 54 deletions(-) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 67d3b5d..54ea042 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -34,7 +34,9 @@ #include <cpu/samsung/exynos5420/power.h> #include <cpu/samsung/exynos5420/i2c.h> #include <cpu/samsung/exynos5420/dp-core.h> +#include <drivers/parade/ps8625/ps8625.h> #include <ec/google/chromeec/ec.h> +#include <stdlib.h> #include "exynos5420.h" @@ -56,7 +58,7 @@ static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ -static void exynos_dp_bridge_setup(void) +static void parade_dp_bridge_setup(void) { gpio_set_value(dp_pd_l, 1); gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); @@ -69,37 +71,19 @@ static void exynos_dp_bridge_setup(void) gpio_set_value(dp_rst_l, 1); gpio_cfg_pin(dp_hpd, GPIO_INPUT); -} -static void exynos_dp_bridge_init(void) -{ - /* De-assert PD (and possibly RST) to power up the bridge */ + /* De-assert PD (and possibly RST) to power up the bridge. */ gpio_set_value(dp_pd_l, 1); gpio_set_value(dp_rst_l, 1); - /* - * We need to wait for 90ms after bringing up the bridge since - * there is a phantom "high" on the HPD chip during its - * bootup. The phantom high comes within 7ms of de-asserting - * PD and persists for at least 15ms. The real high comes - * roughly 50ms after PD is de-asserted. The phantom high - * makes it hard for us to know when the NXP chip is up. - */ - udelay(90000); -} + /* Hang around for the bridge to come up. */ + mdelay(40); -static int exynos_dp_hotplug(void) -{ - /* Check HPD. If it's high, we're all good. */ - return gpio_get_value(dp_hpd) ? 0 : 1; -} + /* Configure the bridge chip. */ + exynos_pinmux_i2c7(); + i2c_init(7, 100000, 0x00); -static void exynos_dp_reset(void) -{ - gpio_set_value(dp_pd_l, 0); - gpio_set_value(dp_rst_l, 0); - /* paranoid delay period (300ms) */ - udelay(300 * 1000); + parade_ps8625_bridge_setup(7, 0x48); } /* @@ -203,7 +187,6 @@ static void backlight_vdd(void) /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { - int dp_tries; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE, .video_info = &dp_video_info, @@ -225,34 +208,14 @@ static void mainboard_init(device_t dev) lcd_vdd(); - // FIXME: should timeout - do { - udelay(50); - } while (!exynos_dp_hotplug()); - - exynos_dp_bridge_setup(); - for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { - exynos_dp_bridge_init(); - if (exynos_dp_hotplug()) { - printk(BIOS_ERR, "Hotplug detect failed.\n"); - exynos_dp_reset(); - continue; - } - - if (dp_controller_init(&dp_device)) - continue; - - udelay(LCD_T3_DELAY_MS * 1000); - - backlight_vdd(); - backlight_pwm(); - backlight_en(); - /* if we're here, we're successful */ - break; - } + parade_dp_bridge_setup(); + dp_controller_init(&dp_device); + + udelay(LCD_T3_DELAY_MS * 1000); - if (dp_tries > MAX_DP_TRIES) - printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); + backlight_vdd(); + backlight_pwm(); + backlight_en(); // Uncomment to get excessive GPIO output: // gpio_info(); [View Less]

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Patch set updated for coreboot: 5bb261b pit: Stop setting up the hardware dp hotplug detect in ROM stage too.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3720 -gerrit commit 5bb261b103682571febc67f639a3eb6f18386419 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 30 03:37:24 2013 -0700 pit: Stop setting up the hardware dp hotplug detect in ROM stage too. This was removed from ramstage a little while ago and should have been removed from here as well. Change-Id: … [View More]

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Patch set updated for coreboot: 41a2d11 i2c: Change the type of the data parameter to uint8_t.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3721 -gerrit commit 41a2d111d45d9e74769c1e572ceb436f25e49a0e Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 30 03:47:33 2013 -0700 i2c: Change the type of the data parameter to uint8_t. Data is intended to be a byte array, so it should be described by a type which has a fixed size equal to an 8 bit byte. Also, the data passed to … [View More]write shouldn't be modified and can be const. Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/i2c.c | 6 +++--- src/cpu/samsung/exynos5420/i2c.c | 13 +++++++------ src/include/device/i2c.h | 6 ++++-- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/cpu/samsung/exynos5250/i2c.c b/src/cpu/samsung/exynos5250/i2c.c index 723cee6..e83ab57 100644 --- a/src/cpu/samsung/exynos5250/i2c.c +++ b/src/cpu/samsung/exynos5250/i2c.c @@ -347,7 +347,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, } int i2c_read(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -376,7 +376,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, } int i2c_write(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, const uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -397,7 +397,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, i2c = &i2c_buses[bus]; ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], - alen, buf, len); + alen, (void *)buf, len); return ret != 0; } diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index acb5bcf..2268628 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -408,7 +408,8 @@ static int hsi2c_wait_for_transfer(struct exynos5_hsi2c *i2c) return 0; } -static int hsi2c_senddata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) +static int hsi2c_senddata(struct exynos5_hsi2c *i2c, const uint8_t *data, + int len) { while (!hsi2c_check_transfer(i2c) && len) { if (!(read32(&i2c->usi_fifo_stat) & HSI2C_TX_FIFO_FULL)) { @@ -434,7 +435,7 @@ static int hsi2c_write(struct exynos5_hsi2c *i2c, unsigned char chip, unsigned char addr[], unsigned char alen, - unsigned char data[], + const uint8_t data[], unsigned short len) { uint32_t i2c_auto_conf; @@ -470,7 +471,7 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, unsigned char chip, unsigned char addr[], unsigned char alen, - unsigned char data[], + uint8_t data[], unsigned short len, int check) { @@ -632,7 +633,7 @@ bailout: } int i2c_read(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -667,7 +668,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, } int i2c_write(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len) + unsigned alen, const uint8_t *buf, unsigned len) { struct s3c24x0_i2c_bus *i2c; unsigned char xaddr[4]; @@ -692,7 +693,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, alen, buf, len); else ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, - &xaddr[4 - alen], alen, buf, len); + &xaddr[4 - alen], alen, (void *)buf, len); if (ret != 0) { diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index d880a7b..997d201 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -20,10 +20,12 @@ #ifndef _DEVICE_I2C_H_ #define _DEVICE_I2C_H_ +#include <stdint.h> + /* note: chip is the 7-bit I2C address */ int i2c_read(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len); + unsigned alen, uint8_t *buf, unsigned len); int i2c_write(unsigned bus, unsigned chip, unsigned addr, - unsigned alen, unsigned char *buf, unsigned len); + unsigned alen, const uint8_t *buf, unsigned len); #endif /* _DEVICE_I2C_H_ */ [View Less]

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Patch set updated for coreboot: fa2e01f armv7/exynos5420: Apply new implementation for SPI transmission.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3714 -gerrit commit fa2e01facac0675dce893e9cb613e74927e21803 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:31:22 2013 +0800 armv7/exynos5420: Apply new implementation for SPI transmission. Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 … [View More]Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 115 +++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 59 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index dddbec5..906f6a7 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -153,10 +153,8 @@ static void exynos_spi_request_bytes(struct exynos_spi *regs, int count, } } -int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, - const uint8_t *txp, int tx_bytes); -int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, - const uint8_t *txp, int tx_bytes) +static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, + const uint8_t *txp, int tx_bytes) { struct exynos_spi_slave *espi = to_exynos_spi(slave); struct exynos_spi *regs = espi->regs; @@ -237,46 +235,6 @@ int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, return 0; } -static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, - void *dinp, void const *doutp, int i) -{ - int rx_lvl, tx_lvl; - unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); - unsigned int out_bytes, in_bytes; - - // TODO In currrent implementation, every read/write must be aligned to - // 4 bytes, otherwise you may get timeout or other unexpected results. - ASSERT(todo % 4 == 0); - - out_bytes = in_bytes = todo; - exynos_spi_soft_reset(regs); - writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); - - while (in_bytes) { - uint32_t spi_sts; - int temp; - - spi_sts = readl(&regs->spi_sts); - rx_lvl = ((spi_sts >> 15) & 0x7f); - tx_lvl = ((spi_sts >> 6) & 0x7f); - while (tx_lvl < 32 && out_bytes) { - // TODO The "writing" (tx) is not supported now; that's - // why we write garbage to keep driving FIFO clock. - temp = 0xffffffff; - writel(temp, &regs->tx_data); - out_bytes -= 4; - tx_lvl += 4; - } - while (rx_lvl >= 4 && in_bytes) { - temp = readl(&regs->rx_data); - if (rxp) - *rxp++ = temp; - in_bytes -= 4; - rx_lvl -= 4; - } - } -} - int spi_claim_bus(struct spi_slave *slave) { struct exynos_spi_slave *espi = to_exynos_spi(slave); @@ -304,32 +262,70 @@ int spi_claim_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { - // TODO(hungte) Invoke exynos_spi_rx_tx to transfer data. - return -1; + unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; + uint8_t *out_ptr = (uint8_t *)dout, *in_ptr = (uint8_t *)din; + int offset, todo, len; + int ret = 0; + + ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); + len = MAX(out_bytes, in_bytes); + + /* + * Exynos SPI limits each transfer to (2^16-1=65535) bytes. To keep + * things simple (especially for word-width transfer mode), allow a + * maximum of (2^16-4=65532) bytes. We could allow more in word mode, + * but the performance difference is small. + */ + spi_cs_activate(slave); + for (offset = 0; !ret && (offset < len); offset += todo) { + todo = min(len - offset, (1 << 16) - 4); + ret = spi_rx_tx(slave, in_ptr, MIN(in_bytes, todo), out_ptr, + MIN(out_bytes, todo)); + // Adjust remaining bytes and pointers. + if (in_bytes >= todo) { + in_bytes -= todo; + in_ptr += todo; + } else { + in_bytes = 0; + in_ptr = NULL; + } + if (out_bytes >= todo) { + out_bytes -= todo; + out_ptr += todo; + } else { + out_bytes = 0; + out_ptr = NULL; + } + } + spi_cs_deactivate(slave); + + return ret; } static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, uint32_t off) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - int upto, todo; - int i; - clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + int rv; - /* Send read instruction (0x3h) followed by a 24 bit addr */ - writel((SF_READ_DATA_CMD << 24) | off, &regs->tx_data); + // TODO(hungte) Merge the "read address" command into spi_xfer calls + // (full-duplex mode). - /* waiting for TX done */ - while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)); + spi_cs_activate(slave); - for (upto = 0, i = 0; upto < len; upto += todo, i++) { - todo = MIN(len - upto, (1 << 15)); - exynos_spi_rx_tx(regs, todo, dest, (void *)(off), i); + // Specify read address (in word-width mode). + ASSERT(off < (1 << 24)); + exynos_spi_request_bytes(regs, sizeof(off), sizeof(off)); + writel(htonl((SF_READ_DATA_CMD << 24) | off), &regs->tx_data); + while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) { + /* Wait for TX done */ } - setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + // Now, safe to transfer. + rv = spi_xfer(slave, NULL, 0, dest, len * 8); + spi_cs_deactivate(slave); - return len; + return (rv == 0) ? len : -1; } void spi_release_bus(struct spi_slave *slave) @@ -378,7 +374,8 @@ static void *exynos_spi_cbfs_map(struct cbfs_media *media, size_t offset, size_t count) { struct exynos_spi_media *spi = (struct exynos_spi_media*)media->context; DEBUG_SPI("exynos_spi_cbfs_map\n"); - // See exynos_spi_rx_tx for I/O alignment limitation. + // exynos: spi_rx_tx may work in 4 byte-width-transmission mode and + // requires buffer memory address to be aligned. if (count % 4) count += 4 - (count % 4); return cbfs_simple_buffer_map(&spi->buffer, media, offset, count); [View Less]

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Patch set updated for coreboot: 16f3931 armv7/exynos5420: Remove the extra reopen when reading SPI.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3715 -gerrit commit 16f393162b67f8b44fc64ff475861b5d9ff12b48 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 21:22:55 2013 +0800 armv7/exynos5420: Remove the extra reopen when reading SPI. The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be … [View More]

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Patch set updated for coreboot: 0e0c01b armv7/exynos5420: Revise SPI open/close/reset procedure.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3712 -gerrit commit 0e0c01b37be60cb4b4a760cf8861a487f994b3f3 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 26 20:22:50 2013 +0800 armv7/exynos5420: Revise SPI open/close/reset procedure. The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it … [View More]tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/spi.c | 76 +++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 82c3765..6637aad 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -102,6 +102,26 @@ void spi_cs_deactivate(struct spi_slave *slave) setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); } +static inline void exynos_spi_soft_reset(struct exynos_spi *regs) +{ + /* The soft reset clears only FIFO and status register. + * All special function registers are not changed. */ + setbits_le32(&regs->ch_cfg, SPI_CH_RST); + clrbits_le32(&regs->ch_cfg, SPI_CH_RST); +} + +static inline void exynos_spi_flush_fifo(struct exynos_spi *regs) +{ + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits_le32(&regs->ch_cfg, SPI_CH_HS_EN); + exynos_spi_soft_reset(regs); + setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); +} + static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, void *dinp, void const *doutp, int i) { @@ -114,8 +134,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, ASSERT(todo % 4 == 0); out_bytes = in_bytes = todo; - setbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + exynos_spi_soft_reset(regs); writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt); while (in_bytes) { @@ -143,35 +162,27 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, } } -/* set up SPI channel */ int spi_claim_bus(struct spi_slave *slave) { struct exynos_spi_slave *espi = to_exynos_spi(slave); struct exynos_spi *regs = espi->regs; - /* set the spi1 GPIO */ + exynos_spi_flush_fifo(regs); - /* set pktcnt and enable it */ - writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt); - /* set FB_CLK_SEL */ - writel(SPI_FB_DELAY_180, &regs->fb_clk); - /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(&regs->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + // Select Active High Clock, Format A (SCP 30.2.1.8). + clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L | SPI_CH_CPHA_B); - /* clear rx and tx channel if set priveously */ - clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - - setbits_le32(&regs->swap_cfg, - SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); - - /* do a soft reset */ - setbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); + // Set FeedBack Clock Selection. + writel(SPI_FB_DELAY_180, &regs->fb_clk); - /* now set rx and tx channel ON */ - setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + // HIGH speed is required for Tx/Rx to work in 50MHz (SCP 30.2.1.6). + if (espi->half_duplex) { + clrbits_le32(&regs->ch_cfg, SPI_CH_HS_EN); + printk(BIOS_DEBUG, "%s: LOW speed.\n", __func__); + } else { + setbits_le32(&regs->ch_cfg, SPI_CH_HS_EN); + printk(BIOS_DEBUG, "%s: HIGH speed.\n", __func__); + } return 0; } @@ -209,21 +220,12 @@ static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, void spi_release_bus(struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - /* - * Let put controller mode to BYTE as - * SPI driver does not support WORD mode yet - */ - clrbits_le32(&regs->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + /* Reset swap mode to make sure no one relying on default values (Ex, + * payload or kernel) will go wrong. */ + clrbits_le32(&regs->mode_cfg, (SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD)); writel(0, &regs->swap_cfg); - - /* - * Flush spi tx, rx fifos and reset the SPI controller - * and clear rx/tx channel - */ - clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_CH_RST); - clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); + exynos_spi_flush_fifo(regs); } // SPI as CBFS media. [View Less]

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coreboot-gerrit July 2013