coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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1030 discussions

Patch set updated for coreboot: 21af019 ARMv7: Drop duplicate call to bootblock_cpu_init()
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3692 -gerrit commit 21af01998ca2622695d358812b0c964e7269fec9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 12 17:07:05 2013 -0700 ARMv7: Drop duplicate call to bootblock_cpu_init() This is already called in ARMv7 bootblock_simple.c so we don't want to do it twice Change-Id: I80cb41035b8a77787e04f2ea58a1cd372cea97d8 … [View More]

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Patch set updated for coreboot: 3327230 Exynos: Only compile UART in if serial console is selected
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3695 -gerrit commit 3327230889a036117ad2a1ba5f024824fa8e2e20 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:51:04 2013 -0700 Exynos: Only compile UART in if serial console is selected Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: … [View More]Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 4 ++++ src/cpu/samsung/exynos5420/Makefile.inc | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 663f532..e4e373c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,9 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +endif bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c @@ -24,7 +26,9 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +endif romstage-y += wakeup.c romstage-y += pwm.c # needed by timer.c romstage-y += gpio.c diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 1dddd21..6f9b91b 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,9 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +endif bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c @@ -24,7 +26,9 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +endif romstage-y += wakeup.c romstage-y += pwm.c # needed by timer.c romstage-y += gpio.c [View Less]

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Patch set updated for coreboot: be7a446 Don't try to use CBMEM console in bootblock
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3694 -gerrit commit be7a446507e3fe0bfb3a261351019e1cfebf806d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:44:36 2013 -0700 Don't try to use CBMEM console in bootblock Otherwise we have to worry about hand off between bootblock and romstage. Too much complexity Change-Id: … [View More]

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Patch set updated for coreboot: 9ec5044 pit: Replace the snow GPIO indexes with ones for pit.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3689 -gerrit commit 9ec50449e83149eaadf297157fb4a3190dec84bf Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 03:29:45 2013 -0700 pit: Replace the snow GPIO indexes with ones for pit. The GPIOs used by vboot and setting up the display and backlight were still the ones for snow. This change updates them so they're correct for pit. … [View More] Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/chromeos.c | 10 +++++----- src/mainboard/google/pit/mainboard.c | 12 +++++++----- src/mainboard/google/pit/romstage.c | 16 ++++++++-------- 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c index 349ba1d..ae219bb 100644 --- a/src/mainboard/google/pit/chromeos.c +++ b/src/mainboard/google/pit/chromeos.c @@ -36,9 +36,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int count = 0; /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; + gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO + gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -54,7 +54,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO + gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; @@ -62,7 +62,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[count].port = EXYNOS5_GPX1; gpios->gpios[count].polarity = ACTIVE_LOW; gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO + gpio_get_value(GPIO_X12); // POWER_GPIO strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -91,7 +91,7 @@ int get_recovery_mode_switch(void) uint32_t ec_events; /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO + if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO return 1; ec_events = google_chromeec_get_events_b(); diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index f0df039..1608788 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -49,9 +49,11 @@ static struct edid edid = { }; /* TODO: transplanted DP stuff, clean up once we have something that works */ -static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ -static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ -static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ +static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ +static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ static void exynos_dp_bridge_setup(void) { @@ -115,14 +117,14 @@ static void exynos_dp_reset(void) static void backlight_pwm(void) { /*Configure backlight PWM as a simple output high (100% brightness) */ - gpio_direction_output(GPIO_B20, 1); + gpio_direction_output(bl_pwm, 1); udelay(LCD_T6_DELAY_MS * 1000); } static void backlight_en(void) { /* Configure GPIO for LCD_BL_EN */ - gpio_direction_output(GPIO_X30, 1); + gpio_direction_output(bl_en, 1); } //static struct video_info smdk5420_dp_config = { diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 001d8cf..41b64b2 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -129,17 +129,17 @@ static void setup_graphics(void) static void setup_gpio(void) { - gpio_direction_input(GPIO_D16); // WP_GPIO - gpio_set_pull(GPIO_D16, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X30); // WP_GPIO + gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); - gpio_direction_input(GPIO_Y10); // RECMODE_GPIO - gpio_set_pull(GPIO_Y10, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X07); // RECMODE_GPIO + gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); - gpio_direction_input(GPIO_X35); // LID_GPIO - gpio_set_pull(GPIO_X35, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X34); // LID_GPIO + gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); - gpio_direction_input(GPIO_X13); // POWER_GPIO - gpio_set_pull(GPIO_X13, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X12); // POWER_GPIO + gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); } static void setup_memory(struct mem_timings *mem, int is_resume) [View Less]

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Patch set updated for coreboot: f67f3db pit: Remove the MAX_CPUS option.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3688 -gerrit commit f67f3dbf10f5127d58c6d11a590f159512964e7f Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 02:37:51 2013 -0700 pit: Remove the MAX_CPUS option. The MAX_CPUS option is only used on x86 currently, so there's no reason to have it in the pit config. Change-Id: I270bbfd3aff781d88304791b1d9735777643caab … [View More]

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Patch set updated for coreboot: 73c1b26 Simplify early / bootblock console code
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3691 -gerrit commit 73c1b263639305e59881f837c787ea09feead52a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 13:42:00 2013 -0700 Simplify early / bootblock console code Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <… [View More]gabeblack(a)chromium.org> --- src/console/Kconfig | 13 +++---------- src/cpu/Kconfig | 2 +- src/cpu/samsung/exynos5250/Kconfig | 3 +-- src/cpu/samsung/exynos5420/Kconfig | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - 5 files changed, 6 insertions(+), 15 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index f62cfdd..013b72f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,22 +1,15 @@ menu "Console" -config DEFAULT_BOOTBLOCK_CONSOLE - bool - default n - config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - default DEFAULT_BOOTBLOCK_CONSOLE + depends on ARCH_ARMV7 + default n help Use console during the bootblock if supported -config DEFAULT_EARLY_CONSOLE - bool - default n - config EARLY_CONSOLE bool "Enable early (pre-RAM) console output." - default DEFAULT_EARLY_CONSOLE + default n help Use console during early (pre-RAM) boot stages diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 788e219..9d268e4 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -20,7 +20,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select DEFAULT_EARLY_CONSOLE + select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index d6c3f1e..63b46d6 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -2,8 +2,7 @@ config CPU_SAMSUNG_EXYNOS5250 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DEFAULT_BOOTBLOCK_CONSOLE - select DEFAULT_EARLY_CONSOLE + select EARLY_CONSOLE bool default n diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index efa0b21..63ff08c 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -2,7 +2,7 @@ config CPU_SAMSUNG_EXYNOS5420 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DEFAULT_EARLY_CONSOLE + select EARLY_CONSOLE bool default n diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 944e711..9bee946 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 select HAVE_UART_MEMORY_MAPPED - select DEFAULT_EARLY_CONSOLE select HAVE_UART_SPECIAL select BOARD_ROMSIZE_KB_4096 [View Less]

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Patch set updated for coreboot: 004ae7d ARM: Don't leave alignment checking on after the exception test.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3690 -gerrit commit 004ae7da3d4b787924eeb71d528987abf99afb85 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 20:15:57 2013 -0700 ARM: Don't leave alignment checking on after the exception test. Currently, the exception handling code on ARM turns on alignment checks as an easy way to generate an exception for testing purposes. It … [View More]

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Patch set updated for coreboot: 642d450 exynos5420: Change some clock settings.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3700 -gerrit commit 642d450f93a645ff1dc36c54bdc21ef1898e13eb Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jun 22 20:05:37 2013 -0700 exynos5420: Change some clock settings. This change adjusts some clock settings so that they match U-Boot. There are three different changes. 1. Change the source for psgen from the oscillator … [View More]

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Patch set updated for coreboot: c17d2a3 exynos5420: use speed parameter in i2c_init() for HSI2C
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3701 -gerrit commit c17d2a3692b42f8a065326519d65152b79881c49 Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 22 19:40:43 2013 -0700 exynos5420: use speed parameter in i2c_init() for HSI2C This allows us to set different speeds for each HSI2C bus. Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02 Signed-off-by: … [View More]David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/i2c.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index cbe7a79..b16d068 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -93,11 +93,6 @@ #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) -/* Controller operating frequency, timing values for operation - * are calculated against this frequency - */ -#define HSI2C_FS_TX_CLOCK 1000000 - /* S3C I2C Controller bits */ #define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ @@ -244,11 +239,11 @@ static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) write32(I2C_MODE_MT | I2C_TXRX_ENA, &bus->regs->iicstat); } -static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) +static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus, + unsigned int bus_freq_hz) { struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; unsigned long clkin = clock_get_periph_rate(i2c_bus->periph_id); - unsigned int op_clk = HSI2C_FS_TX_CLOCK; unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; @@ -259,7 +254,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) * uTemp2 = TSCLK_L + TSCLK_H */ t_ftl_cycle = (read32(&hsregs->usi_conf) >> 16) & 0x7; - utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + utemp0 = (clkin / bus_freq_hz) - 8 - 2 * t_ftl_cycle; /* CLK_DIV max is 256 */ for (i = 0; i < 256; i++) { @@ -274,7 +269,8 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) return -1; } -static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) +static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus, + unsigned int bus_freq_hz) { struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; unsigned int t_sr_release; @@ -288,7 +284,7 @@ static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) u32 i2c_timing_s3; u32 i2c_timing_sla; - hsi2c_get_clk_details(i2c_bus); + hsi2c_get_clk_details(i2c_bus, bus_freq_hz); n_clkdiv = i2c_bus->clk_div; t_scl_l = i2c_bus->clk_cycle / 2; @@ -341,7 +337,8 @@ static void i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) write32(i2c_ctl, &i2c->usi_ctl); /* Initialize the configure registers */ - hsi2c_ch_init(i2c_bus); + /* FIXME: This just assumes 100KHz as a default bus freq */ + hsi2c_ch_init(i2c_bus, 100000); } void i2c_init(unsigned bus_num, int speed, int slaveadd) @@ -352,12 +349,8 @@ void i2c_init(unsigned bus_num, int speed, int slaveadd) i2c_reset(i2c); - /* FIXME(dhendrix): hsi2c_ch_init doesn't take a speed or slaveadd - * parameter, so we should split it out and call it directly from - * romstage without the unneeded parameters. - */ if (i2c->is_highspeed) - hsi2c_ch_init(i2c); + hsi2c_ch_init(i2c, speed); else i2c_ch_init(i2c, speed, slaveadd); } [View Less]

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Patch set updated for coreboot: 267b43a pit: Configure the pinmux for the i2c busses that are connected on pit.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3702 -gerrit commit 267b43a09bf559ae4abc5568d7e5a314406debf7 Author: Gabe Black <gabeblack(a)google.com> Date: Sun Jun 23 03:16:46 2013 -0700 pit: Configure the pinmux for the i2c busses that are connected on pit. Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/… [View More]

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coreboot-gerrit July 2013