coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 8dfe60c exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3667 -gerrit commit 8dfe60cd6d482f4cac9d2ab38af3b376f161af3d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 20 15:21:48 2013 -0700 exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer At one time it seemed to be necessary to disable and then re-enable the MMU when setting the framebuffer to be … [View More]

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Patch set updated for coreboot: 2725d97 armv7: Reserve space BL1 and checksum header by specifying bootblock offset.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3664 -gerrit commit 2725d97da7c3cdf8f0195a4c196b725657064302 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue Jun 11 21:55:58 2013 -0700 armv7: Reserve space BL1 and checksum header by specifying bootblock offset. Not all ARM systems need "BL1", and the layout of BL* and bootblock may be different (ex, Exynos 5250 may use a new BL1 with … [View More]variable length checksum header). To support that better, define the real base address (and ROM offset) of boot block, and then we can post-processing ROM image file by filling data / checksum and any other information. Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 3 ++- src/arch/armv7/bootblock.inc | 8 ------ src/arch/armv7/bootblock.lds | 3 +-- src/cpu/samsung/exynos5250/Kconfig | 34 ++++++++++++++----------- src/cpu/samsung/exynos5420/Kconfig | 40 ++++++++++++++++++------------ src/mainboard/emulation/qemu-armv7/Kconfig | 4 +++ src/mainboard/ti/beaglebone/Kconfig | 12 +++++++++ 7 files changed, 63 insertions(+), 41 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 27a0df6..8474315 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -48,7 +48,8 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # TODO Change -b to Kconfig variable. $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ - -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \ + -B $(objcbfs)/bootblock.bin -a 64 \ + -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ -o $(CONFIG_CBFS_ROM_OFFSET) @printf " CBFS $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index bac32e2..b2c993a 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -29,14 +29,6 @@ * MA 02111-1307 USA */ -.section ".bl1", "a", %progbits -_bl1: - /* For now we have to live with a first stage boot loader - * on ARM, which is 8KB in size and it is prepended to the - * reset vector - */ - .skip (CONFIG_BL1_SIZE_KB * 1024) - .section ".start", "a", %progbits .globl _start _start: b reset diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds index 6f6040d..8370396 100644 --- a/src/arch/armv7/bootblock.lds +++ b/src/arch/armv7/bootblock.lds @@ -25,12 +25,11 @@ OUTPUT_ARCH(arm) TARGET(binary) SECTIONS { - ROMLOC = CONFIG_BOOTBLOCK_BASE - (CONFIG_BL1_SIZE_KB * 1024); + ROMLOC = CONFIG_BOOTBLOCK_BASE; /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; - *(.bl1); *(.start); *(.id); *(.text); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 5f5add4..75d1178 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -10,9 +10,26 @@ config EXYNOS_ACE_SHA bool default n -config BL1_SIZE_KB - int - default 8 +# ROM image layout. +# +# 0x0000: vendor-provided BL1 (8k). +# 0x2000: bootblock +# 0x2010-0x2090: reserved for CBFS master header. +# 0xA000: Free for CBFS data. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x2000 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x2010 + +config CBFS_ROM_OFFSET + # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0A000 + # Example SRAM/iRAM map for Exynos5250 platform: # @@ -50,17 +67,6 @@ config STACK_SIZE hex default 0x1000 -config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - hex "offset of CBFS data in ROM" - default 0x0A000 - -# TODO Change this to some better address not overlapping bootblock when -# cbfstool supports creating header in arbitrary location. -config CBFS_HEADER_ROM_OFFSET - hex "offset of master CBFS header in ROM" - default 0x2040 - # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 93ece2e..406ffd2 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -10,20 +10,39 @@ config EXYNOS_ACE_SHA bool default n -config BL1_SIZE_KB - int - default 8 +# ROM image layout. +# +# 0x0000: vendor-provided BL1 (8k). +# 0x2000: variable length bootblock checksum header +# 0x2010: bootblock +# 0x2020-0x20A0: reserved for CBFS master header. +# 0xA000: Free for CBFS data. + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x2010 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x2020 + +config CBFS_ROM_OFFSET + # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size. + hex "offset of CBFS data in ROM" + default 0x0A000 + # Example SRAM/iRAM map for Exynos5420 platform: # # 0x0202_0000: vendor-provided BL1 -# 0x0202_4400: bootblock, assume up to 32KB in size +# 0x0202_4400: variable length bootblock checksum header. +# 0x0202_4410: bootblock, assume up to 32KB in size # 0x0203_0000: romstage, assume up to 128KB in size. # 0x0207_4000: stack pointer config BOOTBLOCK_BASE hex - default 0x02024400 + default 0x02024410 config ROMSTAGE_BASE hex @@ -50,17 +69,6 @@ config STACK_SIZE hex default 0x1000 -config CBFS_ROM_OFFSET - # Calculated by BL1 + max bootblock size. - hex "offset of CBFS data in ROM" - default 0x0A000 - -# TODO Change this to some better address not overlapping bootblock when -# cbfstool supports creating header in arbitrary location. -config CBFS_HEADER_ROM_OFFSET - hex "offset of master CBFS header in ROM" - default 0x2040 - # TODO We may probably move this to board-specific implementation files instead # of KConfig values. config CBFS_CACHE_ADDRESS diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index b66761d..944e711 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -81,6 +81,10 @@ config ROMSTAGE_SIZE hex default 0x20000 +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + config CBFS_HEADER_ROM_OFFSET hex default 0x0100000 diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 1cde042..8651c9b 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -54,6 +54,18 @@ config NR_DRAM_BANKS int default 1 +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex + default 0x10 + +config CBFS_ROM_OFFSET + hex + default 0x5000 + choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 [View Less]

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Patch set updated for coreboot: 544ab86 exynos5420: Fix some problems with the clock management code.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3665 -gerrit commit 544ab86f10885e4bcd2eb1f1de3702e50edb4b5c Author: Gabe Black <gabeblack(a)google.com> Date: Thu Jun 6 00:14:08 2013 -0700 exynos5420: Fix some problems with the clock management code. The code which figured out the rate of the input clock to a peripheral was doing several things wrong. First, it was using the wrong values … [View More]when determing what the source of a clock was set to. Second, it was using the wrong offset into that register to find the current source setting. This change fixes the constants which select a clock source which get some more things working, but doesn't attempt to fix the bit position table. Change-Id: Id7482ee1c78cec274353bae3ce2dccb84705c66a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 11 ++++--- src/cpu/samsung/exynos5420/clock.c | 65 +++++++++++++++++--------------------- 2 files changed, 36 insertions(+), 40 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index b98a673..3d60b28 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -35,9 +35,13 @@ enum periph_id; #define SPLL 7 enum pll_src_bit { - EXYNOS_SRC_MPLL = 6, - EXYNOS_SRC_EPLL, - EXYNOS_SRC_VPLL, + EXYNOS_SRC_CPLL = 1, + EXYNOS_SRC_DPLL = 2, + EXYNOS_SRC_MPLL = 3, + EXYNOS_SRC_SPLL = 4, + EXYNOS_SRC_IPLL = 5, + EXYNOS_SRC_EPLL = 6, + EXYNOS_SRC_RPLL = 7, }; /* * @@ -46,7 +50,6 @@ enum pll_src_bit { */ struct clk_bit_info { s8 src_bit; /* offset in register to clock source field */ - s8 n_src_bits; /* number of bits in 'src_bit' field */ s8 div_bit; s8 prediv_bit; }; diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index fd15486..6e4701a 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -30,39 +30,35 @@ /* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { - {0, 4, 0, -1}, - {4, 4, 4, -1}, - {8, 4, 8, -1}, - {12, 4, 12, -1}, - {0, 4, 0, 8}, - {4, 4, 16, 24}, - {8, 4, 0, 8}, - {12, 4, 16, 24}, - {-1, -1, -1, -1}, - {16, 4, 0, 8}, /* PERIPH_ID_SROMC */ - {20, 4, 16, 24}, - {24, 4, 0, 8}, - {0, 4, 0, 4}, - {4, 4, 12, 16}, - {-1, 4, -1, -1}, - {-1, 4, -1, -1}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {-1, 4, 24, 0}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {24, 4, 0, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, - {-1, -1, -1, -1}, /* PERIPH_ID_I2S1 */ - {24, 1, 20, -1}, /* PERIPH_ID_SATA */ + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, /* PERIPH_ID_SROMC */ + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, }; /* Epll Clock division values to achive different frequency output */ @@ -221,9 +217,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case EXYNOS_SRC_EPLL: sclk = get_pll_clk(EPLL); break; - case EXYNOS_SRC_VPLL: - sclk = get_pll_clk(VPLL); - break; default: return 0; } [View Less]

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Patch set updated for coreboot: d10a876 exynox5420: Remove the 5250 clock registers and fix the SPI frequency.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3678 -gerrit commit d10a876e628f54ebece4a9ce6eb3086adcdfe39d Author: Gabe Black <gabeblack(a)google.com> Date: Tue Jun 18 06:08:42 2013 -0700 exynox5420: Remove the 5250 clock registers and fix the SPI frequency. The 5420 clock code still had a data structure in it for the 5250 clock registers which was used by some of the clock functions. … [View More]That caused some clocks to be configured incorrectly, specifically the i2c clock which was running at about 80KHz instead of about 600KHz as configured by U-Boot. Also, the registers and bit positions used to set up the SPI bus were not consistent with U-Boot, and if the bus clock rate were set to 50MHz, a rate which has historically worked on snow, loading would fail. With these fixes the clock rate can be set to 50MHz and the device boots as much as is expected. I haven't yet measured the actual frequency of the bus to verify that it's now being calculated correctly. Change-Id: Id53448fcb6d186bddb3f889c84ba267135dfbc00 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clk.h | 357 ------------------------------------- src/cpu/samsung/exynos5420/clock.c | 104 +++++------ src/cpu/samsung/exynos5420/cpu.h | 2 +- 3 files changed, 49 insertions(+), 414 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index 3d60b28..8e2f9ed 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -110,363 +110,6 @@ void clock_select_i2s_clk_source(void); */ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); -struct exynos5_clock { - uint32_t apll_lock; /* base + 0 */ - uint8_t res1[0xfc]; - uint32_t apll_con0; - uint32_t apll_con1; - uint8_t res2[0xf8]; - uint32_t src_cpu; - uint8_t res3[0x1fc]; - uint32_t mux_stat_cpu; - uint8_t res4[0xfc]; - uint32_t div_cpu0; - uint32_t div_cpu1; - uint8_t res5[0xf8]; - uint32_t div_stat_cpu0; - uint32_t div_stat_cpu1; - uint8_t res6[0x1f8]; - uint32_t gate_sclk_cpu; - uint8_t res7[0x1fc]; - uint32_t clkout_cmu_cpu; - uint32_t clkout_cmu_cpu_div_stat; - uint8_t res8[0x5f8]; - - uint32_t armclk_stopctrl; /* base + 0x1000 */ - uint32_t atclk_stopctrl; - uint8_t res9[0x8]; - uint32_t parityfail_status; - uint32_t parityfail_clear; - uint8_t res10[0x8]; - uint32_t pwr_ctrl; - uint32_t pwr_ctr2; - uint8_t res11[0xd8]; - uint32_t apll_con0_l8; - uint32_t apll_con0_l7; - uint32_t apll_con0_l6; - uint32_t apll_con0_l5; - uint32_t apll_con0_l4; - uint32_t apll_con0_l3; - uint32_t apll_con0_l2; - uint32_t apll_con0_l1; - uint32_t iem_control; - uint8_t res12[0xdc]; - uint32_t apll_con1_l8; - uint32_t apll_con1_l7; - uint32_t apll_con1_l6; - uint32_t apll_con1_l5; - uint32_t apll_con1_l4; - uint32_t apll_con1_l3; - uint32_t apll_con1_l2; - uint32_t apll_con1_l1; - uint8_t res13[0xe0]; - uint32_t div_iem_l8; - uint32_t div_iem_l7; - uint32_t div_iem_l6; - uint32_t div_iem_l5; - uint32_t div_iem_l4; - uint32_t div_iem_l3; - uint32_t div_iem_l2; - uint32_t div_iem_l1; - uint8_t res14[0x2ce0]; - - uint32_t mpll_lock; /* base + 0x4000 */ - uint8_t res15[0xfc]; - uint32_t mpll_con0; - uint32_t mpll_con1; - uint8_t res16[0xf8]; - uint32_t src_core0; - uint32_t src_core1; - uint8_t res17[0xf8]; - uint32_t src_mask_core; - uint8_t res18[0x100]; - uint32_t mux_stat_core1; - uint8_t res19[0xf8]; - uint32_t div_core0; - uint32_t div_core1; - uint32_t div_sysrgt; - uint8_t res20[0xf4]; - uint32_t div_stat_core0; - uint32_t div_stat_core1; - uint32_t div_stat_sysrgt; - uint8_t res21[0x2f4]; - uint32_t gate_ip_core; - uint32_t gate_ip_sysrgt; - uint8_t res22[0xf8]; - uint32_t clkout_cmu_core; - uint32_t clkout_cmu_core_div_stat; - uint8_t res23[0x5f8]; - - uint32_t dcgidx_map0; /* base + 0x5000 */ - uint32_t dcgidx_map1; - uint32_t dcgidx_map2; - uint8_t res24[0x14]; - uint32_t dcgperf_map0; - uint32_t dcgperf_map1; - uint8_t res25[0x18]; - uint32_t dvcidx_map; - uint8_t res26[0x1c]; - uint32_t freq_cpu; - uint32_t freq_dpm; - uint8_t res27[0x18]; - uint32_t dvsemclk_en; - uint32_t maxperf; - uint8_t res28[0x3478]; - - uint32_t div_acp; /* base + 0x8500 */ - uint8_t res29[0xfc]; - uint32_t div_stat_acp; - uint8_t res30[0x1fc]; - uint32_t gate_ip_acp; - uint8_t res31a[0xfc]; - uint32_t div_syslft; - uint8_t res31b[0xc]; - uint32_t div_stat_syslft; - uint8_t res31c[0xc]; - uint32_t gate_bus_syslft; - uint8_t res31d[0xdc]; - uint32_t clkout_cmu_acp; - uint32_t clkout_cmu_acp_div_stat; - uint8_t res32[0x38f8]; - - uint32_t div_isp0; /* base + 0xc300 */ - uint32_t div_isp1; - uint32_t div_isp2; - uint8_t res33[0xf4]; - - uint32_t div_stat_isp0; /* base + 0xc400 */ - uint32_t div_stat_isp1; - uint32_t div_stat_isp2; - uint8_t res34[0x3f4]; - - uint32_t gate_ip_isp0; /* base + 0xc800 */ - uint32_t gate_ip_isp1; - uint8_t res35[0xf8]; - uint32_t gate_sclk_isp; - uint8_t res36[0xc]; - uint32_t mcuisp_pwr_ctrl; - uint8_t res37[0xec]; - uint32_t clkout_cmu_isp; - uint32_t clkout_cmu_isp_div_stat; - uint8_t res38[0x3618]; - - uint32_t cpll_lock; /* base + 0x10020 */ - uint8_t res39[0xc]; - uint32_t epll_lock; - uint8_t res40[0xc]; - uint32_t vpll_lock; - uint8_t res41a[0xc]; - uint32_t gpll_lock; - uint8_t res41b[0xcc]; - uint32_t cpll_con0; - uint32_t cpll_con1; - uint8_t res42[0x8]; - uint32_t epll_con0; - uint32_t epll_con1; - uint32_t epll_con2; - uint8_t res43[0x4]; - uint32_t vpll_con0; - uint32_t vpll_con1; - uint32_t vpll_con2; - uint8_t res44a[0x4]; - uint32_t gpll_con0; - uint32_t gpll_con1; - uint8_t res44b[0xb8]; - uint32_t src_top0; - uint32_t src_top1; - uint32_t src_top2; - uint32_t src_top3; - uint32_t src_gscl; - uint32_t src_disp0_0; - uint32_t src_disp0_1; - uint32_t src_disp1_0; - uint32_t src_disp1_1; - uint8_t res46[0xc]; - uint32_t src_mau; - uint32_t src_fsys; - uint8_t res47[0x8]; - uint32_t src_peric0; - uint32_t src_peric1; - uint8_t res48[0x18]; - uint32_t sclk_src_isp; - uint8_t res49[0x9c]; - uint32_t src_mask_top; - uint8_t res50[0xc]; - uint32_t src_mask_gscl; - uint32_t src_mask_disp0_0; - uint32_t src_mask_disp0_1; - uint32_t src_mask_disp1_0; - uint32_t src_mask_disp1_1; - uint32_t src_mask_maudio; - uint8_t res52[0x8]; - uint32_t src_mask_fsys; - uint8_t res53[0xc]; - uint32_t src_mask_peric0; - uint32_t src_mask_peric1; - uint8_t res54[0x18]; - uint32_t src_mask_isp; - uint8_t res55[0x9c]; - uint32_t mux_stat_top0; - uint32_t mux_stat_top1; - uint32_t mux_stat_top2; - uint32_t mux_stat_top3; - uint8_t res56[0xf0]; - uint32_t div_top0; - uint32_t div_top1; - uint8_t res57[0x8]; - uint32_t div_gscl; - uint32_t div_disp0_0; - uint32_t div_disp0_1; - uint32_t div_disp1_0; - uint32_t div_disp1_1; - uint8_t res59[0x8]; - uint32_t div_gen; - uint8_t res60[0x4]; - uint32_t div_mau; - uint32_t div_fsys0; - uint32_t div_fsys1; - uint32_t div_fsys2; - uint32_t div_fsys3; - uint32_t div_peric0; - uint32_t div_peric1; - uint32_t div_peric2; - uint32_t div_peric3; - uint32_t div_peric4; - uint32_t div_peric5; - uint8_t res61[0x10]; - uint32_t sclk_div_isp; - uint8_t res62[0xc]; - uint32_t div2_ratio0; - uint32_t div2_ratio1; - uint8_t res63[0x8]; - uint32_t div4_ratio; - uint8_t res64[0x6c]; - uint32_t div_stat_top0; - uint32_t div_stat_top1; - uint8_t res65[0x8]; - uint32_t div_stat_gscl; - uint32_t div_stat_disp0_0; - uint32_t div_stat_disp0_1; - uint32_t div_stat_disp1_0; - uint32_t div_stat_disp1_1; - uint8_t res67[0x8]; - uint32_t div_stat_gen; - uint8_t res68[0x4]; - uint32_t div_stat_maudio; - uint32_t div_stat_fsys0; - uint32_t div_stat_fsys1; - uint32_t div_stat_fsys2; - uint32_t div_stat_fsys3; - uint32_t div_stat_peric0; - uint32_t div_stat_peric1; - uint32_t div_stat_peric2; - uint32_t div_stat_peric3; - uint32_t div_stat_peric4; - uint32_t div_stat_peric5; - uint8_t res69[0x10]; - uint32_t sclk_div_stat_isp; - uint8_t res70[0xc]; - uint32_t div2_stat0; - uint32_t div2_stat1; - uint8_t res71[0x8]; - uint32_t div4_stat; - uint8_t res72[0x180]; - uint32_t gate_top_sclk_disp0; - uint32_t gate_top_sclk_disp1; - uint32_t gate_top_sclk_gen; - uint8_t res74[0xc]; - uint32_t gate_top_sclk_mau; - uint32_t gate_top_sclk_fsys; - uint8_t res75[0xc]; - uint32_t gate_top_sclk_peric; - uint8_t res76[0x1c]; - uint32_t gate_top_sclk_isp; - uint8_t res77[0xac]; - uint32_t gate_ip_gscl; - uint32_t gate_ip_disp0; - uint32_t gate_ip_disp1; - uint32_t gate_ip_mfc; - uint32_t gate_ip_g3d; - uint32_t gate_ip_gen; - uint8_t res79[0xc]; - uint32_t gate_ip_fsys; - uint8_t res80[0x4]; - uint32_t gate_ip_gps; - uint32_t gate_ip_peric; - uint8_t res81[0xc]; - uint32_t gate_ip_peris; - uint8_t res82[0x1c]; - uint32_t gate_block; - uint8_t res83[0x7c]; - uint32_t clkout_cmu_top; - uint32_t clkout_cmu_top_div_stat; - uint8_t res84[0x37f8]; - - uint32_t src_lex; /* base + 0x14200 */ - uint8_t res85[0x1fc]; - uint32_t mux_stat_lex; - uint8_t res85b[0xfc]; - uint32_t div_lex; - uint8_t res86[0xfc]; - uint32_t div_stat_lex; - uint8_t res87[0x1fc]; - uint32_t gate_ip_lex; - uint8_t res88[0x1fc]; - uint32_t clkout_cmu_lex; - uint32_t clkout_cmu_lex_div_stat; - uint8_t res89[0x3af8]; - - uint32_t div_r0x; /* base + 0x18500 */ - uint8_t res90[0xfc]; - uint32_t div_stat_r0x; - uint8_t res91[0x1fc]; - uint32_t gate_ip_r0x; - uint8_t res92[0x1fc]; - uint32_t clkout_cmu_r0x; - uint32_t clkout_cmu_r0x_div_stat; - uint8_t res94[0x3af8]; - - uint32_t div_r1x; /* base + 0x1c500 */ - uint8_t res95[0xfc]; - uint32_t div_stat_r1x; - uint8_t res96[0x1fc]; - uint32_t gate_ip_r1x; - uint8_t res97[0x1fc]; - uint32_t clkout_cmu_r1x; - uint32_t clkout_cmu_r1x_div_stat; - uint8_t res98[0x3608]; - - uint32_t bpll_lock; /* base + 0x2000c */ - uint8_t res99[0xfc]; - uint32_t bpll_con0; - uint32_t bpll_con1; - uint8_t res100[0xe8]; - uint32_t src_cdrex; - uint8_t res101[0x1fc]; - uint32_t mux_stat_cdrex; - uint8_t res102[0xfc]; - uint32_t div_cdrex; - uint32_t div_cdrex2; - uint8_t res103[0xf8]; - uint32_t div_stat_cdrex; - uint8_t res104[0x2fc]; - uint32_t gate_ip_cdrex; - uint8_t res105[0xc]; - uint32_t c2c_monitor; - uint32_t dmc_pwr_ctrl; - uint8_t res106[0x4]; - uint32_t drex2_pause; - uint8_t res107[0xe0]; - uint32_t clkout_cmu_cdrex; - uint32_t clkout_cmu_cdrex_div_stat; - uint8_t res108[0x8]; - uint32_t lpddr3phy_ctrl; - uint8_t res109a[0xc]; - uint32_t lpddr3phy_con3; - uint32_t pll_div2_sel; - uint8_t res109b[0xf5e4]; -}; - struct exynos5420_clock { uint32_t apll_lock; /* 0x10010000 */ uint8_t res1[0xfc]; diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 8799149..e5ab001 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -69,8 +69,7 @@ static struct st_epll_con_val epll_div[] = { /* exynos5: return pll clock frequency */ unsigned long get_pll_clk(int pllreg) { - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; unsigned int freq; @@ -146,44 +145,44 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; unsigned long sclk, sub_clk; unsigned int src, div, sub_div; - struct exynos5_clock *clk = samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); switch (peripheral) { case PERIPH_ID_UART0: case PERIPH_ID_UART1: case PERIPH_ID_UART2: case PERIPH_ID_UART3: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric0); + src = readl(&clk->clk_src_peric0); + div = readl(&clk->clk_div_peric0); break; case PERIPH_ID_PWM0: case PERIPH_ID_PWM1: case PERIPH_ID_PWM2: case PERIPH_ID_PWM3: case PERIPH_ID_PWM4: - src = readl(&clk->src_peric0); - div = readl(&clk->div_peric3); + src = readl(&clk->clk_src_peric0); + div = readl(&clk->clk_div_peric3); break; case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: - src = readl(&clk->src_peric1); - div = readl(&clk->div_peric1); + src = readl(&clk->clk_src_peric1); + div = readl(&clk->clk_div_peric1); break; case PERIPH_ID_SPI2: - src = readl(&clk->src_peric1); - div = readl(&clk->div_peric2); + src = readl(&clk->clk_src_peric1); + div = readl(&clk->clk_div_peric2); break; case PERIPH_ID_SPI3: case PERIPH_ID_SPI4: - src = readl(&clk->sclk_src_isp); - div = readl(&clk->sclk_div_isp); + src = readl(&clk->clk_src_isp); + div = readl(&clk->clk_div_isp1); break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: - src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); + src = readl(&clk->clk_src_fsys); + div = readl(&clk->clk_div_fsys1); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -197,8 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) case PERIPH_ID_I2C9: case PERIPH_ID_I2C10: sclk = get_pll_clk(MPLL); - sub_div = ((readl(&clk->div_top1) >> 24) & 0x7) + 1; - div = (readl(&clk->div_top0) & 0x7) + 1; + sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1; + div = (readl(&clk->clk_div_top0) & 0x7) + 1; return (sclk / sub_div) / div; default: printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral); @@ -234,13 +233,13 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral) /* exynos5: return ARM clock frequency */ unsigned long get_arm_clk(void) { - struct exynos5_clock *clk = samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned long div; unsigned long armclk; unsigned int arm_ratio; unsigned int arm2_ratio; - div = readl(&clk->div_cpu0); + div = readl(&clk->clk_div_cpu0); /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ arm_ratio = (div >> 0) & 0x7; @@ -255,8 +254,7 @@ unsigned long get_arm_clk(void) /* exynos5: set the mmc clock */ void set_mmc_clk(int dev_index, unsigned int div) { - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); void *addr; unsigned int val, shift; @@ -271,8 +269,7 @@ void set_mmc_clk(int dev_index, unsigned int div) void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; @@ -287,24 +284,24 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) */ switch (periph_id) { case PERIPH_ID_SPI0: - reg = &clk->div_peric1; + reg = &clk->clk_div_peric4; shift = 8; break; case PERIPH_ID_SPI1: - reg = &clk->div_peric1; - shift = 24; + reg = &clk->clk_div_peric4; + shift = 16; break; case PERIPH_ID_SPI2: - reg = &clk->div_peric2; - shift = 8; + reg = &clk->clk_div_peric4; + shift = 24; break; case PERIPH_ID_SPI3: - reg = &clk->sclk_div_isp; - shift = 4; + reg = &clk->clk_div_isp1; + shift = 0; break; case PERIPH_ID_SPI4: - reg = &clk->sclk_div_isp; - shift = 16; + reg = &clk->clk_div_isp1; + shift = 8; break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, @@ -316,32 +313,31 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned shift; unsigned mask = 0xff; u32 *reg; switch (periph_id) { case PERIPH_ID_SPI0: - reg = &clk->div_peric1; - shift = 0; + reg = &clk->clk_div_peric1; + shift = 20; break; case PERIPH_ID_SPI1: - reg = &clk->div_peric1; - shift = 16; + reg = &clk->clk_div_peric1; + shift = 24; break; case PERIPH_ID_SPI2: - reg = &clk->div_peric2; - shift = 0; + reg = &clk->clk_div_peric1; + shift = 28; break; case PERIPH_ID_SPI3: - reg = &clk->sclk_div_isp; - shift = 0; + reg = &clk->clk_div_isp1; + shift = 16; break; case PERIPH_ID_SPI4: - reg = &clk->sclk_div_isp; - shift = 12; + reg = &clk->clk_div_isp1; + shift = 20; break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, @@ -441,8 +437,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) int clock_set_mshci(enum periph_id peripheral) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); u32 *addr; unsigned int clock; unsigned int tmp; @@ -459,10 +454,10 @@ int clock_set_mshci(enum periph_id peripheral) */ switch (peripheral) { case PERIPH_ID_SDMMC0: - addr = &clk->div_fsys1; + addr = &clk->clk_div_fsys1; break; case PERIPH_ID_SDMMC2: - addr = &clk->div_fsys2; + addr = &clk->clk_div_fsys2; break; default: printk(BIOS_DEBUG, "invalid peripheral\n"); @@ -484,8 +479,7 @@ int clock_epll_set_rate(unsigned long rate) unsigned int i; unsigned int lockcnt; unsigned int start; - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); epll_con = readl(&clk->epll_con0); epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << @@ -534,17 +528,15 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); - clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, + clrsetbits_le32(&clk->clk_src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); } int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) { - struct exynos5_clock *clk = - samsung_get_base_clock(); + struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned int div ; if ((dst_frq == 0) || (src_frq == 0)) { @@ -559,7 +551,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } - clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, + clrsetbits_le32(&clk->clk_div_peric4, AUDIO_1_RATIO_MASK, (div & AUDIO_1_RATIO_MASK)); return 0; } diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 05be3cc..7d0a5d5 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -170,7 +170,7 @@ #define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 #define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE) -#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE) +#define samsung_get_base_clock() ((struct exynos5420_clock *)EXYNOS5_CLOCK_BASE) #define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE) #define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE) #define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE) [View Less]

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Patch set updated for coreboot: 09f3eb9 ARM: when setting a GPIO to put, set the value, then the direction
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3679 -gerrit commit 09f3eb94659e9917334933d89717c4215eb642b4 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Jun 18 13:02:23 2013 -0700 ARM: when setting a GPIO to put, set the value, then the direction We saw a problem on x86 last year in which setting direction, then value, glitched the output and caused problems. Change this … [View More]

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Patch set updated for coreboot: fe4756c exynos5420: add I2C8-10 to clock_get_periph_rate()
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3676 -gerrit commit fe4756ccb2b44c35d6772505dcb995875e1b16ed Author: David Hendricks <dhendrix(a)chromium.org> Date: Sat Jun 15 19:22:06 2013 -0700 exynos5420: add I2C8-10 to clock_get_periph_rate() This adds entries for I2C8-10 to giant switch statement in clock_get_periph_rate(). It also eliminates the I2C peripheral's usage of … [View More]

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Patch set updated for coreboot: 7399978 PIT: memory setup
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3677 -gerrit commit 7399978d690d8af6d2788d52750b7b9286ec6391 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Jun 3 13:03:50 2013 -0700 PIT: memory setup Tested and working. Gets us to ramstage. Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Signed-… [View More]off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/clock_init.c | 1 + src/cpu/samsung/exynos5420/cpu.h | 76 +++++ src/cpu/samsung/exynos5420/dmc.h | 208 ++++++++----- src/cpu/samsung/exynos5420/dmc_common.c | 11 +- src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 459 +++++++++++++++++------------ src/cpu/samsung/exynos5420/power.c | 1 + src/cpu/samsung/exynos5420/setup.h | 158 +++++++++- src/mainboard/google/pit/Kconfig | 1 + src/mainboard/google/pit/memory.c | 457 +--------------------------- src/mainboard/google/pit/romstage.c | 97 +++++- 10 files changed, 738 insertions(+), 731 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 0a13c9e..2ce975c 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -24,6 +24,7 @@ #include "clk.h" #include "cpu.h" #include "dp.h" +#include "dmc.h" #include "setup.h" void system_clock_init(void) diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 7cdd35e..05be3cc 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -93,6 +93,82 @@ /* Distance between each Trust Zone PC register set */ #define TZPC_BASE_OFFSET 0x10000 +/* EXYNOS5420 Common*/ +#define EXYNOS5420_I2C_SPACING 0x10000 + +#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 +#define EXYNOS5420_PRO_ID 0x10000000 +#define EXYNOS5420_CLOCK_BASE 0x10010000 +#define EXYNOS5420_POWER_BASE 0x10040000 +#define EXYNOS5420_SWRESET 0x10040400 +#define EXYNOS5420_SYSREG_BASE 0x10050000 +#define EXYNOS5420_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5420_DMC_PHY0_BASE 0x10C00000 +#define EXYNOS5420_DMC_PHY1_BASE 0x10C10000 +#define EXYNOS5420_DMC_DREXI_0 0x10C20000 +#define EXYNOS5420_DMC_DREXI_1 0x10C30000 +#define EXYNOS5420_DMC_TZASC_0 0x10D40000 +#define EXYNOS5420_DMC_TZASC_1 0x10D50000 +#define EXYNOS5420_USB_HOST_XHCI_BASE 0x12000000 +#define EXYNOS5420_USB3PHY_BASE 0x12100000 +#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000 +#define EXYNOS5420_MMC_BASE 0x12200000 +#define EXYNOS5420_SROMC_BASE 0x12250000 +#define EXYNOS5420_UART_BASE 0x12C00000 +#define EXYNOS5420_I2C_BASE 0x12C60000 +#define EXYNOS5420_I2C_8910_BASE 0x12E00000 +#define EXYNOS5420_SPI_BASE 0x12D20000 +#define EXYNOS5420_I2S_BASE 0x12D60000 +#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5420_SPI_ISP_BASE 0x131A0000 +#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 +#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 +#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 +#define EXYNOS5420_DP_BASE 0x145B0000 +#define EXYNOS5420_INF_REG_BASE 0x10040800 + +#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE + +#define ARM_CORE0_CONFIG (EXYNOS5420_POWER_BASE + 0x2000) +#define ARM_CORE0_STATUS (EXYNOS5420_POWER_BASE + 0x2004) +#define CORE_CONFIG_OFFSET 0x80 +#define CORE_COUNT 0x8 + +/* + * POWER + */ +#define PMU_BASE EXYNOS5420_POWER_BASE +#define SW_RST_REG_OFFSET 0x400 + +#define INF_REG_BASE EXYNOS5420_INF_REG_BASE +#define INF_REG0_OFFSET 0x00 +#define INF_REG1_OFFSET 0x04 +#define INF_REG2_OFFSET 0x08 +#define INF_REG3_OFFSET 0x0C +#define INF_REG4_OFFSET 0x10 +#define INF_REG5_OFFSET 0x14 +#define INF_REG6_OFFSET 0x18 +#define INF_REG7_OFFSET 0x1C + +#define PMU_SPARE_BASE (EXYNOS5420_INF_REG_BASE + 0x100) +#define PMU_SPARE_0 PMU_SPARE_BASE +#define PMU_SPARE_1 (PMU_SPARE_BASE + 0x4) +#define PMU_SPARE_2 (PMU_SPARE_BASE + 0x8) +#define PMU_SPARE_3 (PMU_SPARE_BASE + 0xc) +#define RST_FLAG_REG PMU_SPARE_BASE +#define RST_FLAG_VAL 0xfcba0d10 + +#define PAD_RETENTION_DRAM_STATUS (EXYNOS5420_POWER_BASE + 0x3004) +#define PAD_RETENTION_DRAM_COREBLK_OPTION (EXYNOS5420_POWER_BASE + 0x31E8) +#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000 + #define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE) #define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE) #define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE) diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h index cd5ff23..df7797d 100644 --- a/src/cpu/samsung/exynos5420/dmc.h +++ b/src/cpu/samsung/exynos5420/dmc.h @@ -18,17 +18,68 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_DMC_H #define CPU_SAMSUNG_EXYNOS5420_DMC_H +#define DMC_INTERLEAVE_SIZE 0x1f + +/* CONCONTROL register fields */ +#define CONCONTROL_DFI_INIT_START_SHIFT 28 +#define CONCONTROL_RD_FETCH_SHIFT 12 +#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) +#define CONCONTROL_AREF_EN_SHIFT 5 + +/* PRECHCONFIG register field */ +#define PRECHCONFIG_TP_CNT_SHIFT 24 + +/* PWRDNCONFIG register field */ +#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 +#define PWRDNCONFIG_DSREF_CYC_SHIFT 16 + +/* PHY_CON0 register fields */ +#define PHY_CON0_T_WRRDCMD_SHIFT 17 +#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) +#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3 +#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 + +/* PHY_CON1 register fields */ +#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 + +/* PHY_CON12 register fields */ +#define PHY_CON12_CTRL_START_POINT_SHIFT 24 +#define PHY_CON12_CTRL_INC_SHIFT 16 +#define PHY_CON12_CTRL_FORCE_SHIFT 8 +#define PHY_CON12_CTRL_START_SHIFT 6 +#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) +#define PHY_CON12_CTRL_DLL_ON_SHIFT 5 +#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) +#define PHY_CON12_CTRL_REF_SHIFT 1 + +/* PHY_CON16 register fields */ +#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 +#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) + +#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 +#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) + +#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) + +/* PHY_CON42 register fields */ +#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 +#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) + +#define PHY_CON42_CTRL_RDLAT_SHIFT 0 +#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) + #ifndef __ASSEMBLER__ struct exynos5_dmc { unsigned int concontrol; unsigned int memcontrol; - unsigned int memconfig0; + unsigned int cgcontrol; unsigned int memconfig1; unsigned int directcmd; - unsigned int prechconfig; + unsigned int prechconfig0; unsigned int phycontrol0; - unsigned char res1[0xc]; - unsigned int pwrdnconfig; + unsigned int prechconfig1; + unsigned char res1[0x8]; + unsigned int pwrdnconfig; /* 0x0028*/ unsigned int timingpzq; unsigned int timingref; unsigned int timingrow; @@ -36,12 +87,12 @@ struct exynos5_dmc { unsigned int timingpower; unsigned int phystatus; unsigned char res2[0x4]; - unsigned int chipstatus_ch0; + unsigned int chipstatus_ch0; /* 0x0048 */ unsigned int chipstatus_ch1; unsigned char res3[0x4]; unsigned int mrstatus; unsigned char res4[0x8]; - unsigned int qoscontrol0; + unsigned int qoscontrol0; /* 0x0060 */ unsigned char resr5[0x4]; unsigned int qoscontrol1; unsigned char res6[0x4]; @@ -72,45 +123,83 @@ struct exynos5_dmc { unsigned int qoscontrol14; unsigned char res19[0x4]; unsigned int qoscontrol15; - unsigned char res20[0x14]; + unsigned char res20[0x4]; + unsigned int timing_set_sw; /* 0x00e0 */ + unsigned int timingrow1; + unsigned int timingdata1; + unsigned int timingpower1; unsigned int ivcontrol; unsigned int wrtra_config; unsigned int rdlvl_config; - unsigned char res21[0x8]; + unsigned char res21[0x4]; + unsigned int brbrsvcontrol; /* 0x0100*/ unsigned int brbrsvconfig; unsigned int brbqosconfig; unsigned int membaseconfig0; - unsigned int membaseconfig1; + unsigned int membaseconfig1; /* 0x0110 */ unsigned char res22[0xc]; - unsigned int wrlvl_config; - unsigned char res23[0xc]; - unsigned int perevcontrol; + unsigned int wrlvl_config0; /* 0x0120 */ + unsigned int wrlvl_config1; + unsigned int wrlvl_status; + unsigned char res23[0x4]; + unsigned int perevcontrol; /* 0x0130 */ unsigned int perev0config; unsigned int perev1config; unsigned int perev2config; unsigned int perev3config; - unsigned char res24[0xdebc]; - unsigned int pmnc_ppc_a; - unsigned char res25[0xc]; - unsigned int cntens_ppc_a; - unsigned char res26[0xc]; - unsigned int cntenc_ppc_a; - unsigned char res27[0xc]; - unsigned int intens_ppc_a; - unsigned char res28[0xc]; - unsigned int intenc_ppc_a; - unsigned char res29[0xc]; - unsigned int flag_ppc_a; - unsigned char res30[0xac]; - unsigned int ccnt_ppc_a; - unsigned char res31[0xc]; - unsigned int pmcnt0_ppc_a; + unsigned char res22a[0xc]; + unsigned int ctrl_io_rdata_ch0; + unsigned int ctrl_io_rdata_ch1; + unsigned char res23a[0x8]; + unsigned int cacal_config0; + unsigned int cacal_config1; + unsigned int cacal_status; + unsigned char res24[0x94]; + unsigned int emergent_config0; /* 0x0200 */ + unsigned int emergent_config1; + unsigned char res25[0x8]; + unsigned int bp_control0; + unsigned int bp_control0_r; + unsigned int bp_control0_w; + unsigned char res26[0x4]; + unsigned int bp_control1; + unsigned int bp_control1_r; + unsigned int bp_control1_w; + unsigned char res27[0x4]; + unsigned int bp_control2; + unsigned int bp_control2_r; + unsigned int bp_control2_w; + unsigned char res28[0x4]; + unsigned int bp_control3; + unsigned int bp_control3_r; + unsigned int bp_control3_w; + unsigned char res29[0xb4]; + unsigned int winconfig_odt_w; /* 0x0300 */ + unsigned char res30[0x4]; + unsigned int winconfig_ctrl_read; + unsigned int winconfig_ctrl_gate; + unsigned char res31[0xdcf0]; + unsigned int pmnc_ppc; unsigned char res32[0xc]; - unsigned int pmcnt1_ppc_a; + unsigned int cntens_ppc; unsigned char res33[0xc]; - unsigned int pmcnt2_ppc_a; + unsigned int cntenc_ppc; unsigned char res34[0xc]; - unsigned int pmcnt3_ppc_a; + unsigned int intens_ppc; + unsigned char res35[0xc]; + unsigned int intenc_ppc; + unsigned char res36[0xc]; + unsigned int flag_ppc; /* 0xe050 */ + unsigned char res37[0xac]; + unsigned int ccnt_ppc; + unsigned char res38[0xc]; + unsigned int pmcnt0_ppc; + unsigned char res39[0xc]; + unsigned int pmcnt1_ppc; + unsigned char res40[0xc]; + unsigned int pmcnt2_ppc; + unsigned char res41[0xc]; + unsigned int pmcnt3_ppc; /* 0xe140 */ }; struct exynos5_phy_control { @@ -160,6 +249,15 @@ struct exynos5_phy_control { unsigned int phy_con42; }; +struct exynos5_tzasc { + unsigned char res1[0xf00]; + unsigned int membaseconfig0; + unsigned int membaseconfig1; + unsigned char res2[0x8]; + unsigned int memconfig0; + unsigned int memconfig1; +}; + enum ddr_mode { DDR_MODE_DDR2, DDR_MODE_DDR3, @@ -196,54 +294,6 @@ enum { MEM_TIMINGS_MSR_COUNT = 4, }; -#define DMC_INTERLEAVE_SIZE 0x1f - -/* CONCONTROL register fields */ -#define CONCONTROL_DFI_INIT_START_SHIFT 28 -#define CONCONTROL_RD_FETCH_SHIFT 12 -#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) -#define CONCONTROL_AREF_EN_SHIFT 5 - -/* PRECHCONFIG register field */ -#define PRECHCONFIG_TP_CNT_SHIFT 24 - -/* PWRDNCONFIG register field */ -#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0 -#define PWRDNCONFIG_DSREF_CYC_SHIFT 16 - -/* PHY_CON0 register fields */ -#define PHY_CON0_T_WRRDCMD_SHIFT 17 -#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT) -#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11 - -/* PHY_CON1 register fields */ -#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 - -/* PHY_CON12 register fields */ -#define PHY_CON12_CTRL_START_POINT_SHIFT 24 -#define PHY_CON12_CTRL_INC_SHIFT 16 -#define PHY_CON12_CTRL_FORCE_SHIFT 8 -#define PHY_CON12_CTRL_START_SHIFT 6 -#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT) -#define PHY_CON12_CTRL_DLL_ON_SHIFT 5 -#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT) -#define PHY_CON12_CTRL_REF_SHIFT 1 - -/* PHY_CON16 register fields */ -#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24 -#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT) - -#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21 -#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT) - -#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19) - -/* PHY_CON42 register fields */ -#define PHY_CON42_CTRL_BSTLEN_SHIFT 8 -#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT) - -#define PHY_CON42_CTRL_RDLAT_SHIFT 0 -#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT) /* These are the memory timings for a particular memory type and speed */ struct mem_timings { diff --git a/src/cpu/samsung/exynos5420/dmc_common.c b/src/cpu/samsung/exynos5420/dmc_common.c index 3abc3d3..bef76d1 100644 --- a/src/cpu/samsung/exynos5420/dmc_common.c +++ b/src/cpu/samsung/exynos5420/dmc_common.c @@ -23,10 +23,9 @@ #include <console/console.h> #include <arch/io.h> #include <delay.h> -#include "setup.h" #include "dmc.h" -#include "clk.h" #include "setup.h" +#include "clk.h" #define ZQ_INIT_TIMEOUT 10000 @@ -173,11 +172,3 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) } } -void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc) -{ - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0); - writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1); -} - diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c index 2d78087..74ee7e9 100644 --- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c @@ -1,11 +1,17 @@ /* * This file is part of the coreboot project. * + * DDR3 mem setup file for EXYNOS5 based board + * * Copyright (C) 2012 Samsung Electronics * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -14,181 +20,181 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ -/* DDR3 mem setup file for SMDK5420 board based on EXYNOS5 */ - #include <console/console.h> #include <delay.h> #include <arch/io.h> -#include "clk.h" -#include "cpu.h" #include "dmc.h" #include "setup.h" +#include "cpu.h" +#include "clk.h" -#define RDLVL_COMPLETE_TIMEOUT 10000 +#define TIMEOUT 10000 -static void reset_phy_ctrl(void) -{ - struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; - - writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); - writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); - -#if 0 - /* - * For proper memory initialization there should be a minimum delay of - * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal. - * The below value is an approximate value whose calculation in done - * considering that sdelay takes 2 instruction for every 1 delay cycle. - * And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec - * So for 500 usec, the number of delay cycle should be - * (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000 - * - * TODO(hatim.rv(a)samsung.com): Implement the delay using timer/counter - */ - sdelay(425000); -#endif - udelay(500); -} +/* 'reset' field is currently ignored. */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int mem_reset) +int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) { - unsigned int val; + struct exynos5420_clock *clk = + (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; - struct exynos5_dmc *dmc; + struct exynos5_dmc *drex0, *drex1; + struct exynos5_tzasc *tzasc0, *tzasc1; + u32 val, nLockR, nLockW_phy0, nLockW_phy1; int i; phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE; phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE; - dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE; - - if (mem_reset) { - printk(BIOS_SPEW, "%s: reset phy: ", __func__); - reset_phy_ctrl(); - printk(BIOS_SPEW, "done\n"); - } else { - printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__); - } + drex0 = (struct exynos5_dmc *)EXYNOS5420_DMC_DREXI_0; + drex1 = (struct exynos5_dmc *)EXYNOS5420_DMC_DREXI_1; + tzasc0 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC_0; + tzasc1 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC_1; - /* Set Impedance Output Driver */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: mem->impedance 0x%x\n", - mem->impedance); - val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | - (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | - (mem->impedance << CA_CS_DRVR_DS_OFFSET) | - (mem->impedance << CA_ADR_DRVR_DS_OFFSET); - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: val 0x%x\n", val); - writel(val, &phy0_ctrl->phy_con39); - writel(val, &phy1_ctrl->phy_con39); + /* Enable PAUSE for DREX */ + setbits_le32(&clk->pause, ENABLE_BIT); + + /* Enable BYPASS mode */ + setbits_le32(&clk->bpll_con1, BYPASS_EN); + + writel(MUX_BPLL_SEL_FOUTBPLL, &clk->clk_src_cdrex); + do { + val = readl(&clk->clk_mux_stat_cdrex); + val &= BPLL_SEL_MASK; + } while (val != FOUTBPLL); + + clrbits_le32(&clk->bpll_con1, BYPASS_EN); + + /* Specify the DDR memory type as DDR3 */ + val = readl(&phy0_ctrl->phy_con0); + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + writel(val, &phy0_ctrl->phy_con0); + + val = readl(&phy1_ctrl->phy_con0); + val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); + val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); + writel(val, &phy1_ctrl->phy_con0); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Set Read Latency and Burst Length for PHY0 and PHY1\n"); val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); writel(val, &phy0_ctrl->phy_con42); writel(val, &phy1_ctrl->phy_con42); + val = readl(&phy0_ctrl->phy_con26); + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); + writel(val, &phy0_ctrl->phy_con26); + + val = readl(&phy1_ctrl->phy_con26); + val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); + val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); + writel(val, &phy1_ctrl->phy_con26); + + /* Set Driver strength for CK, CKE, CS & CA to 0x7 + * Set Driver strength for Data Slice 0~3 to 0x6 + */ + val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | + (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET); + val |= (0x6 << DA_3_DS_OFFSET) | (0x6 << DA_2_DS_OFFSET) | + (0x6 << DA_1_DS_OFFSET) | (0x6 << DA_0_DS_OFFSET); + writel(val, &phy0_ctrl->phy_con39); + writel(val, &phy1_ctrl->phy_con39); + /* ZQ Calibration */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: ZQ Calibration\n"); if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) return SETUP_ERR_ZQ_CALIBRATION_FAILURE; + clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN); + clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN); + /* DQ Signal */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQ Signal\n"); writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14); - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), - &dmc->concontrol); - - update_reset_dll(dmc, DDR_MODE_DDR3); - - /* DQS Signal */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: DQS Signal\n"); - writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); - writel(mem->phy1_dqs, &phy1_ctrl->phy_con4); - - writel(mem->phy0_dq, &phy0_ctrl->phy_con6); - writel(mem->phy1_dq, &phy1_ctrl->phy_con6); - - writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); - writel(mem->phy1_tFS, &phy1_ctrl->phy_con10); - - val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | - (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | - (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | - (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); - - /* Start DLL locking */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Start DLL Locking\n"); - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &phy0_ctrl->phy_con12); - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &phy1_ctrl->phy_con12); - - update_reset_dll(dmc, DDR_MODE_DDR3); - - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &dmc->concontrol); - - /* Memory Channel Inteleaving Size */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Memory Channel Inteleaving Size\n"); - writel(mem->iv_size, &dmc->ivcontrol); - - /* Set DMC MEMCONTROL register */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set DMC MEMCONTROL register\n"); - val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; - writel(val, &dmc->memcontrol); - - writel(mem->memconfig, &dmc->memconfig0); - writel(mem->memconfig, &dmc->memconfig1); - writel(mem->membaseconfig0, &dmc->membaseconfig0); - writel(mem->membaseconfig1, &dmc->membaseconfig1); + val = MEM_TERM_EN | PHY_TERM_EN; + writel(val, &drex0->phycontrol0); + writel(val, &drex1->phycontrol0); + + writel(mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex0->concontrol); + writel(mem->concontrol | + (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex1->concontrol); + + do { + val = readl(&drex0->phystatus); + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); + do { + val = readl(&drex1->phystatus); + } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); + + clrbits_le32(&drex0->concontrol, DFI_INIT_START); + clrbits_le32(&drex1->concontrol, DFI_INIT_START); + + update_reset_dll(drex0, DDR_MODE_DDR3); + update_reset_dll(drex1, DDR_MODE_DDR3); + + /* Set Base Address: + * 0x2000_0000 ~ 0x5FFF_FFFF + * 0x6000_0000 ~ 0x9FFF_FFFF + */ + /* MEMBASECONFIG0 */ + val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) | + DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK); + writel(val, &tzasc0->membaseconfig0); + writel(val, &tzasc1->membaseconfig0); + + /* MEMBASECONFIG1 */ + val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) | + DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK); + writel(val, &tzasc0->membaseconfig1); + writel(val, &tzasc1->membaseconfig1); + + /* Memory Channel Inteleaving Size + * Exynos5420 Channel interleaving = 128 bytes + */ + /* MEMCONFIG0/1 */ + writel(mem->memconfig, &tzasc0->memconfig0); + writel(mem->memconfig, &tzasc1->memconfig0); + writel(mem->memconfig, &tzasc0->memconfig1); + writel(mem->memconfig, &tzasc1->memconfig1); /* Precharge Configuration */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Precharge Configuration\n"); writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &dmc->prechconfig); - - /* Power Down mode Configuration */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Power Down mode Configuraation\n"); - writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | - mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, - &dmc->pwrdnconfig); + &drex0->prechconfig0); + writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, + &drex1->prechconfig0); /* TimingRow, TimingData, TimingPower and Timingaref * values as per Memory AC parameters */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "TimingRow, TimingData, TimingPower and Timingaref\n"); - writel(mem->timing_ref, &dmc->timingref); - writel(mem->timing_row, &dmc->timingrow); - writel(mem->timing_data, &dmc->timingdata); - writel(mem->timing_power, &dmc->timingpower); - - /* Send PALL command */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n"); - dmc_config_prech(mem, dmc); + writel(mem->timing_ref, &drex0->timingref); + writel(mem->timing_ref, &drex1->timingref); + writel(mem->timing_row, &drex0->timingrow); + writel(mem->timing_row, &drex1->timingrow); + writel(mem->timing_data, &drex0->timingdata); + writel(mem->timing_data, &drex1->timingdata); + writel(mem->timing_power, &drex0->timingpower); + writel(mem->timing_power, &drex1->timingpower); /* Send NOP, MRS and ZQINIT commands */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send NOP, MRS, and ZQINIT\n"); - dmc_config_mrs(mem, dmc); + dmc_config_mrs(mem, drex0); + dmc_config_mrs(mem, drex1); if (mem->gate_leveling_enable) { - val = PHY_CON0_RESET_VAL; - val |= P0_CMD_EN; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); + + setbits_le32(&phy0_ctrl->phy_con0, CTRL_ATGATE); + setbits_le32(&phy1_ctrl->phy_con0, CTRL_ATGATE); + + setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN); + setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; @@ -201,38 +207,51 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, writel(val, &phy0_ctrl->phy_con0); writel(val, &phy1_ctrl->phy_con0); - val = (mem->ctrl_start_point << - PHY_CON12_CTRL_START_POINT_SHIFT) | - (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | - (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | - (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | - (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); + val = readl(&phy0_ctrl->phy_con1); + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); + writel(val, &phy0_ctrl->phy_con1); - val = PHY_CON2_RESET_VAL; - val |= INIT_DESKEW_EN; - val |= RDLVL_GATE_EN; - writel(val, &phy0_ctrl->phy_con2); - writel(val, &phy1_ctrl->phy_con2); + val = readl(&phy1_ctrl->phy_con1); + val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); + writel(val, &phy1_ctrl->phy_con1); - val = PHY_CON0_RESET_VAL; - val |= P0_CMD_EN; - val |= BYTE_RDLVL_EN; - val |= CTRL_SHGATE; - writel(val, &phy0_ctrl->phy_con0); - writel(val, &phy1_ctrl->phy_con0); + nLockR = readl(&phy0_ctrl->phy_con13); + nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; + nLockR = readl(&phy0_ctrl->phy_con12); + nLockR &= ~CTRL_DLL_ON; + nLockR |= nLockW_phy0; + writel(nLockR, &phy0_ctrl->phy_con12); - val = PHY_CON1_RESET_VAL; + nLockR = readl(&phy1_ctrl->phy_con13); + nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2; + nLockR = readl(&phy1_ctrl->phy_con12); + nLockR &= ~CTRL_DLL_ON; + nLockR |= nLockW_phy1; + writel(nLockR, &phy1_ctrl->phy_con12); + + writel(0x00030004, &drex0->directcmd); + writel(0x00130004, &drex0->directcmd); + writel(0x00030004, &drex1->directcmd); + writel(0x00130004, &drex1->directcmd); + + setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); + setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); + + setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE); + setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE); + + val = readl(&phy0_ctrl->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); writel(val, &phy0_ctrl->phy_con1); + + val = readl(&phy1_ctrl->phy_con1); + val &= ~(CTRL_GATEDURADJ_MASK); writel(val, &phy1_ctrl->phy_con1); - writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); - i = RDLVL_COMPLETE_TIMEOUT; - while ((readl(&dmc->phystatus) & - (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != - (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { + writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config); + i = TIMEOUT; + while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { /* * TODO(waihong): Comment on how long this take to * timeout @@ -240,38 +259,116 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, udelay(1); i--; } - if (!i){ - printk(BIOS_SPEW, "Timeout on RDLVL. No DRAM.\n"); + if (!i) return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config); + + writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config); + i = TIMEOUT; + while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + udelay(1); + i--; } - writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config); + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config); writel(0, &phy0_ctrl->phy_con14); writel(0, &phy1_ctrl->phy_con14); - val = (mem->ctrl_start_point << - PHY_CON12_CTRL_START_POINT_SHIFT) | - (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | - (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | - (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | - (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | - (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &phy0_ctrl->phy_con12); - writel(val, &phy1_ctrl->phy_con12); - - update_reset_dll(dmc, DDR_MODE_DDR3); + writel(0x00030000, &drex0->directcmd); + writel(0x00130000, &drex0->directcmd); + writel(0x00030000, &drex1->directcmd); + writel(0x00130000, &drex1->directcmd); + + /* Set Read DQ Calibration */ + writel(0x00030004, &drex0->directcmd); + writel(0x00130004, &drex0->directcmd); + writel(0x00030004, &drex1->directcmd); + writel(0x00130004, &drex1->directcmd); + + val = readl(&phy0_ctrl->phy_con1); + val |= READ_LEVELLING_DDR3; + writel(val, &phy0_ctrl->phy_con1); + val = readl(&phy1_ctrl->phy_con1); + val |= READ_LEVELLING_DDR3; + writel(val, &phy1_ctrl->phy_con1); + + val = readl(&phy0_ctrl->phy_con2); + val |= (RDLVL_EN | RDLVL_INCR_ADJ); + writel(val, &phy0_ctrl->phy_con2); + val = readl(&phy1_ctrl->phy_con2); + val |= (RDLVL_EN | RDLVL_INCR_ADJ); + writel(val, &phy1_ctrl->phy_con2); + + setbits_le32(&drex0->rdlvl_config, CTRL_RDLVL_DATA_ENABLE); + i = TIMEOUT; + while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + udelay(1); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + clrbits_le32(&drex0->rdlvl_config, CTRL_RDLVL_DATA_ENABLE); + + setbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE); + i = TIMEOUT; + while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != + RDLVL_COMPLETE_CHO) && (i > 0)) { + /* + * TODO(waihong): Comment on how long this take to + * timeout + */ + udelay(1); + i--; + } + if (!i) + return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; + clrbits_le32(&drex1->rdlvl_config, CTRL_RDLVL_DATA_ENABLE); + + writel(0x00030000, &drex0->directcmd); + writel(0x00130000, &drex0->directcmd); + writel(0x00030000, &drex1->directcmd); + writel(0x00130000, &drex1->directcmd); + + update_reset_dll(drex0, DDR_MODE_DDR3); + update_reset_dll(drex1, DDR_MODE_DDR3); + + /* Common Settings for Leveling */ + val = PHY_CON12_RESET_VAL; + writel((val + nLockW_phy0), &phy0_ctrl->phy_con12); + writel((val + nLockW_phy1), &phy1_ctrl->phy_con12); + + setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN); + setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); + + update_reset_dll(drex0, DDR_MODE_DDR3); + update_reset_dll(drex1, DDR_MODE_DDR3); } /* Send PALL command */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Send PALL Command\n"); - dmc_config_prech(mem, dmc); + dmc_config_prech(mem, drex0); + dmc_config_prech(mem, drex1); - writel(mem->memcontrol, &dmc->memcontrol); + writel(mem->memcontrol, &drex0->memcontrol); + writel(mem->memcontrol, &drex1->memcontrol); /* Set DMC Concontrol and enable auto-refresh counter */ - printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Set DMC Concontrol and enable auto-refresh counter\n"); - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); + writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex0->concontrol); + writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) | + (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), + &drex1->concontrol); return 0; } diff --git a/src/cpu/samsung/exynos5420/power.c b/src/cpu/samsung/exynos5420/power.c index 82791b6..18e0299 100644 --- a/src/cpu/samsung/exynos5420/power.c +++ b/src/cpu/samsung/exynos5420/power.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <arch/hlt.h> #include "cpu.h" +#include "dmc.h" #include "power.h" #include "setup.h" #include "sysreg.h" diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 34056f3..7d486f0 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -1,4 +1,4 @@ -/* + /* * This file is part of the coreboot project. * * Copyright (C) 2012 Samsung Electronics @@ -27,6 +27,11 @@ enum ddr_mode; struct exynos5_phy_control; #define NOT_AVAILABLE 0 +#define DATA_MASK 0xFFFFF + +#define ENABLE_BIT 0x1 +#define DISABLE_BIT 0x0 +#define CA_SWAP_EN (1 << 0) /* TZPC : Register Offsets */ #define TZPC0_BASE 0x10100000 @@ -122,6 +127,7 @@ struct exynos5_phy_control; /* MEMCONFIG0 register bit fields */ #define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) #define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) #define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) #define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) @@ -201,6 +207,10 @@ struct exynos5_phy_control; /* CLK_SRC_CDREX */ #define CLK_SRC_CDREX_VAL 0x00000001 +#define MUX_MCLK_CDR_MSPLL (1 << 4) +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) +#define BPLL_SEL_MASK 0x7 +#define FOUTBPLL 2 /* CLK_DIV_CDREX */ #define CLK_DIV_CDREX0_VAL 0x30010100 @@ -620,39 +630,177 @@ struct exynos5_phy_control; #define CTRL_SHGATE (1 << 8) #define PHY_CON1_RESET_VAL 0x09210100 +#define RDLVL_PASS_ADJ_VAL 0x6 +#define RDLVL_PASS_ADJ_OFFSET 16 #define CTRL_GATEDURADJ_MASK (0xf << 20) +#define READ_LEVELLING_DDR3 0x0100 #define PHY_CON2_RESET_VAL 0x00010004 #define INIT_DESKEW_EN (1 << 6) +#define DLL_DESKEW_EN (1 << 12) #define RDLVL_GATE_EN (1 << 24) +#define RDLVL_EN (1 << 25) +#define RDLVL_INCR_ADJ (0x1 << 16) + +/* DREX_PAUSE */ +#define DREX_PAUSE_EN (1 << 0) + +#define BYPASS_EN (1 << 22) + +/********-----MEMMORY VAL----------***/ +#define PHY_CON0_VAL 0x17021A00 + +#define PHY_CON12_RESET_VAL 0x10100070 +#define PHY_CON12_VAL 0x10107F50 +#define CTRL_START (1 << 6) +#define CTRL_DLL_ON (1 << 5) +#define CTRL_FORCE_MASK (0x7F << 8) +#define CTRL_LOCK_COARSE_MASK (0x7F << 10) + + +#define CTRL_OFFSETD_RESET_VAL 0x8 +#define CTRL_OFFSETD_VAL 0x7F + +#define CTRL_OFFSETR0 0x7F +#define CTRL_OFFSETR1 0x7F +#define CTRL_OFFSETR2 0x7F +#define CTRL_OFFSETR3 0x7F +#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \ + CTRL_OFFSETR1 << 8 | \ + CTRL_OFFSETR2 << 16 | \ + CTRL_OFFSETR3 << 24) +#define PHY_CON4_RESET_VAL 0x08080808 + +#define CTRL_OFFSETW0 0x7F +#define CTRL_OFFSETW1 0x7F +#define CTRL_OFFSETW2 0x7F +#define CTRL_OFFSETW3 0x7F +#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \ + CTRL_OFFSETW1 << 8 | \ + CTRL_OFFSETW2 << 16 | \ + CTRL_OFFSETW3 << 24) +#define PHY_CON6_RESET_VAL 0x08080808 + +#define PHY_CON14_RESET_VAL 0x001F0000 +#define CTRL_PULLD_DQS 0xF +#define CTRL_PULLD_DQS_OFFSET 0 /*ZQ Configurations */ #define PHY_CON16_RESET_VAL 0x08000304 +#define ZQ_CLK_EN (1 << 27) #define ZQ_CLK_DIV_EN (1 << 18) +#define ZQ_MANUAL_MODE_OFFSET 2 +#define ZQ_LONG_CALIBRATION 0x1 #define ZQ_MANUAL_STR (1 << 1) #define ZQ_DONE (1 << 0) +#define ZQ_MODE_DDS_OFFSET 24 + +#define LONG_CALIBRATION (ZQ_LONG_CALIBRATION << ZQ_MANUAL_MODE_OFFSET) #define CTRL_RDLVL_GATE_ENABLE 1 -#define CTRL_RDLVL_GATE_DISABLE 1 +#define CTRL_RDLVL_GATE_DISABLE 0 +#define CTRL_RDLVL_DATA_ENABLE (1 << 1) /* Direct Command */ #define DIRECT_CMD_NOP 0x07000000 #define DIRECT_CMD_PALL 0x01000000 #define DIRECT_CMD_ZQINIT 0x0a000000 #define DIRECT_CMD_CHANNEL_SHIFT 28 #define DIRECT_CMD_CHIP_SHIFT 20 +#define DIRECT_CMD_REFA (5 << 24) +#define DIRECT_CMD_MRS1 0x71C00 +#define DIRECT_CMD_MRS2 0x10BFC +#define DIRECT_CMD_MRS3 0x0050C +#define DIRECT_CMD_MRS4 0x00868 +#define DIRECT_CMD_MRS5 0x00C04 + +/* Drive Strength */ +#define IMPEDANCE_48_OHM 4 +#define IMPEDANCE_40_OHM 5 +#define IMPEDANCE_34_OHM 6 +#define IMPEDANCE_30_OHM 7 +#define PHY_CON39_VAL_48_OHM 0x09240924 +#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D +#define PHY_CON39_VAL_34_OHM 0x0DB60DB6 +#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF + + +#define CTRL_BSTLEN_OFFSET 8 +#define CTRL_RDLAT_OFFSET 0 + +#define CMD_DEFAULT_LPDDR3 0xF +#define CMD_DEFUALT_OFFSET 0 +#define T_WRDATA_EN 0x7 +#define T_WRDATA_EN_DDR3 0x8 +#define T_WRDATA_EN_OFFSET 16 +#define T_WRDATA_EN_MASK 0x1f + +#define PHY_CON31_VAL 0x0C183060 +#define PHY_CON32_VAL 0x60C18306 +#define PHY_CON33_VAL 0x00000030 + +#define PHY_CON31_RESET_VAL 0x0 +#define PHY_CON32_RESET_VAL 0x0 +#define PHY_CON33_RESET_VAL 0x0 + +#define SL_DLL_DYN_CON_EN (1 << 1) +#define FP_RESYNC (1 << 3) +#define CTRL_START (1 << 6) + +#define DMC_AREF_EN (1 << 5) +#define DMC_CONCONTROL_EMPTY (1 << 8) +#define DFI_INIT_START (1 << 28) + +#define DMC_MEMCONTROL_VAL 0x00312700 +#define CLK_STOP_EN (1 << 0) +#define DPWRDN_EN (1 << 1) +#define DSREF_EN (1 << 5) + +/* As we use channel interleaving, therefore value of the base address + * register must be set as half of the bus base address + * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so + * we need to set half 0x10 to the membaseconfigx registers + * see exynos5420 UM section 17.17.3.21 for more + */ +#define DMC_CHIP_BASE_0 0x10 +#define DMC_CHIP_BASE_1 0x50 +#define DMC_CHIP_MASK 0x7C0 + +#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0 +#define MEMBASECONFIG_CHIP_MASK_OFFSET 0 +#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20 +#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40 +#define CHIP_BASE_OFFSET 16 + +#define MEMCONFIG_VAL 0x1323 +#define PRECHCONFIG_DEFAULT_VAL 0xFF000000 +#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF + +#define TIMINGAREF_VAL 0x5d +#define TIMINGROW_VAL 0x345A8692 +#define TIMINGDATA_VAL 0x3630065C +#define TIMINGPOWER_VAL 0x50380336 +#define DFI_INIT_COMPLETE (1 << 3) + +#define BRBRSVCONTROL_VAL 0x00000033 +#define BRBRSVCONFIG_VAL 0x88778877 /* DMC PHY Control0 register */ #define PHY_CONTROL0_RESET_VAL 0x0 #define MEM_TERM_EN (1 << 31) /* Termination enable for memory */ #define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */ #define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */ +#define CTRL_ATGATE (1 << 6) #define FP_RSYNC (1 << 3) /* Force DLL resyncronization */ /* Driver strength for CK, CKE, CS & CA */ #define IMP_OUTPUT_DRV_40_OHM 0x5 #define IMP_OUTPUT_DRV_30_OHM 0x7 +#define DA_3_DS_OFFSET 25 +#define DA_2_DS_OFFSET 22 +#define DA_1_DS_OFFSET 19 +#define DA_0_DS_OFFSET 16 #define CA_CK_DRVR_DS_OFFSET 9 #define CA_CKE_DRVR_DS_OFFSET 6 #define CA_CS_DRVR_DS_OFFSET 3 @@ -687,8 +835,10 @@ void mem_ctrl_init(void); * @param mem_reset Reset memory during initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int mem_reset); +int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset); + +/* Memory variant specific initialization code for LPDDR3 */ +int lpddr3_mem_ctrl_init(int reset); /* * Configure ZQ I/O interface diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index 8aed0a0..0dc013b 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_TI_TPS65090 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select HAVE_INIT_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c index 68c2bd6..74f3e6e 100644 --- a/src/mainboard/google/pit/memory.c +++ b/src/mainboard/google/pit/memory.c @@ -23,147 +23,21 @@ #include <console/console.h> #include <cpu/samsung/exynos5420/gpio.h> -#include <cpu/samsung/exynos5420/setup.h> #include <cpu/samsung/exynos5420/dmc.h> +#include <cpu/samsung/exynos5420/setup.h> #include <cpu/samsung/exynos5420/clk.h> -const struct mem_timings mem_timings[] = { - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { +const struct mem_timings mem_timings = { .mem_manuf = MEM_MANUF_SAMSUNG, .mem_type = DDR_MODE_DDR3, .frequency_mhz = 800, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x64, - .bpll_pdiv = 0x3, - .bpll_sdiv = 0x0, - .use_bpll = 0, - .pclk_cdrex_ratio = 0x5, .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 + 0x00020018, 0x00030000, 0x00010002, 0x00000d70 }, .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, + .timing_row = 0x6836650f, .timing_data = 0x3630580b, - .timing_power = 0x41000a44, + .timing_power = 0x41000a26, .phy0_dqs = 0x08080808, .phy1_dqs = 0x08080808, .phy0_dq = 0x08080808, @@ -191,7 +65,7 @@ const struct mem_timings mem_timings[] = { .rd_fetch = 0x3, - .zq_mode_dds = 0x5, + .zq_mode_dds = 0x6, .zq_mode_term = 0x1, .zq_mode_noterm = 1, @@ -207,20 +81,18 @@ const struct mem_timings mem_timings[] = { DMC_MEMCONTROL_DPWRDN_DISABLE | DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | + DMC_MEMCONTROL_DSREF_DISABLE | DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | DMC_MEMCONTROL_MEM_TYPE_DDR3 | DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | + DMC_MEMCONTROL_NUM_CHIP_2 | DMC_MEMCONTROL_BL_8 | DMC_MEMCONTROL_PZQ_DISABLE | DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | + .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT | DMC_MEMCONFIGx_CHIP_COL_10 | DMC_MEMCONFIGx_CHIP_ROW_15 | DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), .prechconfig_tp_cnt = 0xff, .dpwrdn_cyc = 0xff, .dsref_cyc = 0xffff, @@ -230,316 +102,9 @@ const struct mem_timings mem_timings[] = { DMC_CONCONTROL_EMPTY_DISABLE | DMC_CONCONTROL_AREF_EN_DISABLE | DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, + .dmc_channels = 1, .chips_per_channel = 2, - .chips_to_configure = 1, + .chips_to_configure = 2, .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, .gate_leveling_enable = 1, - }, - { - .mem_manuf = MEM_MANUF_ELPIDA, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010042, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x4, - .phy1_tFS = 0x4, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x7, - .zq_mode_term = 0x1, - .zq_mode_noterm = 0, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_30_OHM, - .gate_leveling_enable = 0, - }, { - .mem_manuf = MEM_MANUF_SAMSUNG, - .mem_type = DDR_MODE_DDR3, - .frequency_mhz = 780, - .mpll_mdiv = 0x64, - .mpll_pdiv = 0x3, - .mpll_sdiv = 0x0, - .cpll_mdiv = 0xde, - .cpll_pdiv = 0x4, - .cpll_sdiv = 0x2, - .gpll_mdiv = 0x215, - .gpll_pdiv = 0xc, - .gpll_sdiv = 0x1, - .epll_mdiv = 0x60, - .epll_pdiv = 0x3, - .epll_sdiv = 0x3, - .vpll_mdiv = 0x96, - .vpll_pdiv = 0x3, - .vpll_sdiv = 0x2, - - .bpll_mdiv = 0x82, - .bpll_pdiv = 0x4, - .bpll_sdiv = 0x0, - .use_bpll = 1, - .pclk_cdrex_ratio = 0x5, - .direct_cmd_msr = { - 0x00020018, 0x00030000, 0x00010000, 0x00000d70 - }, - .timing_ref = 0x000000bb, - .timing_row = 0x8c36660f, - .timing_data = 0x3630580b, - .timing_power = 0x41000a44, - .phy0_dqs = 0x08080808, - .phy1_dqs = 0x08080808, - .phy0_dq = 0x08080808, - .phy1_dq = 0x08080808, - .phy0_tFS = 0x8, - .phy1_tFS = 0x8, - .phy0_pulld_dqs = 0xf, - .phy1_pulld_dqs = 0xf, - - .lpddr3_ctrl_phy_reset = 0x1, - .ctrl_start_point = 0x10, - .ctrl_inc = 0x10, - .ctrl_start = 0x1, - .ctrl_dll_on = 0x1, - .ctrl_ref = 0x8, - - .ctrl_force = 0x1a, - .ctrl_rdlat = 0x0b, - .ctrl_bstlen = 0x08, - - .fp_resync = 0x8, - .iv_size = 0x7, - .dfi_init_start = 1, - .aref_en = 1, - - .rd_fetch = 0x3, - - .zq_mode_dds = 0x5, - .zq_mode_term = 0x1, - .zq_mode_noterm = 1, - - /* - * Dynamic Clock: Always Running - * Memory Burst length: 8 - * Number of chips: 1 - * Memory Bus width: 32 bit - * Memory Type: DDR3 - * Additional Latancy for PLL: 0 Cycle - */ - .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE | - DMC_MEMCONTROL_DPWRDN_DISABLE | - DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE | - DMC_MEMCONTROL_TP_DISABLE | - DMC_MEMCONTROL_DSREF_ENABLE | - DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | - DMC_MEMCONTROL_MEM_TYPE_DDR3 | - DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_1 | - DMC_MEMCONTROL_BL_8 | - DMC_MEMCONTROL_PZQ_DISABLE | - DMC_MEMCONTROL_MRR_BYTE_7_0, - .memconfig = DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED | - DMC_MEMCONFIGx_CHIP_COL_10 | - DMC_MEMCONFIGx_CHIP_ROW_15 | - DMC_MEMCONFIGx_CHIP_BANK_8, - .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40), - .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80), - .prechconfig_tp_cnt = 0xff, - .dpwrdn_cyc = 0xff, - .dsref_cyc = 0xffff, - .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE | - DMC_CONCONTROL_TIMEOUT_LEVEL0 | - DMC_CONCONTROL_RD_FETCH_DISABLE | - DMC_CONCONTROL_EMPTY_DISABLE | - DMC_CONCONTROL_AREF_EN_DISABLE | - DMC_CONCONTROL_IO_PD_CON_DISABLE, - .dmc_channels = 2, - .chips_per_channel = 2, - .chips_to_configure = 1, - .send_zq_init = 1, - .impedance = IMP_OUTPUT_DRV_40_OHM, - .gate_leveling_enable = 1, - } }; - -#define BOARD_ID0_GPIO 88 /* GPD0, pin 0 */ -#define BOARD_ID1_GPIO 89 /* GPD0, pin 1 */ - -enum board_config { - PIT_CONFIG_UNKNOWN = -1, - PIT_CONFIG_SAMSUNG_EVT, - PIT_CONFIG_ELPIDA_EVT, - PIT_CONFIG_SAMSUNG_DVT, - PIT_CONFIG_ELPIDA_DVT, - PIT_CONFIG_SAMSUNG_PVT, - PIT_CONFIG_ELPIDA_PVT, - PIT_CONFIG_SAMSUNG_MP, - PIT_CONFIG_ELPIDA_MP, - PIT_CONFIG_RSVD, -}; - -struct { - enum mvl3 id0, id1; - enum board_config config; -} id_map[] = { - /* ID0 ID1 config */ - { LOGIC_0, LOGIC_0, PIT_CONFIG_SAMSUNG_MP }, - { LOGIC_0, LOGIC_1, PIT_CONFIG_ELPIDA_MP }, - { LOGIC_1, LOGIC_0, PIT_CONFIG_SAMSUNG_DVT }, - { LOGIC_1, LOGIC_1, PIT_CONFIG_ELPIDA_DVT }, - { LOGIC_0, LOGIC_Z, PIT_CONFIG_SAMSUNG_PVT }, - { LOGIC_1, LOGIC_Z, PIT_CONFIG_ELPIDA_PVT }, - { LOGIC_Z, LOGIC_0, PIT_CONFIG_SAMSUNG_MP }, - { LOGIC_Z, LOGIC_Z, PIT_CONFIG_ELPIDA_MP }, - { LOGIC_Z, LOGIC_1, PIT_CONFIG_RSVD }, -}; - -static int board_get_config(void) -{ - int i; - int id0, id1; - enum board_config config = PIT_CONFIG_UNKNOWN; - - id0 = gpio_read_mvl3(BOARD_ID0_GPIO); - id1 = gpio_read_mvl3(BOARD_ID1_GPIO); - if (id0 < 0 || id1 < 0) - return -1; - - for (i = 0; i < ARRAY_SIZE(id_map); i++) { - if (id0 == id_map[i].id0 && id1 == id_map[i].id1) { - config = id_map[i].config; - break; - } - } - - return config; -} - -struct mem_timings *get_mem_timings(void) -{ - int i; - enum board_config config; - enum ddr_mode mem_type; - unsigned int frequency_mhz; - enum mem_manuf mem_manuf; - const struct mem_timings *mem; - - config = board_get_config(); - switch (config) { - case PIT_CONFIG_ELPIDA_EVT: - case PIT_CONFIG_ELPIDA_DVT: - case PIT_CONFIG_ELPIDA_PVT: - case PIT_CONFIG_ELPIDA_MP: - mem_manuf = MEM_MANUF_ELPIDA; - mem_type = DDR_MODE_DDR3; - frequency_mhz = 800; - break; - case PIT_CONFIG_SAMSUNG_EVT: - case PIT_CONFIG_SAMSUNG_DVT: - case PIT_CONFIG_SAMSUNG_PVT: - case PIT_CONFIG_SAMSUNG_MP: - mem_manuf = MEM_MANUF_SAMSUNG; - mem_type = DDR_MODE_DDR3; - frequency_mhz = 800; - break; - default: - printk(BIOS_CRIT, "Unknown board configuration.\n"); - return NULL; - } - - for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings); - i++, mem++) { - if (mem->mem_type == mem_type && - mem->frequency_mhz == frequency_mhz && - mem->mem_manuf == mem_manuf) - return (struct mem_timings *)mem; - } - - return NULL; -} diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 8a5a1dd..1ff8d51 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -130,7 +130,7 @@ static void setup_gpio(void) static void setup_memory(struct mem_timings *mem, int is_resume) { - printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", + printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", mem->mem_manuf, mem->mem_type, mem->mpll_mdiv, @@ -148,27 +148,97 @@ static void setup_memory(struct mem_timings *mem, int is_resume) } } -static struct mem_timings *setup_clock(void) +#define PRIMITIVE_MEM_TEST 0 +#if PRIMITIVE_MEM_TEST +static unsigned long primitive_mem_test(void) { - struct mem_timings *mem = get_mem_timings(); - if (!mem) { - die("Unable to auto-detect memory timings\n"); + unsigned long *l = (void *)0x40000000; + int bad = 0; + unsigned long i; + for(i = 0; i < 256*1048576; i++){ + if (! (i%1048576)) + printk(BIOS_SPEW, "%lu ...", i); + l[i] = 0xffffffff - i; } - system_clock_init(); + for(i = 0; i < 256*1048576; i++){ + if (! (i%1048576)) + printk(BIOS_SPEW, "%lu ...", i); + if (l[i] != (0xffffffff - i)){ + printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i); + bad++; + } + } + + printk(BIOS_SPEW, "%d errors\n", bad); - return mem; + return bad; } +#else +#define primitive_mem_test() +#endif + +#define SIMPLE_SPI_TEST 0 +#if SIMPLE_SPI_TEST +/* here is a simple SPI debug test, known to fid trouble */ +static void simple_spi_test(void) +{ + struct cbfs_media default_media, *media; + int i, amt = 4 * MiB, errors = 0; + //u32 *data = (void *)0x40000000; + u32 data[1024]; + u32 in; + + amt = sizeof(data); + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + printk(BIOS_SPEW, "Failed to initialize default media.\n"); + return; + } + + + media->open(media); + if (media->read(media, data, (size_t) 0, amt) < amt){ + printk(BIOS_SPEW, "simple_spi_test fails\n"); + return; + } + + + for(i = 0; i < amt; i += 4){ + if (media->read(media, &in, (size_t) i, 4) < 1){ + printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); + return; + } + if (data[i/4] != in){ + errors++; + printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", + i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); + /* reread it to see which is wrong. */ + if (media->read(media, &in, (size_t) i, 4) < 1){ + printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); + return; + } + printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", + i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); + } + + } + printk(BIOS_SPEW, "%d errors\n", errors); +} +#else +#define simple_spi_test() +#endif void main(void) { - struct mem_timings *mem; + + extern struct mem_timings mem_timings; void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ - mem = setup_clock(); + system_clock_init(); console_init(); @@ -176,7 +246,9 @@ void main(void) setup_power(); } - setup_memory(mem, is_resume); + setup_memory(&mem_timings, is_resume); + + primitive_mem_test(); if (is_resume) { wakeup(); @@ -186,9 +258,12 @@ void main(void) setup_gpio(); setup_graphics(); + simple_spi_test(); /* Set SPI (primary CBFS media) clock to 50MHz. */ + /* if this is uncommented SPI will not work correctly. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); - + simple_spi_test(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + simple_spi_test(); stage_exit(entry); } [View Less]

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Patch set updated for coreboot: 469f54e exynos5420: Implement support for the pinmux as functions.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3674 -gerrit commit 469f54e48c54c70d28a564df7c620de2b775fe03 Author: Gabe Black <gabeblack(a)google.com> Date: Sat Jun 15 23:40:26 2013 -0700 exynos5420: Implement support for the pinmux as functions. Change-Id: I5e0ec360597cd95cb6510fb32b04d8931e6a33db Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/… [View More]exynos5420/clock.c | 1 + src/cpu/samsung/exynos5420/i2c.c | 1 - src/cpu/samsung/exynos5420/pinmux.c | 434 ++++++++++++++--------------------- src/cpu/samsung/exynos5420/pinmux.h | 60 +++-- src/cpu/samsung/exynos5420/uart.c | 3 +- src/mainboard/google/pit/mainboard.c | 2 +- src/mainboard/google/pit/romstage.c | 7 +- 7 files changed, 206 insertions(+), 302 deletions(-) diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 6e4701a..1df4aba 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -24,6 +24,7 @@ #include "timer.h" #include "clk.h" #include "cpu.h" +#include "periph.h" /* input clock of PLL: SMDK5420 has 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index 98eb641..43cc4d2 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -157,7 +157,6 @@ static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) */ static void i2c_bus_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) { - exynos_pinmux_config(bus->periph_id, 0); i2c_ch_init(bus, speed, slaveadd); } diff --git a/src/cpu/samsung/exynos5420/pinmux.c b/src/cpu/samsung/exynos5420/pinmux.c index 6991dfc..566ba60 100644 --- a/src/cpu/samsung/exynos5420/pinmux.c +++ b/src/cpu/samsung/exynos5420/pinmux.c @@ -23,276 +23,180 @@ #include "cpu.h" #include "pinmux.h" -int exynos_pinmux_config(enum periph_id peripheral, int flags) +static void exynos_pinmux_uart(int start, int count) { - int i, start, count, start_ext, pin_ext, pin, drv; - - switch (peripheral) { - case PERIPH_ID_UART0: - case PERIPH_ID_UART1: - case PERIPH_ID_UART2: - case PERIPH_ID_UART3: - switch (peripheral) { - default: - case PERIPH_ID_UART0: - start = GPIO_A00; count = 4; - break; - case PERIPH_ID_UART1: - start = GPIO_A04; count = 4; - break; - case PERIPH_ID_UART2: - start = GPIO_A10; count = 4; - break; - case PERIPH_ID_UART3: - start = GPIO_A14; count = 2; - break; - } - for (i = start; i < start + count; i++) { - gpio_set_pull(i, GPIO_PULL_NONE); + int i; + + for (i = start; i < start + count; i++) { + gpio_set_pull(i, GPIO_PULL_NONE); + gpio_cfg_pin(i, GPIO_FUNC(0x2)); + } +} + +void exynos_pinmux_uart0(void) +{ + exynos_pinmux_uart(GPIO_A00, 4); +} + +void exynos_pinmux_uart1(void) +{ + exynos_pinmux_uart(GPIO_A04, 4); +} + +void exynos_pinmux_uart2(void) +{ + exynos_pinmux_uart(GPIO_A10, 4); +} + +void exynos_pinmux_uart3(void) +{ + exynos_pinmux_uart(GPIO_A14, 2); +} + +static void exynos_pinmux_sdmmc(int start, int start_ext) +{ + int i; + + if (start_ext) { + for (i = start_ext; i <= (start_ext + 3); i++) { gpio_cfg_pin(i, GPIO_FUNC(0x2)); + gpio_set_pull(i, GPIO_PULL_UP); + gpio_set_drv(i, GPIO_DRV_4X); } - break; - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC2: - case PERIPH_ID_SDMMC3: - pin = GPIO_FUNC(0x2); - pin_ext = GPIO_FUNC(0x2); - drv = GPIO_DRV_4X; - switch (peripheral) { - default: - case PERIPH_ID_SDMMC0: - start = GPIO_C00; - start_ext = GPIO_C10; - break; - case PERIPH_ID_SDMMC1: - start = GPIO_C20; - start_ext = 0; - break; - case PERIPH_ID_SDMMC2: - start = GPIO_C30; - /* - * TODO: (alim.akhtar(a)samsung.com) - * add support for 8 bit mode (needs to be a per-board - * option, so in the FDT). - */ - start_ext = 0; - break; - case PERIPH_ID_SDMMC3: - /* - * TODO: Need to add defintions for GPC4 before - * enabling this. - */ - printk(BIOS_DEBUG, "SDMMC3 not supported yet"); - return -1; - } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - printk(BIOS_DEBUG, "SDMMC device %d does not support 8bit mode", - peripheral); - return -1; - } - if (flags & PINMUX_FLAG_8BIT_MODE) { - ASSERT(peripheral == PERIPH_ID_SDMMC0); - for (i = 0; i <= 3; i++) { - gpio_cfg_pin(start_ext + i, pin_ext); - gpio_set_pull(start_ext + i, - GPIO_PULL_UP); - gpio_set_drv(start_ext + i, drv); - } - } - for (i = 0; i < 2; i++) { - gpio_cfg_pin(start + i, pin); - gpio_set_pull(start + i, GPIO_PULL_NONE); - gpio_set_drv(start + i, drv); - } - for (i = 2; i <= 6; i++) { - gpio_cfg_pin(start + i, pin); - gpio_set_pull(start + i, GPIO_PULL_UP); - gpio_set_drv(start + i, drv); - } - break; - case PERIPH_ID_SROMC: - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2)); - - for (i = 2; i < 4; i++) - gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP); - - gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP); - - if (flags & PINMUX_FLAG_16BIT) { - gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y60 + i, - GPIO_PULL_UP); - } - } - break; - case PERIPH_ID_SPI0: - case PERIPH_ID_SPI1: - case PERIPH_ID_SPI2: - case PERIPH_ID_SPI3: { - int cfg; - - switch (peripheral) { - default: - case PERIPH_ID_SPI0: - start = GPIO_A20; - cfg = 0x2; - break; - case PERIPH_ID_SPI1: - start = GPIO_A24; - cfg = 0x2; - break; - case PERIPH_ID_SPI2: - start = GPIO_B11; - cfg = 0x5; - break; - case PERIPH_ID_SPI3: - start = GPIO_E00; - cfg = 0x2; - break; - } + } - for (i = 0; i < 4; i++) - gpio_cfg_pin(start + i, GPIO_FUNC(cfg)); - break; + for (i = 0; i < 3; i++) { + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); + gpio_set_pull(start + i, GPIO_PULL_NONE); + gpio_set_drv(start + i, GPIO_DRV_4X); } - case PERIPH_ID_SPI4: - for (i = 0; i < 2; i++) - gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); - for (i = 2; i < 4; i++) - gpio_cfg_pin(GPIO_E02 + i, GPIO_FUNC(0x4)); - break; - case PERIPH_ID_BACKLIGHT: - gpio_cfg_pin(GPIO_B20, GPIO_OUTPUT); - gpio_set_value(GPIO_B20, 1); - break; - case PERIPH_ID_LCD: - gpio_cfg_pin(GPIO_Y25, GPIO_OUTPUT); - gpio_set_value(GPIO_Y25, 1); - gpio_cfg_pin(GPIO_X15, GPIO_OUTPUT); - gpio_set_value(GPIO_X15, 1); - gpio_cfg_pin(GPIO_X30, GPIO_OUTPUT); - gpio_set_value(GPIO_X30, 1); - break; - case PERIPH_ID_I2C0: - gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2)); - gpio_set_pull(GPIO_B30, GPIO_PULL_NONE); - gpio_set_pull(GPIO_B31, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2C1: - gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2)); - gpio_set_pull(GPIO_B32, GPIO_PULL_NONE); - gpio_set_pull(GPIO_B33, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2C2: - gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3)); - gpio_set_pull(GPIO_A06, GPIO_PULL_NONE); - gpio_set_pull(GPIO_A07, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2C3: - gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3)); - gpio_set_pull(GPIO_A12, GPIO_PULL_NONE); - gpio_set_pull(GPIO_A13, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2C4: - gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3)); - gpio_set_pull(GPIO_A20, GPIO_PULL_NONE); - gpio_set_pull(GPIO_A21, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2C5: - gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3)); - gpio_set_pull(GPIO_A22, GPIO_PULL_NONE); - gpio_set_pull(GPIO_A23, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2C6: - gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4)); - break; - case PERIPH_ID_I2C7: - gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3)); - gpio_set_pull(GPIO_B22, GPIO_PULL_NONE); - gpio_set_pull(GPIO_B23, GPIO_PULL_NONE); - break; - case PERIPH_ID_DPHPD: - /* Set Hotplug detect for DP */ - gpio_cfg_pin(GPIO_X07, GPIO_FUNC(0x3)); - - /* - * Hotplug detect should have an external pullup; disable the - * internal pulldown so they don't fight. - */ - gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); - break; - case PERIPH_ID_I2S1: - for (i = 0; i < 5; i++) - gpio_cfg_pin(GPIO_B00 + i, GPIO_FUNC(0x02)); - break; - default: - printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral); - return -1; + + for (i = 3; i <= 6; i++) { + gpio_cfg_pin(start + i, GPIO_FUNC(0x2)); + gpio_set_pull(start + i, GPIO_PULL_UP); + gpio_set_drv(start + i, GPIO_DRV_4X); + } +} + +void exynos_pinmux_sdmmc0(void) +{ + gpio_set_pull(GPIO_C02, GPIO_PULL_UP); + exynos_pinmux_sdmmc(GPIO_C00, GPIO_C30); +} + +void exynos_pinmux_sdmmc1(void) +{ + exynos_pinmux_sdmmc(GPIO_C10, GPIO_D14); +} + +void exynos_pinmux_sdmmc2(void) +{ + exynos_pinmux_sdmmc(GPIO_C20, 0); +} + +static void exynos_pinmux_spi(int start, int cfg) +{ + int i; + + for (i = start; i < start + 4; i++) + gpio_cfg_pin(i, cfg); +} + +void exynos_pinmux_spi0(void) +{ + exynos_pinmux_spi(GPIO_A20, 0x2); +} + +void exynos_pinmux_spi1(void) +{ + exynos_pinmux_spi(GPIO_A24, 0x2); +} + +void exynos_pinmux_spi2(void) +{ + exynos_pinmux_spi(GPIO_B11, 0x5); +} + +void exynos_pinmux_spi3(void) +{ + exynos_pinmux_spi(GPIO_F10, 0x2); +} + +void exynos_pinmux_spi4(void) +{ + int i; + + for (i = 0; i < 2; i++) { + gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4)); + gpio_cfg_pin(GPIO_E04 + i, GPIO_FUNC(0x4)); } +} + +static void exynos_pinmux_i2c(int start, int func) +{ + gpio_cfg_pin(start, GPIO_FUNC(func)); + gpio_cfg_pin(start + 1, GPIO_FUNC(func)); + gpio_set_pull(start, GPIO_PULL_NONE); + gpio_set_pull(start + 1, GPIO_PULL_NONE); +} + +void exynos_pinmux_i2c0(void) +{ + exynos_pinmux_i2c(GPIO_B30, 0x2); +} + +void exynos_pinmux_i2c1(void) +{ + exynos_pinmux_i2c(GPIO_B32, 0x2); +} + +void exynos_pinmux_i2c2(void) +{ + exynos_pinmux_i2c(GPIO_A06, 0x3); +} + +void exynos_pinmux_i2c3(void) +{ + exynos_pinmux_i2c(GPIO_A12, 0x3); +} + +void exynos_pinmux_i2c4(void) +{ + exynos_pinmux_i2c(GPIO_A20, 0x3); +} + +void exynos_pinmux_i2c5(void) +{ + exynos_pinmux_i2c(GPIO_A22, 0x3); +} + +void exynos_pinmux_i2c6(void) +{ + exynos_pinmux_i2c(GPIO_B13, 0x4); +} + +void exynos_pinmux_i2c7(void) +{ + exynos_pinmux_i2c(GPIO_B22, 0x3); +} + +void exynos_pinmux_i2c8(void) +{ + exynos_pinmux_i2c(GPIO_B34, 0x2); +} + +void exynos_pinmux_i2c9(void) +{ + exynos_pinmux_i2c(GPIO_B36, 0x2); +} + +void exynos_pinmux_i2c10(void) +{ + exynos_pinmux_i2c(GPIO_B40, 0x2); +} - return 0; +void exynos_pinmux_dphpd(void) +{ + gpio_cfg_pin(GPIO_X07, GPIO_FUNC(0x3)); + gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); } diff --git a/src/cpu/samsung/exynos5420/pinmux.h b/src/cpu/samsung/exynos5420/pinmux.h index c94b6eb..fc09fc9 100644 --- a/src/cpu/samsung/exynos5420/pinmux.h +++ b/src/cpu/samsung/exynos5420/pinmux.h @@ -20,36 +20,34 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_PINMUX_H #define CPU_SAMSUNG_EXYNOS5420_PINMUX_H -#include "periph.h" - -enum { - PINMUX_FLAG_NONE = 0x00000000, - - /* Flags for eMMC */ - PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ - - /* - * Flags for SPI. - */ - PINMUX_FLAG_SLAVE_MODE = 1 << 0, /* Slave mode */ - - /* Flags for SROM controller */ - PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ - PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ -}; - -/** - * Configures the pinmux for a particular peripheral. - * - * Each gpio can be configured in many different ways (4 bits on exynos) - * such as "input", "output", "special function", "external interrupt" - * etc. This function will configure the peripheral pinmux along with - * pull-up/down and drive strength. - * - * @param peripheral peripheral to be configured - * @param flags configure flags - * @return 0 if ok, -1 on error (e.g. unsupported peripheral) - */ -int exynos_pinmux_config(enum periph_id peripheral, int flags); +void exynos_pinmux_uart0(void); +void exynos_pinmux_uart1(void); +void exynos_pinmux_uart2(void); +void exynos_pinmux_uart3(void); + +void exynos_pinmux_sdmmc0(void); +void exynos_pinmux_sdmmc1(void); +void exynos_pinmux_sdmmc2(void); +void exynos_pinmux_sdmmc3(void); + +void exynos_pinmux_spi0(void); +void exynos_pinmux_spi1(void); +void exynos_pinmux_spi2(void); +void exynos_pinmux_spi3(void); +void exynos_pinmux_spi4(void); + +void exynos_pinmux_i2c0(void); +void exynos_pinmux_i2c1(void); +void exynos_pinmux_i2c2(void); +void exynos_pinmux_i2c3(void); +void exynos_pinmux_i2c4(void); +void exynos_pinmux_i2c5(void); +void exynos_pinmux_i2c6(void); +void exynos_pinmux_i2c7(void); +void exynos_pinmux_i2c8(void); +void exynos_pinmux_i2c9(void); +void exynos_pinmux_i2c10(void); + +void exynos_pinmux_dphpd(void); #endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 2dea033..de71b80 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -23,6 +23,7 @@ #include "uart.h" #include "clk.h" #include "cpu.h" +#include "periph.h" #define RX_FIFO_COUNT_MASK 0xff #define RX_FIFO_FULL_MASK (1 << 8) @@ -93,7 +94,7 @@ static void exynos5_init_dev(void) struct s5p_uart *uart = (struct s5p_uart *)base_port; // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + exynos_pinmux_uart3(); /* enable FIFOs */ writel(0x1, &uart->ufcon); diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index dccb095..7743864 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -56,7 +56,7 @@ static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ static void exynos_dp_bridge_setup(void) { - exynos_pinmux_config(PERIPH_ID_DPHPD, 0); + exynos_pinmux_dphpd(); gpio_set_value(dp_pd_l, 1); gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 7cf19c5..8a5a1dd 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -50,6 +50,7 @@ static void setup_power(void) power_init(); /* Initialize I2C bus to configure PMIC. */ + exynos_pinmux_i2c0(); i2c_init(0, I2C_0_SPEED, 0x00); printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); @@ -100,16 +101,16 @@ static void setup_storage(void) } gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE); gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X); - exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); + exynos_pinmux_sdmmc0(); /* MMC2: Removable, 4 bit mode, no GPIO. */ clock_set_mshci(PERIPH_ID_SDMMC2); - exynos_pinmux_config(PERIPH_ID_SDMMC2, 0); + exynos_pinmux_sdmmc2(); } static void setup_graphics(void) { - exynos_pinmux_config(PERIPH_ID_DPHPD, 0); + exynos_pinmux_dphpd(); } static void setup_gpio(void) [View Less]

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Patch set updated for coreboot: c45eb3a armv7a: Enable native memcpy / memset
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3675 -gerrit commit c45eb3a710376f279c87c64eac22e8dfed25df11 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 29 13:12:20 2013 -0700 armv7a: Enable native memcpy / memset The code has been there for quite a while but was never enabled. Change-Id: I4ec3dcbb3c03805ac5c75872614e5d394df667cf Signed-off-by: Stefan Reinauer … [View More]

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Patch set updated for coreboot: 4897391 ARM: Tell the linker memset and memcpy are functions.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3672 -gerrit commit 48973919eb019cf5eaf54861b50d0ee2259a051c Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jun 14 15:53:23 2013 -0700 ARM: Tell the linker memset and memcpy are functions. The memset and memcpy functions are assembled as ARM code, likely because that's the default of the assembler. Without special annotation, the … [View More]assembler and linker don't know that those symbols are functions which need special handling so that ARM/thumb issues are handled properly. This change adds that annotation which gets those functions working in Coreboot which is compiled as thumb. Libpayload and depthcharge are compiled as ARM so they don't *need* the annotation since it just works out in ARM mode, but it's the safe thing to do in case we change that in the future. We should explicitly select ARM vs. thumb when assembling assembly files to be consistent across builds and toolchains. Change-Id: I814b137064cf46ae9e2744ff6c223b695dc1ef01 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- payloads/libpayload/arch/armv7/memcpy.S | 1 + payloads/libpayload/arch/armv7/memset.S | 1 + src/arch/armv7/memcpy.S | 1 + src/arch/armv7/memset.S | 1 + 4 files changed, 4 insertions(+) diff --git a/payloads/libpayload/arch/armv7/memcpy.S b/payloads/libpayload/arch/armv7/memcpy.S index 549320c..e68b28f 100644 --- a/payloads/libpayload/arch/armv7/memcpy.S +++ b/payloads/libpayload/arch/armv7/memcpy.S @@ -57,6 +57,7 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ +.type memcpy, function .globl memcpy memcpy: diff --git a/payloads/libpayload/arch/armv7/memset.S b/payloads/libpayload/arch/armv7/memset.S index 4ff4c3c..aa4f57a 100644 --- a/payloads/libpayload/arch/armv7/memset.S +++ b/payloads/libpayload/arch/armv7/memset.S @@ -27,6 +27,7 @@ * memset again. */ +.type memset, function .globl memset memset: ands r3, r0, #3 @ 1 unaligned? diff --git a/src/arch/armv7/memcpy.S b/src/arch/armv7/memcpy.S index f04113f..921fc2a 100644 --- a/src/arch/armv7/memcpy.S +++ b/src/arch/armv7/memcpy.S @@ -57,6 +57,7 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ +.type memcpy, function .globl memcpy memcpy: diff --git a/src/arch/armv7/memset.S b/src/arch/armv7/memset.S index 3ea2721..a3cc947 100644 --- a/src/arch/armv7/memset.S +++ b/src/arch/armv7/memset.S @@ -27,6 +27,7 @@ * memset again. */ +.type memset, function .globl memset memset: ands r3, r0, #3 @ 1 unaligned? [View Less]

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coreboot-gerrit July 2013