coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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1030 discussions

Patch set updated for coreboot: d73f0ef exynos5250: Clear the framebuffer before making it uncacheable.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3655 -gerrit commit d73f0ef52adc1e8f4094c61d671e8b1ed6d0a47f Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 23:06:47 2013 -0700 exynos5250: Clear the framebuffer before making it uncacheable. If we clear the framebuffer and then flush it back to memory using cache operations, the writes are going to be full cachelines at a time. If we make it uncacheable first, the writes will be serialized writes of whatever sized chunks memset uses, probably 4 bytes or less. Change-Id: I1b81731cfed00ae091ba6357451ab186d16f559e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index d2a6df7..3687ea8 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev) lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ + /* * We need to clean and invalidate the framebuffer region and disable * caching as well. We assume that our dcache <--> memory address @@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); - memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); }

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Patch set updated for coreboot: 1e86b75 exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3654 -gerrit commit 1e86b754ed5871dba57a76f7585975b032dabf38 Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 22:57:34 2013 -0700 exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer. At one time it seemed to be necessary to disable and then re-enable the MMU when setting the framebuffer to be uncache-able due to bugs in the MMU management code. Since those bugs have been fixed, this is no longer necessary. Change-Id: I5f7b9bd14dc9929efe1834ec9a258d388b8c94e9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 3ab57c9..d2a6df7 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -105,15 +105,11 @@ static void exynos_displayport_init(device_t dev) * Note: We may want to do something clever to ensure the framebuffer * region is aligned such that we don't change dcache policy for other * stuff inadvertantly. - * - * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); dcache_clean_invalidate_by_mva(lower, upper - lower); - dcache_mmu_disable(); mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); - dcache_mmu_enable(); mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG,

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Patch set updated for coreboot: 972efcc ARM: Fix up page table/cachability management.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3653 -gerrit commit 972efcc37fb855f08539af3a40e4d0f3a1f90ebf Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 22:45:54 2013 -0700 ARM: Fix up page table/cachability management. When modifying the page tables, use writel to ensure the writes happen, flush the page tables themselves to ensure they're visible to the MMU if it doesn't look at the caches, and invalidate the right TLB entries. The first two changes are probably safer but may not be strictly necessary. The third change is necessary because we were invalidating the TLB using i which was in megabytes but using an instruction that expects an address in bytes. One symptom of this problem was that the framebuffer, which was supposed to be marked uncacheable, was only being partially updated since some of the updates were still in the cache. With this change the graphics show up correctly. Change-Id: I5475df29690371459b0d37a304eebc62f81dd76b Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/lib/mmu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index 594bba5..7d6d46a 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -34,6 +34,7 @@ #include <console/console.h> #include <arch/cache.h> +#include <arch/io.h> #define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */ @@ -44,11 +45,14 @@ void mmu_disable_range(unsigned long start_mb, unsigned long size_mb) unsigned int i; uint32_t *ttb_entry = (uint32_t *)ttb_addr; printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n", - start_mb << 20, ((start_mb + size_mb) << 20) - 1); + start_mb*MiB, start_mb*MiB + size_mb*MiB - 1); + + for (i = start_mb; i < start_mb + size_mb; i++) + writel(0, &ttb_entry[i]); for (i = start_mb; i < start_mb + size_mb; i++) { - ttb_entry[i] = 0; - tlbimvaa(i); + dccmvac((uintptr_t)&ttb_entry[i]); + tlbimvaa(i*MiB); } } @@ -99,9 +103,14 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n", start_mb << 20, ((start_mb + size_mb) << 20) - 1, str); + /* Write out page table entries. */ + for (i = start_mb; i < start_mb + size_mb; i++) + writel((i << 20) | attr, &ttb_entry[i]); + + /* Flush the page table entries, and old translations from the TLB. */ for (i = start_mb; i < start_mb + size_mb; i++) { - ttb_entry[i] = (i << 20) | attr; - tlbimvaa(start_mb); + dccmvac((uintptr_t)&ttb_entry[i]); + tlbimvaa(i*MiB); } }

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Patch set updated for coreboot: b522b1e exynos5250: Simplify the graphics code by eliminating the unused color map.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3652 -gerrit commit b522b1e4ac187a77de51504fdaf3eb1fd4fb76d3 Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 15:58:46 2013 -0700 exynos5250: Simplify the graphics code by eliminating the unused color map. The code that allocated space for the framebuffer was adding space for a vestigial color map which was never used. It was also passing around a structure which was used to calculate a single value which was already known when that structure was put together. Eliminate the extra space, and pass the single value instead of the structure. Change-Id: Ia6a41cefdf8b29fe7d68f9596a156eced6eb5df8 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/cpu.c | 21 +++++---------------- src/cpu/samsung/exynos5250/dp-core.h | 16 ++++------------ src/cpu/samsung/exynos5250/fb.c | 29 ++++++++--------------------- src/mainboard/google/snow/mainboard.c | 2 +- 4 files changed, 18 insertions(+), 50 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index b51a591..3ab57c9 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -68,12 +68,10 @@ static void exynos_displayport_init(device_t dev) /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. */ - vidinfo_t vi; struct exynos5_fimd_panel panel; unsigned long int fb_size; u32 lcdbase; - memset(&vi, 0, sizeof(vi)); memset(&panel, 0, sizeof(panel)); panel.is_dp = 1; /* Display I/F is eDP */ @@ -94,18 +92,10 @@ static void exynos_displayport_init(device_t dev) panel.xres = conf->xres; panel.yres = conf->yres; - vi.vl_col = conf->xres; - vi.vl_row = conf->yres; - vi.vl_bpix = conf->bpp; - /* - * The size is a magic number from hardware. Allocate enough for the - * frame buffer and color map. - */ + /* The size is a magic number from hardware. */ fb_size = conf->xres * conf->yres * (conf->bpp / 8); - lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB); - printk(BIOS_SPEW, "LCD colormap base is %p\n", (void *)(lcdbase)); - mmio_resource(dev, 0, lcdbase/KiB, 64); - vi.cmap = (void *)lcdbase; + lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); + printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); /* * We need to clean and invalidate the framebuffer region and disable @@ -119,18 +109,17 @@ static void exynos_displayport_init(device_t dev) * FIXME: Is disabling/re-enabling the MMU entirely necessary? */ uint32_t lower = ALIGN_DOWN(lcdbase, MiB); - uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB); + uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); dcache_clean_invalidate_by_mva(lower, upper - lower); dcache_mmu_disable(); mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); dcache_mmu_enable(); - lcdbase += 64*KiB; mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ - ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); + ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_init(device_t dev) diff --git a/src/cpu/samsung/exynos5250/dp-core.h b/src/cpu/samsung/exynos5250/dp-core.h index 144524d..73f4638 100644 --- a/src/cpu/samsung/exynos5250/dp-core.h +++ b/src/cpu/samsung/exynos5250/dp-core.h @@ -117,14 +117,6 @@ struct s5p_dp_device { struct link_train link_train; }; -/* this struct is used by mainboards to pass mode info to the driver */ -typedef struct vidinfo { - u16 vl_col; - u16 vl_row; - u8 vl_bpix; - u16 *cmap; -} vidinfo_t; - /* s5p_dp_reg.c */ /* @@ -260,9 +252,9 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; -void fb_init(vidinfo_t *panel_info, void *lcdbase, - struct exynos5_fimd_panel *pd); +void fb_init(unsigned long int fb_size, void *lcdbase, + struct exynos5_fimd_panel *pd); int dp_controller_init(struct s5p_dp_device *dp_device); -int lcd_ctrl_init(vidinfo_t *panel_info, - struct exynos5_fimd_panel *panel_data, void *lcdbase); +int lcd_ctrl_init(unsigned long int fb_size, + struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* CPU_SAMSUNG_EXYNOS5250_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5250/fb.c b/src/cpu/samsung/exynos5250/fb.c index d4c3d44..760f5ee 100644 --- a/src/cpu/samsung/exynos5250/fb.c +++ b/src/cpu/samsung/exynos5250/fb.c @@ -116,32 +116,21 @@ static void fimd_bypass(void) sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } -/* Calculate the size of Framebuffer from the resolution */ -static u32 calc_fbsize(vidinfo_t *panel_info) -{ - /* They had PAGE_SIZE here instead of 4096. - * but that's a totally arbitrary number -- everything nowadays - * has lots of page sizes. - * So keep it obvious. - */ - return ALIGN((panel_info->vl_col * panel_info->vl_row * - ((1<<panel_info->vl_bpix) / 8)), 4096); -} - /* * Initialize display controller. * * @param lcdbase pointer to the base address of framebuffer. * @pd pointer to the main panel_data structure */ -void fb_init(vidinfo_t *panel_info, void *lcdbase, - struct exynos5_fimd_panel *pd) +void fb_init(unsigned long int fb_size, void *lcdbase, + struct exynos5_fimd_panel *pd) { unsigned int val; - u32 fbsize; struct exynos5_fimd *fimd = samsung_get_base_fimd(); struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl(); + fb_size = ALIGN(fb_size, 4096); + writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); writel(val, &fimd->vidcon0); @@ -161,9 +150,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, writel(val, &disp_ctrl->vidtcon2); writel((unsigned int)lcdbase, &fimd->vidw00add0b0); - - fbsize = calc_fbsize(panel_info); - writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + writel((unsigned int)lcdbase + fb_size, &fimd->vidw00add1b0); writel(pd->xres * 2, &fimd->vidw00add2); @@ -586,12 +573,12 @@ int dp_controller_init(struct s5p_dp_device *dp_device) * @param lcdbase Base address of LCD frame buffer * @return 0 if ok, -ve error code on error */ -int lcd_ctrl_init(vidinfo_t *panel_info, - struct exynos5_fimd_panel *panel_data, void *lcdbase) +int lcd_ctrl_init(unsigned long int fb_size, + struct exynos5_fimd_panel *panel_data, void *lcdbase) { int ret = 0; fimd_bypass(); - fb_init(panel_info, lcdbase, panel_data); + fb_init(fb_size, lcdbase, panel_data); return ret; } diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 2dd56fc..76605bb 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -226,7 +226,7 @@ static void mainboard_init(device_t dev) disable_usb30_pll(); fb_addr = cbmem_find(CBMEM_ID_CONSOLE); - set_vbe_mode_info_valid(&edid, (uintptr_t)(fb_addr) + 64*KiB); + set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); do {

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Patch set updated for coreboot: 0c22dc3 ARM: Fix the way the space for the page tables is allocated.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3651 -gerrit commit 0c22dc3dfa8e5b61d88dfb032784b91c0c14dbed Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 21:41:59 2013 -0700 ARM: Fix the way the space for the page tables is allocated. The page tables need to be aligned to a 16KB boundary and are 16KB in size. The CBMEM allocator only guarantees 512 byte alignment, so to make sure things are where they're supposed to be, the code was allocating extra space and then adjusting the pointer upwards. Unfortunately, it was adding the size of the table to the pointer first, then aligning it. Since it allocated twice the space of the table, this had the effect of moving past the first table size region of bytes, and then aligning upwards, pushing the end of the table out of the space allocated for it. You can get away with this if you push things you don't care about off the end, and it happened to be the case that we were allocating a color map we weren't using at the start of the next part of cbmem. Change-Id: I6b196fc573801b02f27f2e667acbf06163266651 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/lib/mmu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c index d4e08f7..594bba5 100644 --- a/src/arch/armv7/lib/mmu.c +++ b/src/arch/armv7/lib/mmu.c @@ -118,11 +118,12 @@ void mmu_init(void) * programmer's guide) * * FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to - * 512 bytes. So add double the space in cbmem and fix-up the pointer. + * 512 bytes. So allocate some extra space in cbmem and fix-up the + * pointer. */ - ttb_size = L1_TLB_ENTRIES * sizeof(unsigned long); - ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2); - ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size); + ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t); + ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB); + ttb_addr = ALIGN(ttb_addr, 16*KiB); printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr); /*

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Patch set updated for coreboot: e17c449 snow: Make coreboot set up pins for busses it knows are hooked up as such.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3650 -gerrit commit e17c449636927d86b58b36891fc5a3eaf4b3c8ca Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 15:55:47 2013 -0700 snow: Make coreboot set up pins for busses it knows are hooked up as such. Coreboot knows that, for the snow board, certain pins are to be connected to bus controllers in the SOC and to the wires of a bus external to the SOC. It can configure them as such and free its payload from having to know how to set everything up. Change-Id: I1bb127c810e9ee077afc4227a6f316eaa53d6498 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/mainboard.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 250b71f..2dd56fc 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -176,6 +176,32 @@ static void disable_usb30_pll(void) gpio_direction_output(usb3_pll_l, 0); } +static void gpio_init(void) +{ + /* Set up the I2C busses. */ + exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE); + exynos_pinmux_config(PERIPH_ID_I2C1, PINMUX_FLAG_NONE); + exynos_pinmux_config(PERIPH_ID_I2C2, PINMUX_FLAG_NONE); + exynos_pinmux_config(PERIPH_ID_I2C3, PINMUX_FLAG_NONE); + exynos_pinmux_config(PERIPH_ID_I2C4, PINMUX_FLAG_NONE); + exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE); + + /* Set up the GPIOs used to arbitrate for I2C bus 4. */ + gpio_set_pull(GPIO_F03, GPIO_PULL_NONE); + gpio_set_pull(GPIO_E04, GPIO_PULL_NONE); + gpio_direction_output(GPIO_F03, 1); + gpio_direction_input(GPIO_E04); + + /* Set up the GPIO used to enable the audio codec. */ + gpio_set_pull(GPIO_X17, GPIO_PULL_NONE); + gpio_set_pull(GPIO_X15, GPIO_PULL_NONE); + gpio_direction_output(GPIO_X17, 1); + gpio_direction_output(GPIO_X15, 1); + + /* Set up the I2S busses. */ + exynos_pinmux_config(PERIPH_ID_I2S1, PINMUX_FLAG_NONE); +} + /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { @@ -186,6 +212,8 @@ static void mainboard_init(device_t dev) }; void *fb_addr; + gpio_init(); + i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE); i2c_init(7, I2C_0_SPEED, I2C_SLAVE);

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Patch set updated for coreboot: 9e1ffbb exynos5250: When enabling the I2S pins, turn off pull ups/downs.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3649 -gerrit commit 9e1ffbba52d99440073384cbeb62508593769931 Author: Gabe Black <gabeblack(a)google.com> Date: Sat May 18 15:52:01 2013 -0700 exynos5250: When enabling the I2S pins, turn off pull ups/downs. These pins will be driven by the internal controller which shouldn't have pull ups or downs in the pin fighting with them. Change-Id: I579aed84ace45d8f5f1d3ca64c064d98de842b57 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/pinmux.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c index 6991dfc..9a473d0 100644 --- a/src/cpu/samsung/exynos5250/pinmux.c +++ b/src/cpu/samsung/exynos5250/pinmux.c @@ -286,8 +286,10 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags) gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); break; case PERIPH_ID_I2S1: - for (i = 0; i < 5; i++) + for (i = 0; i < 5; i++) { gpio_cfg_pin(GPIO_B00 + i, GPIO_FUNC(0x02)); + gpio_set_pull(GPIO_B00 + i, GPIO_PULL_NONE); + } break; default: printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);

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Patch set updated for coreboot: 7c7025a exynos5420: Replace the 5250 GPIO code with code that should work on 5420.
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3648 -gerrit commit 7c7025a5c35a6caccfcc0b4a555e3749d69eed76 Author: Gabe Black <gabeblack(a)google.com> Date: Fri May 17 02:57:17 2013 -0700 exynos5420: Replace the 5250 GPIO code with code that should work on 5420. Change-Id: Iac6615240e94c74037afc801169c32d3ebc4ac03 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/cpu.h | 10 +- src/cpu/samsung/exynos5420/gpio.h | 430 ++++++++++++++++++-------------------- 2 files changed, 213 insertions(+), 227 deletions(-) diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 62ff424..7cdd35e 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -55,11 +55,7 @@ #define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 -#define EXYNOS5_GPIO_PART4_BASE 0x10D10000 /* V00..V37 */ -#define EXYNOS5_GPIO_PART5_BASE 0x10D100C0 /* V40..V47 */ #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 -#define EXYNOS5_GPIO_PART1_BASE 0x11400000 /* A00..Y67 */ -#define EXYNOS5_GPIO_PART2_BASE 0x11400c00 /* X00..X37 */ #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 #define EXYNOS5_USBPHY_BASE 0x12130000 #define EXYNOS5_USBOTG_BASE 0x12140000 @@ -76,7 +72,11 @@ #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 #define EXYNOS5_I2S_BASE 0x12D60000 -#define EXYNOS5_GPIO_PART3_BASE 0x13400000 /* E00..H17 */ +#define EXYNOS5_GPIO_PART3_BASE 0x13410000 /* C00..Y67 */ +#define EXYNOS5_GPIO_PART1_BASE 0x13400000 /* Y70..Y77 */ +#define EXYNOS5_GPIO_PART2_BASE 0x13400c00 /* X00..X37 */ +#define EXYNOS5_GPIO_PART4_BASE 0x14000000 /* E00..J47 */ +#define EXYNOS5_GPIO_PART5_BASE 0x14010000 /* A00..H07 */ #define EXYNOS5_FIMD_BASE 0x14400000 #define EXYNOS5_DISP1_CTRL_BASE 0x14420000 #define EXYNOS5_MIPI_DSI1_BASE 0x14500000 diff --git a/src/cpu/samsung/exynos5420/gpio.h b/src/cpu/samsung/exynos5420/gpio.h index 0787826..0011904 100644 --- a/src/cpu/samsung/exynos5420/gpio.h +++ b/src/cpu/samsung/exynos5420/gpio.h @@ -52,10 +52,12 @@ struct gpio_bank { #define GPIO_DRV_FAST 0x0 #define GPIO_DRV_SLOW 0x1 -#define EXYNOS5_GPIO_BASE0 0x11400000 -#define EXYNOS5_GPIO_BASE1 0x13400000 -#define EXYNOS5_GPIO_BASE2 0x10d10000 -#define EXYNOS5_GPIO_BASE3 0x03860000 +#define EXYNOS5_GPIO_BASE0 0x13400000 +#define EXYNOS5_GPIO_BASE1 0x13400c00 +#define EXYNOS5_GPIO_BASE2 0x13410000 +#define EXYNOS5_GPIO_BASE3 0x14000000 +#define EXYNOS5_GPIO_BASE4 0x14010000 +#define EXYNOS5_GPIO_BASE5 0x03860000 enum exynos5_gpio_port { /* @@ -64,59 +66,59 @@ enum exynos5_gpio_port { */ /* base == EXYNOS_GPIO_BASE0 */ - EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE0 + 0x0000, - EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE0 + 0x0020, - EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE0 + 0x0040, - - EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE0 + 0x0060, - EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE0 + 0x0080, - EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE0 + 0x00a0, - EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE0 + 0x00c0, - - EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE0 + 0x00e0, - EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE0 + 0x0100, - EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE0 + 0x0120, - EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE0 + 0x0140, - - EXYNOS5_GPD0 = EXYNOS5_GPIO_BASE0 + 0x0160, - EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE0 + 0x0180, - - EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE0 + 0x01a0, - EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE0 + 0x01c0, - EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE0 + 0x01e0, - EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE0 + 0x0200, - EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE0 + 0x0220, - EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE0 + 0x0240, - EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE0 + 0x0260, - - EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE0 + 0x0c00, - EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE0 + 0x0c20, - EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE0 + 0x0c40, - EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE0 + 0x0c60, + EXYNOS5_GPY7 = EXYNOS5_GPIO_BASE0 + 0x0000, /* base == EXYNOS_GPIO_BASE1 */ - EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE1 + 0x0000, - EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE1 + 0x0020, - - EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE1 + 0x0040, - EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE1 + 0x0060, - - EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE1 + 0x0080, - EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE1 + 0x00a0, - EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE1 + 0x00c0, - - EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE1 + 0x00e0, - EXYNOS5_GPH1 = EXYNOS5_GPIO_BASE1 + 0x0100, + EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE1 + 0x0000, + EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE1 + 0x0020, + EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE1 + 0x0040, + EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE1 + 0x0060, /* base == EXYNOS_GPIO_BASE2 */ - EXYNOS5_GPV0 = EXYNOS5_GPIO_BASE2 + 0x0000, - EXYNOS5_GPV1 = EXYNOS5_GPIO_BASE2 + 0x0020, - EXYNOS5_GPV2 = EXYNOS5_GPIO_BASE2 + 0x0060, - EXYNOS5_GPV3 = EXYNOS5_GPIO_BASE2 + 0x0080, - EXYNOS5_GPV4 = EXYNOS5_GPIO_BASE2 + 0x00c0, - - /* base == EXYNOS_GPIO_BASE3 */ - EXYNOS5_GPZ = EXYNOS5_GPIO_BASE3 + 0x0000, + EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE2 + 0x0000, + EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE2 + 0x0020, + EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE2 + 0x0040, + EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE2 + 0x0060, + EXYNOS5_GPC4 = EXYNOS5_GPIO_BASE2 + 0x0080, + + EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE2 + 0x00a0, + + EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE2 + 0x00c0, + EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE2 + 0x00e0, + EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE2 + 0x0100, + EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE2 + 0x0120, + EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE2 + 0x0140, + EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE2 + 0x0160, + EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE2 + 0x0180, + + /* base == EXYNOS5_GPIO_BASE3 */ + EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE3 + 0x0000, + EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE3 + 0x0020, + + EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE3 + 0x0040, + EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE3 + 0x0060, + + EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE3 + 0x0080, + EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE3 + 0x00a0, + EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE3 + 0x00c0, + + EXYNOS5_GPJ4 = EXYNOS5_GPIO_BASE3 + 0x00e0, + + /* base == EXYNOS5_GPIO_BASE4 */ + EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE4 + 0x0000, + EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE4 + 0x0020, + EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE4 + 0x0040, + + EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE4 + 0x0060, + EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE4 + 0x0080, + EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE4 + 0x00a0, + EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE4 + 0x00c0, + EXYNOS5_GPB4 = EXYNOS5_GPIO_BASE4 + 0x00e0, + + EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE4 + 0x0100, + + /* base == EXYNOS5_GPIO_BASE5 */ + EXYNOS5_GPZ0 = EXYNOS5_GPIO_BASE5 + 0x0000, }; enum { @@ -127,63 +129,53 @@ enum { /* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ enum exynos5_gpio_pin { /* GPIO_PART1_STARTS */ - GPIO_A00, - GPIO_A01, - GPIO_A02, - GPIO_A03, - GPIO_A04, - GPIO_A05, - GPIO_A06, - GPIO_A07, - GPIO_A10, - GPIO_A11, - GPIO_A12, - GPIO_A13, - GPIO_A14, - GPIO_A15, - GPIO_A16, - GPIO_A17, - GPIO_A20, - GPIO_A21, - GPIO_A22, - GPIO_A23, - GPIO_A24, - GPIO_A25, - GPIO_A26, - GPIO_A27, - GPIO_B00, /* 0x18 */ - GPIO_B01, - GPIO_B02, - GPIO_B03, - GPIO_B04, - GPIO_B05, - GPIO_B06, - GPIO_B07, - GPIO_B10, - GPIO_B11, - GPIO_B12, - GPIO_B13, - GPIO_B14, - GPIO_B15, - GPIO_B16, - GPIO_B17, - GPIO_B20, - GPIO_B21, - GPIO_B22, - GPIO_B23, - GPIO_B24, - GPIO_B25, - GPIO_B26, - GPIO_B27, - GPIO_B30, - GPIO_B31, - GPIO_B32, - GPIO_B33, - GPIO_B34, - GPIO_B35, - GPIO_B36, - GPIO_B37, - GPIO_C00, /* 0x38 */ + GPIO_Y70, + GPIO_Y71, + GPIO_Y72, + GPIO_Y73, + GPIO_Y74, + GPIO_Y75, + GPIO_Y76, + GPIO_Y77, + + /* GPIO_PART2_STARTS */ + GPIO_MAX_PORT_PART_1, + GPIO_X00 = GPIO_MAX_PORT_PART_1, /* 0x08 */ + GPIO_X01, + GPIO_X02, + GPIO_X03, + GPIO_X04, + GPIO_X05, + GPIO_X06, + GPIO_X07, + GPIO_X10, + GPIO_X11, + GPIO_X12, + GPIO_X13, + GPIO_X14, + GPIO_X15, + GPIO_X16, + GPIO_X17, + GPIO_X20, + GPIO_X21, + GPIO_X22, + GPIO_X23, + GPIO_X24, + GPIO_X25, + GPIO_X26, + GPIO_X27, + GPIO_X30, + GPIO_X31, + GPIO_X32, + GPIO_X33, + GPIO_X34, + GPIO_X35, + GPIO_X36, + GPIO_X37, + + /* GPIO_PART3_STARTS */ + GPIO_MAX_PORT_PART_2, + GPIO_C00 = GPIO_MAX_PORT_PART_2, /* 0x28 */ GPIO_C01, GPIO_C02, GPIO_C03, @@ -215,15 +207,16 @@ enum exynos5_gpio_pin { GPIO_C35, GPIO_C36, GPIO_C37, - GPIO_D00, /* 0x58 */ - GPIO_D01, - GPIO_D02, - GPIO_D03, - GPIO_D04, - GPIO_D05, - GPIO_D06, - GPIO_D07, - GPIO_D10, + GPIO_C40, + GPIO_C41, + GPIO_C42, + GPIO_C43, + GPIO_C44, + GPIO_C45, + GPIO_C46, + GPIO_C47, + + GPIO_D10, /* 0x50 */ GPIO_D11, GPIO_D12, GPIO_D13, @@ -231,7 +224,8 @@ enum exynos5_gpio_pin { GPIO_D15, GPIO_D16, GPIO_D17, - GPIO_Y00, /* 0x68 */ + + GPIO_Y00, /* 0x58 */ GPIO_Y01, GPIO_Y02, GPIO_Y03, @@ -288,44 +282,9 @@ enum exynos5_gpio_pin { GPIO_Y66, GPIO_Y67, - /* GPIO_PART2_STARTS */ - GPIO_MAX_PORT_PART_1, - GPIO_X00 = GPIO_MAX_PORT_PART_1, /* 0xa0 */ - GPIO_X01, - GPIO_X02, - GPIO_X03, - GPIO_X04, - GPIO_X05, - GPIO_X06, - GPIO_X07, - GPIO_X10, - GPIO_X11, - GPIO_X12, - GPIO_X13, - GPIO_X14, - GPIO_X15, - GPIO_X16, - GPIO_X17, - GPIO_X20, - GPIO_X21, - GPIO_X22, - GPIO_X23, - GPIO_X24, - GPIO_X25, - GPIO_X26, - GPIO_X27, - GPIO_X30, - GPIO_X31, - GPIO_X32, - GPIO_X33, - GPIO_X34, - GPIO_X35, - GPIO_X36, - GPIO_X37, - - /* GPIO_PART3_STARTS */ - GPIO_MAX_PORT_PART_2, - GPIO_E00 = GPIO_MAX_PORT_PART_2, /* 0xc0 */ + /* GPIO_PART4_STARTS */ + GPIO_MAX_PORT_PART_3, + GPIO_E00 = GPIO_MAX_PORT_PART_3, /* 0x90 */ GPIO_E01, GPIO_E02, GPIO_E03, @@ -341,7 +300,8 @@ enum exynos5_gpio_pin { GPIO_E15, GPIO_E16, GPIO_E17, - GPIO_F00, /* 0xd0 */ + + GPIO_F00, /* 0xa0 */ GPIO_F01, GPIO_F02, GPIO_F03, @@ -357,7 +317,8 @@ enum exynos5_gpio_pin { GPIO_F15, GPIO_F16, GPIO_F17, - GPIO_G00, + + GPIO_G00, /* 0xb0 */ GPIO_G01, GPIO_G02, GPIO_G03, @@ -381,7 +342,85 @@ enum exynos5_gpio_pin { GPIO_G25, GPIO_G26, GPIO_G27, - GPIO_H00, + + GPIO_J40, /* 0xc8 */ + GPIO_J41, + GPIO_J42, + GPIO_J43, + GPIO_J44, + GPIO_J45, + GPIO_J46, + GPIO_J47, + + /* GPIO_PART5_STARTS */ + GPIO_MAX_PORT_PART_4, + GPIO_A00 = GPIO_MAX_PORT_PART_4, /* 0xd0 */ + GPIO_A01, + GPIO_A02, + GPIO_A03, + GPIO_A04, + GPIO_A05, + GPIO_A06, + GPIO_A07, + GPIO_A10, + GPIO_A11, + GPIO_A12, + GPIO_A13, + GPIO_A14, + GPIO_A15, + GPIO_A16, + GPIO_A17, + GPIO_A20, + GPIO_A21, + GPIO_A22, + GPIO_A23, + GPIO_A24, + GPIO_A25, + GPIO_A26, + GPIO_A27, + + GPIO_B00, /* 0xe8 */ + GPIO_B01, + GPIO_B02, + GPIO_B03, + GPIO_B04, + GPIO_B05, + GPIO_B06, + GPIO_B07, + GPIO_B10, + GPIO_B11, + GPIO_B12, + GPIO_B13, + GPIO_B14, + GPIO_B15, + GPIO_B16, + GPIO_B17, + GPIO_B20, + GPIO_B21, + GPIO_B22, + GPIO_B23, + GPIO_B24, + GPIO_B25, + GPIO_B26, + GPIO_B27, + GPIO_B30, + GPIO_B31, + GPIO_B32, + GPIO_B33, + GPIO_B34, + GPIO_B35, + GPIO_B36, + GPIO_B37, + GPIO_B40, + GPIO_B41, + GPIO_B42, + GPIO_B43, + GPIO_B44, + GPIO_B45, + GPIO_B46, + GPIO_B47, + + GPIO_H00, /* 0x110 */ GPIO_H01, GPIO_H02, GPIO_H03, @@ -389,70 +428,17 @@ enum exynos5_gpio_pin { GPIO_H05, GPIO_H06, GPIO_H07, - GPIO_H10, - GPIO_H11, - GPIO_H12, - GPIO_H13, - GPIO_H14, - GPIO_H15, - GPIO_H16, - GPIO_H17, - - /* GPIO_PART4_STARTS */ - GPIO_MAX_PORT_PART_3, - GPIO_V00 = GPIO_MAX_PORT_PART_3, - GPIO_V01, - GPIO_V02, - GPIO_V03, - GPIO_V04, - GPIO_V05, - GPIO_V06, - GPIO_V07, - GPIO_V10, - GPIO_V11, - GPIO_V12, - GPIO_V13, - GPIO_V14, - GPIO_V15, - GPIO_V16, - GPIO_V17, - GPIO_V20, - GPIO_V21, - GPIO_V22, - GPIO_V23, - GPIO_V24, - GPIO_V25, - GPIO_V26, - GPIO_V27, - GPIO_V30, - GPIO_V31, - GPIO_V32, - GPIO_V33, - GPIO_V34, - GPIO_V35, - GPIO_V36, - GPIO_V37, - - /* GPIO_PART5_STARTS */ - GPIO_MAX_PORT_PART_4, - GPIO_V40 = GPIO_MAX_PORT_PART_4, - GPIO_V41, - GPIO_V42, - GPIO_V43, - GPIO_V44, - GPIO_V45, - GPIO_V46, - GPIO_V47, /* GPIO_PART6_STARTS */ GPIO_MAX_PORT_PART_5, - GPIO_Z0 = GPIO_MAX_PORT_PART_5, - GPIO_Z1, - GPIO_Z2, - GPIO_Z3, - GPIO_Z4, - GPIO_Z5, - GPIO_Z6, + GPIO_Z00 = GPIO_MAX_PORT_PART_5, /* 0x118 */ + GPIO_Z01, + GPIO_Z02, + GPIO_Z03, + GPIO_Z04, + GPIO_Z05, + GPIO_Z06, + GPIO_Z07, GPIO_MAX_PORT };

1 0

Patch set updated for coreboot: da4fee8 cpu: Add CPU microcode file to cbfs with 16-byte alignment
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3663 -gerrit commit da4fee8c1596de600c902d07ac8309cc45e3e7ca Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 11 16:36:37 2013 -0500 cpu: Add CPU microcode file to cbfs with 16-byte alignment On x86 there is a 16-byte alignment requirement for the addresses containing the CPU microcode. The cbfs files containing the microcode are used in memory-mapped fashion when loading new mircocode. Therefore, the data payload's address/offset of a cbfs file in flash dictates the resulting alignment. Fix this by processing the CPU microcode cbfs file separately as it uses $(CBFSTOOL) to find the proper location within the provided rom image. Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/Makefile.inc | 3 ++- src/arch/x86/Makefile.inc | 3 ++- src/cpu/Makefile.inc | 20 ++++++++++++++------ 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 1ef78d1..27a0df6 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -46,7 +46,7 @@ prebuild-files = \ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # TODO Change -b to Kconfig variable. -$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ @@ -56,6 +56,7 @@ $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuil -f $(objcbfs)/romstage.elf -b 0 \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7f1b7b2..0faf140 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -61,11 +61,12 @@ prebuild-files = \ $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m x86 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 \ -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 09d36ec..a860f67 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -15,17 +15,17 @@ subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 ## Rules for building the microcode blob in CBFS ################################################################################ +cpu_ucode_cbfs_name = cpu_microcode_blob.bin + # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) -cbfs-files-y += cpu_microcode_blob.bin -cpu_microcode_blob.bin-type = 0x53 -cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cbfs_include_ucode = y endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y) -cbfs-files-y += cpu_microcode_blob.bin -cpu_microcode_blob.bin-type = 0x53 -cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin +cbfs_include_ucode = y endif # In case we have more than one "source" (cough) files containing microcode, we @@ -42,3 +42,11 @@ $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -j .data -O binary $< $@ + +ifeq ($(cbfs_include_ucode),y) +# Add CPU microcode to specified rom image $(1) +add-cpu-microcode-to-cbfs = \ + $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 -b +else +add-cpu-microcode-to-cbfs = true +endif

1 0

Patch set updated for coreboot: fb274b8 google/snow: Don't spew output with GPIO config
by Gabe Black 10 Jul '13

10 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3661 -gerrit commit fb274b81c759b45b4169383822209bd30f508623 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 17 10:34:25 2013 -0700 google/snow: Don't spew output with GPIO config There are hundreds of GPIOs on the Exynos5250. Don't always print all of them per default. Change-Id: Ie349f2a4117883302b743027ed13cc9705b804f8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/mainboard.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 76605bb..a0d6a61 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -229,6 +229,8 @@ static void mainboard_init(device_t dev) set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); + + // FIXME: should timeout do { udelay(50); } while (!exynos_dp_hotplug()); @@ -256,7 +258,8 @@ static void mainboard_init(device_t dev) if (dp_tries > MAX_DP_TRIES) printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); - gpio_info(); + // Uncomment to get excessive GPIO output: + // gpio_info(); } static void mainboard_enable(device_t dev)

1 0

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coreboot-gerrit July 2013