Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3722
-gerrit
commit 550b54997f834ec994b8db07661728ea2321a5a2
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 30 06:09:12 2013 -0700
pit: Enable the ps8625 driver.
Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig
index 20e0084..89ffb5b 100644
--- a/src/mainboard/google/pit/Kconfig
+++ b/src/mainboard/google/pit/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_INIT_TIMER
+ select DRIVER_PARADE_PS8625
config MAINBOARD_DIR
string
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3723
-gerrit
commit e39ecc38133fb8e4b2fcad8ce2ec9cd915d75080
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 30 05:19:53 2013 -0700
pit: Redo the display port bridge initialization code.
The display port bridge on pit is different from the one on snow and needs to
be initialized differently. Instead of waiting for the chip to come up on its
own and assert the hotplug detect, we need to access it over i2c and get it up
and running ourselves.
Change-Id: I4bc911cb8e4463edff7beabd2f356cb70ae9f507
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/mainboard.c | 71 +++++++++---------------------------
1 file changed, 17 insertions(+), 54 deletions(-)
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 67d3b5d..54ea042 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -34,7 +34,9 @@
#include <cpu/samsung/exynos5420/power.h>
#include <cpu/samsung/exynos5420/i2c.h>
#include <cpu/samsung/exynos5420/dp-core.h>
+#include <drivers/parade/ps8625/ps8625.h>
#include <ec/google/chromeec/ec.h>
+#include <stdlib.h>
#include "exynos5420.h"
@@ -56,7 +58,7 @@ static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */
static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */
static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */
-static void exynos_dp_bridge_setup(void)
+static void parade_dp_bridge_setup(void)
{
gpio_set_value(dp_pd_l, 1);
gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT);
@@ -69,37 +71,19 @@ static void exynos_dp_bridge_setup(void)
gpio_set_value(dp_rst_l, 1);
gpio_cfg_pin(dp_hpd, GPIO_INPUT);
-}
-static void exynos_dp_bridge_init(void)
-{
- /* De-assert PD (and possibly RST) to power up the bridge */
+ /* De-assert PD (and possibly RST) to power up the bridge. */
gpio_set_value(dp_pd_l, 1);
gpio_set_value(dp_rst_l, 1);
- /*
- * We need to wait for 90ms after bringing up the bridge since
- * there is a phantom "high" on the HPD chip during its
- * bootup. The phantom high comes within 7ms of de-asserting
- * PD and persists for at least 15ms. The real high comes
- * roughly 50ms after PD is de-asserted. The phantom high
- * makes it hard for us to know when the NXP chip is up.
- */
- udelay(90000);
-}
+ /* Hang around for the bridge to come up. */
+ mdelay(40);
-static int exynos_dp_hotplug(void)
-{
- /* Check HPD. If it's high, we're all good. */
- return gpio_get_value(dp_hpd) ? 0 : 1;
-}
+ /* Configure the bridge chip. */
+ exynos_pinmux_i2c7();
+ i2c_init(7, 100000, 0x00);
-static void exynos_dp_reset(void)
-{
- gpio_set_value(dp_pd_l, 0);
- gpio_set_value(dp_rst_l, 0);
- /* paranoid delay period (300ms) */
- udelay(300 * 1000);
+ parade_ps8625_bridge_setup(7, 0x48);
}
/*
@@ -203,7 +187,6 @@ static void backlight_vdd(void)
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
- int dp_tries;
struct s5p_dp_device dp_device = {
.base = (struct exynos5_dp *)EXYNOS5420_DP1_BASE,
.video_info = &dp_video_info,
@@ -225,34 +208,14 @@ static void mainboard_init(device_t dev)
lcd_vdd();
- // FIXME: should timeout
- do {
- udelay(50);
- } while (!exynos_dp_hotplug());
-
- exynos_dp_bridge_setup();
- for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) {
- exynos_dp_bridge_init();
- if (exynos_dp_hotplug()) {
- printk(BIOS_ERR, "Hotplug detect failed.\n");
- exynos_dp_reset();
- continue;
- }
-
- if (dp_controller_init(&dp_device))
- continue;
-
- udelay(LCD_T3_DELAY_MS * 1000);
-
- backlight_vdd();
- backlight_pwm();
- backlight_en();
- /* if we're here, we're successful */
- break;
- }
+ parade_dp_bridge_setup();
+ dp_controller_init(&dp_device);
+
+ udelay(LCD_T3_DELAY_MS * 1000);
- if (dp_tries > MAX_DP_TRIES)
- printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
+ backlight_vdd();
+ backlight_pwm();
+ backlight_en();
// Uncomment to get excessive GPIO output:
// gpio_info();
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3720
-gerrit
commit 06513f724aa434d6de1eb6c2090175c365643c1b
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 30 03:37:24 2013 -0700
pit: Stop setting up the hardware dp hotplug detect in ROM stage too.
This was removed from ramstage a little while ago and should have been removed
from here as well.
Change-Id: I6a40ed4a98bedac39e5492e4b1aed3427ab4e08b
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/romstage.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index f123253..a757615 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -135,11 +135,6 @@ static void setup_ec(void)
exynos_pinmux_spi2();
}
-static void setup_graphics(void)
-{
- exynos_pinmux_dphpd();
-}
-
static void setup_gpio(void)
{
gpio_direction_input(GPIO_X30); // WP_GPIO
@@ -280,7 +275,6 @@ void main(void)
setup_storage();
setup_gpio();
- setup_graphics();
setup_ec();
simple_spi_test();
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3715
-gerrit
commit 95b92c4435ddbe9aefee246bcd371d3468b188cb
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Wed Jun 26 21:22:55 2013 +0800
armv7/exynos5420: Remove the extra reopen when reading SPI.
The workaround of re-opening device in exynos_spi_read has been fixed by the new
correct open/close and xfer procedure. It's safe to be removed now.
Change-Id: I6b1bf717c916903999a137998a578b0a866829bd
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/spi.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c
index 906f6a7..1c60378 100644
--- a/src/cpu/samsung/exynos5420/spi.c
+++ b/src/cpu/samsung/exynos5420/spi.c
@@ -364,9 +364,6 @@ static size_t exynos_spi_cbfs_read(struct cbfs_media *media, void *dest,
int bytes;
DEBUG_SPI("exynos_spi_cbfs_read(%u)\n", count);
bytes = exynos_spi_read(spi->slave, dest, count, offset);
- // Flush and re-open the device.
- spi_release_bus(spi->slave);
- spi_claim_bus(spi->slave);
return bytes;
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3712
-gerrit
commit b800a8757508fdff401c24792ff73217b6f2aa3b
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Wed Jun 26 20:22:50 2013 +0800
armv7/exynos5420: Revise SPI open/close/reset procedure.
The original Exynos SPI open/close procedure was copied from U-Boot SPL with
some assumptions that only works in SPL stage. For example, it tries to always
work in 4-byte transmission mode with only RX data is swapped, and claims a
packet for initial address command (and with incorrect size).
This commit revises open/close and reset so only the required SPI registers are
configured.
Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/spi.c | 76 +++++++++++++++++++++-------------------
1 file changed, 39 insertions(+), 37 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c
index 82c3765..6637aad 100644
--- a/src/cpu/samsung/exynos5420/spi.c
+++ b/src/cpu/samsung/exynos5420/spi.c
@@ -102,6 +102,26 @@ void spi_cs_deactivate(struct spi_slave *slave)
setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);
}
+static inline void exynos_spi_soft_reset(struct exynos_spi *regs)
+{
+ /* The soft reset clears only FIFO and status register.
+ * All special function registers are not changed. */
+ setbits_le32(®s->ch_cfg, SPI_CH_RST);
+ clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+}
+
+static inline void exynos_spi_flush_fifo(struct exynos_spi *regs)
+{
+ /*
+ * Flush spi tx, rx fifos and reset the SPI controller
+ * and clear rx/tx channel
+ */
+ clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+ clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN);
+ exynos_spi_soft_reset(regs);
+ setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+}
+
static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
void *dinp, void const *doutp, int i)
{
@@ -114,8 +134,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
ASSERT(todo % 4 == 0);
out_bytes = in_bytes = todo;
- setbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ exynos_spi_soft_reset(regs);
writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
while (in_bytes) {
@@ -143,35 +162,27 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
}
}
-/* set up SPI channel */
int spi_claim_bus(struct spi_slave *slave)
{
struct exynos_spi_slave *espi = to_exynos_spi(slave);
struct exynos_spi *regs = espi->regs;
- /* set the spi1 GPIO */
+ exynos_spi_flush_fifo(regs);
- /* set pktcnt and enable it */
- writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
- /* set FB_CLK_SEL */
- writel(SPI_FB_DELAY_180, ®s->fb_clk);
- /* set CH_WIDTH and BUS_WIDTH as word */
- setbits_le32(®s->mode_cfg,
- SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
- clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
+ // Select Active High Clock, Format A (SCP 30.2.1.8).
+ clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L | SPI_CH_CPHA_B);
- /* clear rx and tx channel if set priveously */
- clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
-
- setbits_le32(®s->swap_cfg,
- SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP);
-
- /* do a soft reset */
- setbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
+ // Set FeedBack Clock Selection.
+ writel(SPI_FB_DELAY_180, ®s->fb_clk);
- /* now set rx and tx channel ON */
- setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
+ // HIGH speed is required for Tx/Rx to work in 50MHz (SCP 30.2.1.6).
+ if (espi->half_duplex) {
+ clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN);
+ printk(BIOS_DEBUG, "%s: LOW speed.\n", __func__);
+ } else {
+ setbits_le32(®s->ch_cfg, SPI_CH_HS_EN);
+ printk(BIOS_DEBUG, "%s: HIGH speed.\n", __func__);
+ }
return 0;
}
@@ -209,21 +220,12 @@ static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len,
void spi_release_bus(struct spi_slave *slave)
{
struct exynos_spi *regs = to_exynos_spi(slave)->regs;
- /*
- * Let put controller mode to BYTE as
- * SPI driver does not support WORD mode yet
- */
- clrbits_le32(®s->mode_cfg,
- SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
+ /* Reset swap mode to make sure no one relying on default values (Ex,
+ * payload or kernel) will go wrong. */
+ clrbits_le32(®s->mode_cfg, (SPI_MODE_CH_WIDTH_WORD |
+ SPI_MODE_BUS_WIDTH_WORD));
writel(0, ®s->swap_cfg);
-
- /*
- * Flush spi tx, rx fifos and reset the SPI controller
- * and clear rx/tx channel
- */
- clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_CH_RST);
- clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+ exynos_spi_flush_fifo(regs);
}
// SPI as CBFS media.
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3719
-gerrit
commit 3b028e2c77d583fba88bd0b405c4727ef3449d74
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Wed Jun 26 17:28:52 2013 -0700
PIT: add panel to the list of things to be powered up by the PMIC
This appears to be needed, though we have no way to test yet.
Change-Id: I39033581011e056258193f2cdff78814361a8d55
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/romstage.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 30c8aeb..f123253 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -71,7 +71,8 @@ struct pmic_write pmic_writes[] =
MAX77802_BUCK_TYPE2_IGNORE_PWRREQ },
{ 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V },
{ 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON |
- MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }
+ MAX77802_BUCK_TYPE1_IGNORE_PWRREQ },
+ { 1, MAX77802_REG_PMIC_LDO35CTRL1, MAX77802_LDO35CTRL1_1_2V },
};
static void setup_power(int is_resume)