Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3687
-gerrit
commit 05973a44b21bdf03acd35aa00889d71cfec6c05a
Author: Gabe Black <gabeblack(a)google.com>
Date: Wed Jun 19 02:18:25 2013 -0700
pit: Stop compiling in the max77686 driver on pit.
That part isn't used on pit.
Change-Id: I48f3a10f7e6eb89b1e9630d2372b6865b4c12a7f
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig
index b3094a2..d7409d3 100644
--- a/src/mainboard/google/pit/Kconfig
+++ b/src/mainboard/google/pit/Kconfig
@@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_I2C
select BOARD_ROMSIZE_KB_4096
- select DRIVER_MAXIM_MAX77686
select CHROMEOS
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3683
-gerrit
commit 02c4c8486bfce79bcec870dda1318b200baba2c3
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Wed Jun 19 12:02:47 2013 -0700
Samsung CPUs: Unify Kconfig
For all other CPUs, we unconditionally include the CPU Kconfig
files in the CPU directory, not in the vendor directory. Do the
same thing for the Exynos CPUs. This allows us to make CPU dependent
changes in the directory of that CPU alone.
Also, drop some unused Kconfig variables from the Exynos Kconfig
files.
Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/Kconfig | 22 ----------------------
src/cpu/samsung/exynos5250/Kconfig | 27 ++++++++++++---------------
src/cpu/samsung/exynos5420/Kconfig | 20 +++++++++++---------
3 files changed, 23 insertions(+), 46 deletions(-)
diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig
index 54f4ed1..ae37403 100644
--- a/src/cpu/samsung/Kconfig
+++ b/src/cpu/samsung/Kconfig
@@ -1,24 +1,2 @@
-config CPU_SAMSUNG_EXYNOS5250
- depends on ARCH_ARMV7
- select HAVE_MONOTONIC_TIMER
- select HAVE_UART_SPECIAL
- select DEFAULT_BOOTBLOCK_CONSOLE
- select DEFAULT_EARLY_CONSOLE
- bool
- default n
-
-config CPU_SAMSUNG_EXYNOS5420
- depends on ARCH_ARMV7
- select HAVE_MONOTONIC_TIMER
- select HAVE_UART_SPECIAL
- select DEFAULT_EARLY_CONSOLE
- bool
- default n
-
-if CPU_SAMSUNG_EXYNOS5250
source src/cpu/samsung/exynos5250/Kconfig
-endif
-
-if CPU_SAMSUNG_EXYNOS5420
source src/cpu/samsung/exynos5420/Kconfig
-endif
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 75d1178..d6c3f1e 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -1,3 +1,14 @@
+config CPU_SAMSUNG_EXYNOS5250
+ depends on ARCH_ARMV7
+ select HAVE_MONOTONIC_TIMER
+ select HAVE_UART_SPECIAL
+ select DEFAULT_BOOTBLOCK_CONSOLE
+ select DEFAULT_EARLY_CONSOLE
+ bool
+ default n
+
+if CPU_SAMSUNG_EXYNOS5250
+
config BOOTBLOCK_CPU_INIT
string
default "cpu/samsung/exynos5250/bootblock.c"
@@ -6,10 +17,6 @@ config BOOTBLOCK_CPU_INIT
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
-config EXYNOS_ACE_SHA
- bool
- default n
-
# ROM image layout.
#
# 0x0000: vendor-provided BL1 (8k).
@@ -77,17 +84,6 @@ config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x000017000
-# FIXME: This is for copying SPI content into SRAM temporarily and
-# will be removed when we have the SPI streaming driver implemented.
-config SPI_IMAGE_HACK
- hex
- default 0x02060000
-
-# FIXME: other magic numbers that should probably go away
-config XIP_ROM_SIZE
- hex
- default ROMSTAGE_SIZE
-
config SYS_SDRAM_BASE
hex
default 0x40000000
@@ -137,3 +133,4 @@ config CONSOLE_SERIAL_UART_ADDRESS
help
Map the UART names to the respective MMIO address.
+endif
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig
index 406ffd2..efa0b21 100644
--- a/src/cpu/samsung/exynos5420/Kconfig
+++ b/src/cpu/samsung/exynos5420/Kconfig
@@ -1,3 +1,13 @@
+config CPU_SAMSUNG_EXYNOS5420
+ depends on ARCH_ARMV7
+ select HAVE_MONOTONIC_TIMER
+ select HAVE_UART_SPECIAL
+ select DEFAULT_EARLY_CONSOLE
+ bool
+ default n
+
+if CPU_SAMSUNG_EXYNOS5420
+
config BOOTBLOCK_CPU_INIT
string
default "cpu/samsung/exynos5420/bootblock.c"
@@ -6,10 +16,6 @@ config BOOTBLOCK_CPU_INIT
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
-config EXYNOS_ACE_SHA
- bool
- default n
-
# ROM image layout.
#
# 0x0000: vendor-provided BL1 (8k).
@@ -79,11 +85,6 @@ config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x000013000
-# FIXME: other magic numbers that should probably go away
-config XIP_ROM_SIZE
- hex
- default ROMSTAGE_SIZE
-
config SYS_SDRAM_BASE
hex
default 0x20000000
@@ -133,3 +134,4 @@ config CONSOLE_SERIAL_UART_ADDRESS
help
Map the UART names to the respective MMIO address.
+endif
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3693
-gerrit
commit ffcc2655e861be6db45ae59525e3562e6905884e
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Wed Jun 19 15:46:25 2013 -0700
Exynos5420: add code to make sure resume will work on DRAM.
Found during a perusal of u-boot changes. It looks important.
For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commi…
Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/bootblock.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c
index d3d737e..5cc9ef6 100644
--- a/src/cpu/samsung/exynos5420/bootblock.c
+++ b/src/cpu/samsung/exynos5420/bootblock.c
@@ -19,10 +19,28 @@
#include "clk.h"
#include "wakeup.h"
+#include "cpu.h"
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
+ u32 ret;
+ /*
+ * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+ * pad retention, CKE goes high. This causes memory contents
+ * not to be retained during DRAM initialization. Therfore,
+ * there is a new control register(0x100431e8[28]) which lets us
+ * release pad retention and retain the memory content until the
+ * initialization is complete.
+ */
+ if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) {
+ write32(PAD_RETENTION_DRAM_COREBLK_VAL,
+ (void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
+ do {
+ ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
+ } while (ret != 0x1);
+ }
+
/* kick off the multi-core timer.
* We want to do this as early as we can.
*/