Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3645
-gerrit
commit 4ee373c4de0d5c27d11f9d4dc84efb728b012095
Author: Gabe Black <gabeblack(a)google.com>
Date: Mon May 13 15:56:53 2013 -0700
pit: Fix some settings for the exynos5420 CPU.
Some of the settings which were defaulted to or automatically selected for the
exynos5420 which were inherited from the exynos5250 were not correct for this
SOC.
Change-Id: I11ffd8a6b80628405ac493fe2139f79c05d15d7e
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/Kconfig | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig
index 2f7ea94..93ece2e 100644
--- a/src/cpu/samsung/exynos5420/Kconfig
+++ b/src/cpu/samsung/exynos5420/Kconfig
@@ -17,13 +17,13 @@ config BL1_SIZE_KB
# Example SRAM/iRAM map for Exynos5420 platform:
#
# 0x0202_0000: vendor-provided BL1
-# 0x0202_3400: bootblock, assume up to 32KB in size
+# 0x0202_4400: bootblock, assume up to 32KB in size
# 0x0203_0000: romstage, assume up to 128KB in size.
-# 0x0207_8000: stack pointer
+# 0x0207_4000: stack pointer
config BOOTBLOCK_BASE
hex
- default 0x02023400
+ default 0x02024400
config ROMSTAGE_BASE
hex
@@ -40,11 +40,11 @@ config ROMSTAGE_SIZE
# consecutive memory locations ending just below SP
config STACK_TOP
hex
- default 0x02078000
+ default 0x02074000
config STACK_BOTTOM
hex
- default 0x02077000
+ default 0x02073000
config STACK_SIZE
hex
@@ -69,13 +69,7 @@ config CBFS_CACHE_ADDRESS
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
- default 0x000017000
-
-# FIXME: This is for copying SPI content into SRAM temporarily and
-# will be removed when we have the SPI streaming driver implemented.
-config SPI_IMAGE_HACK
- hex
- default 0x02060000
+ default 0x000013000
# FIXME: other magic numbers that should probably go away
config XIP_ROM_SIZE
@@ -84,11 +78,11 @@ config XIP_ROM_SIZE
config SYS_SDRAM_BASE
hex
- default 0x40000000
+ default 0x20000000
config SYS_TEXT_BASE
hex
- default 0x43e00000
+ default 0x23e00000
config COREBOOT_TABLES_SIZE
hex
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3655
-gerrit
commit 3452a38360f6c24a227156ed41dc2fb93566a109
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat May 18 23:06:47 2013 -0700
exynos5250: Clear the framebuffer before making it uncacheable.
If we clear the framebuffer and then flush it back to memory using cache
operations, the writes are going to be full cachelines at a time. If we make
it uncacheable first, the writes will be serialized writes of whatever sized
chunks memset uses, probably 4 bytes or less.
Change-Id: I1b81731cfed00ae091ba6357451ab186d16f559e
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5250/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index d2a6df7..3687ea8 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev)
lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size);
printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase));
+ memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
+
/*
* We need to clean and invalidate the framebuffer region and disable
* caching as well. We assume that our dcache <--> memory address
@@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev)
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
"Initializing Exynos VGA, base %p\n", (void *)lcdbase);
- memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase);
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3654
-gerrit
commit 7306681a84a07a87fa803aa2da591073af07d116
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat May 18 22:57:34 2013 -0700
exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer.
At one time it seemed to be necessary to disable and then re-enable the MMU
when setting the framebuffer to be uncache-able due to bugs in the MMU
management code. Since those bugs have been fixed, this is no longer
necessary.
Change-Id: I5f7b9bd14dc9929efe1834ec9a258d388b8c94e9
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5250/cpu.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 3ab57c9..d2a6df7 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -105,15 +105,11 @@ static void exynos_displayport_init(device_t dev)
* Note: We may want to do something clever to ensure the framebuffer
* region is aligned such that we don't change dcache policy for other
* stuff inadvertantly.
- *
- * FIXME: Is disabling/re-enabling the MMU entirely necessary?
*/
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva(lower, upper - lower);
- dcache_mmu_disable();
mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF);
- dcache_mmu_enable();
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3653
-gerrit
commit c4660f65364abb4ba89ffd14c99fb85b298f5567
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat May 18 22:45:54 2013 -0700
ARM: Fix up page table/cachability management.
When modifying the page tables, use writel to ensure the writes happen, flush
the page tables themselves to ensure they're visible to the MMU if it doesn't
look at the caches, and invalidate the right TLB entries.
The first two changes are probably safer but may not be strictly necessary.
The third change is necessary because we were invalidating the TLB using i
which was in megabytes but using an instruction that expects an address in
bytes.
One symptom of this problem was that the framebuffer, which was supposed to be
marked uncacheable, was only being partially updated since some of the updates
were still in the cache. With this change the graphics show up correctly.
Change-Id: I5475df29690371459b0d37a304eebc62f81dd76b
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/lib/mmu.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c
index 594bba5..7d6d46a 100644
--- a/src/arch/armv7/lib/mmu.c
+++ b/src/arch/armv7/lib/mmu.c
@@ -34,6 +34,7 @@
#include <console/console.h>
#include <arch/cache.h>
+#include <arch/io.h>
#define L1_TLB_ENTRIES 4096 /* 1 entry for each 1MB address space */
@@ -44,11 +45,14 @@ void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
unsigned int i;
uint32_t *ttb_entry = (uint32_t *)ttb_addr;
printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n",
- start_mb << 20, ((start_mb + size_mb) << 20) - 1);
+ start_mb*MiB, start_mb*MiB + size_mb*MiB - 1);
+
+ for (i = start_mb; i < start_mb + size_mb; i++)
+ writel(0, &ttb_entry[i]);
for (i = start_mb; i < start_mb + size_mb; i++) {
- ttb_entry[i] = 0;
- tlbimvaa(i);
+ dccmvac((uintptr_t)&ttb_entry[i]);
+ tlbimvaa(i*MiB);
}
}
@@ -99,9 +103,14 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n",
start_mb << 20, ((start_mb + size_mb) << 20) - 1, str);
+ /* Write out page table entries. */
+ for (i = start_mb; i < start_mb + size_mb; i++)
+ writel((i << 20) | attr, &ttb_entry[i]);
+
+ /* Flush the page table entries, and old translations from the TLB. */
for (i = start_mb; i < start_mb + size_mb; i++) {
- ttb_entry[i] = (i << 20) | attr;
- tlbimvaa(start_mb);
+ dccmvac((uintptr_t)&ttb_entry[i]);
+ tlbimvaa(i*MiB);
}
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3651
-gerrit
commit 6e2063d961e936b02c9df8cb3fff6fa3ca89f477
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat May 18 21:41:59 2013 -0700
ARM: Fix the way the space for the page tables is allocated.
The page tables need to be aligned to a 16KB boundary and are 16KB in size.
The CBMEM allocator only guarantees 512 byte alignment, so to make sure
things are where they're supposed to be, the code was allocating extra space
and then adjusting the pointer upwards. Unfortunately, it was adding the size
of the table to the pointer first, then aligning it. Since it allocated twice
the space of the table, this had the effect of moving past the first table
size region of bytes, and then aligning upwards, pushing the end of the table
out of the space allocated for it.
You can get away with this if you push things you don't care about off the
end, and it happened to be the case that we were allocating a color map we
weren't using at the start of the next part of cbmem.
Change-Id: I6b196fc573801b02f27f2e667acbf06163266651
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/lib/mmu.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/arch/armv7/lib/mmu.c b/src/arch/armv7/lib/mmu.c
index d4e08f7..594bba5 100644
--- a/src/arch/armv7/lib/mmu.c
+++ b/src/arch/armv7/lib/mmu.c
@@ -118,11 +118,12 @@ void mmu_init(void)
* programmer's guide)
*
* FIXME: TLB needs to be aligned to 16KB, but cbmem_add() aligns to
- * 512 bytes. So add double the space in cbmem and fix-up the pointer.
+ * 512 bytes. So allocate some extra space in cbmem and fix-up the
+ * pointer.
*/
- ttb_size = L1_TLB_ENTRIES * sizeof(unsigned long);
- ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size * 2);
- ttb_addr = ALIGN(ttb_addr + ttb_size, ttb_size);
+ ttb_size = L1_TLB_ENTRIES * sizeof(uint32_t);
+ ttb_addr = (uintptr_t)cbmem_add(CBMEM_ID_GDT, ttb_size + 16*KiB);
+ ttb_addr = ALIGN(ttb_addr, 16*KiB);
printk(BIOS_DEBUG, "Translation table is @ 0x%08x\n", ttb_addr);
/*
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3650
-gerrit
commit 661daaafb5fc0a255574c7db8e661441525d8054
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat May 18 15:55:47 2013 -0700
snow: Make coreboot set up pins for busses it knows are hooked up as such.
Coreboot knows that, for the snow board, certain pins are to be connected to
bus controllers in the SOC and to the wires of a bus external to the SOC. It
can configure them as such and free its payload from having to know how to
set everything up.
Change-Id: I1bb127c810e9ee077afc4227a6f316eaa53d6498
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/snow/mainboard.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 250b71f..2dd56fc 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -176,6 +176,32 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void gpio_init(void)
+{
+ /* Set up the I2C busses. */
+ exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C1, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C2, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C3, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C4, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+
+ /* Set up the GPIOs used to arbitrate for I2C bus 4. */
+ gpio_set_pull(GPIO_F03, GPIO_PULL_NONE);
+ gpio_set_pull(GPIO_E04, GPIO_PULL_NONE);
+ gpio_direction_output(GPIO_F03, 1);
+ gpio_direction_input(GPIO_E04);
+
+ /* Set up the GPIO used to enable the audio codec. */
+ gpio_set_pull(GPIO_X17, GPIO_PULL_NONE);
+ gpio_set_pull(GPIO_X15, GPIO_PULL_NONE);
+ gpio_direction_output(GPIO_X17, 1);
+ gpio_direction_output(GPIO_X15, 1);
+
+ /* Set up the I2S busses. */
+ exynos_pinmux_config(PERIPH_ID_I2S1, PINMUX_FLAG_NONE);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -186,6 +212,8 @@ static void mainboard_init(device_t dev)
};
void *fb_addr;
+ gpio_init();
+
i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE);
i2c_init(7, I2C_0_SPEED, I2C_SLAVE);
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3649
-gerrit
commit de979e0a987ab0583a67218cee2ceba980e298b0
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat May 18 15:52:01 2013 -0700
exynos5250: When enabling the I2S pins, turn off pull ups/downs.
These pins will be driven by the internal controller which shouldn't have pull
ups or downs in the pin fighting with them.
Change-Id: I579aed84ace45d8f5f1d3ca64c064d98de842b57
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5250/pinmux.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c
index 6991dfc..9a473d0 100644
--- a/src/cpu/samsung/exynos5250/pinmux.c
+++ b/src/cpu/samsung/exynos5250/pinmux.c
@@ -286,8 +286,10 @@ int exynos_pinmux_config(enum periph_id peripheral, int flags)
gpio_set_pull(GPIO_X07, GPIO_PULL_NONE);
break;
case PERIPH_ID_I2S1:
- for (i = 0; i < 5; i++)
+ for (i = 0; i < 5; i++) {
gpio_cfg_pin(GPIO_B00 + i, GPIO_FUNC(0x02));
+ gpio_set_pull(GPIO_B00 + i, GPIO_PULL_NONE);
+ }
break;
default:
printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);