Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3668
-gerrit
commit 939611002e4ac8468d7eab6e397348d2fc3d3bae
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon May 20 15:24:13 2013 -0700
exynos5420: Clear the framebuffer before making it uncacheable
If we clear the framebuffer and then flush it back to memory using cache
operations, the writes are going to be full cachelines at a time. If we
make it uncacheable first, the writes will be serialized writes of
whatever sized chunks memset uses, probably 4 bytes or less.
Change-Id: I960f87a370e97f9e91236ad796d931573bb3dbb8
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index 1d51174..6e360bf 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev)
lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size);
printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase));
+ memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
+
/*
* We need to clean and invalidate the framebuffer region and disable
* caching as well. We assume that our dcache <--> memory address
@@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev)
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
"Initializing Exynos VGA, base %p\n", (void *)lcdbase);
- memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase);
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3667
-gerrit
commit aaea996cfa60e44d48e93d8e1f7529ea3d3875e5
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon May 20 15:21:48 2013 -0700
exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer
At one time it seemed to be necessary to disable and then re-enable the
MMU when setting the framebuffer to be uncache-able due to bugs in the
MMU management code. Since those bugs have been fixed, this is no longer
necessary.
Change-Id: I7ce825cf5eaaa95119364d780cba0935752e4632
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/cpu/samsung/exynos5420/cpu.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index e83c16a..1d51174 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -105,15 +105,11 @@ static void exynos_displayport_init(device_t dev)
* Note: We may want to do something clever to ensure the framebuffer
* region is aligned such that we don't change dcache policy for other
* stuff inadvertantly.
- *
- * FIXME: Is disabling/re-enabling the MMU entirely necessary?
*/
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva(lower, upper - lower);
- dcache_mmu_disable();
mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF);
- dcache_mmu_enable();
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3679
-gerrit
commit b76bfb542c90238f6902ffb7fdcbce683fdea439
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Tue Jun 18 13:02:23 2013 -0700
ARM: when setting a GPIO to put, set the value, then the direction
We saw a problem on x86 last year in which setting direction, then value,
glitched the output and caused problems. Change this code to set the output,
then the direction.
Change-Id: I3e1e17ffe82ae270eea539530368a58c6cfe0ebe
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5250/gpio.c | 4 ++--
src/cpu/samsung/exynos5420/gpio.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/gpio.c b/src/cpu/samsung/exynos5250/gpio.c
index b8ebb0a..2a93328 100644
--- a/src/cpu/samsung/exynos5250/gpio.c
+++ b/src/cpu/samsung/exynos5250/gpio.c
@@ -170,14 +170,14 @@ int gpio_direction_output(unsigned gpio, int value)
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
- gpio_cfg_pin(gpio, GPIO_OUTPUT);
-
val = readl(&bank->dat);
val &= ~DAT_MASK(GPIO_BIT(gpio));
if (value)
val |= DAT_SET(GPIO_BIT(gpio));
writel(val, &bank->dat);
+ gpio_cfg_pin(gpio, GPIO_OUTPUT);
+
return 0;
}
diff --git a/src/cpu/samsung/exynos5420/gpio.c b/src/cpu/samsung/exynos5420/gpio.c
index b8ebb0a..2a93328 100644
--- a/src/cpu/samsung/exynos5420/gpio.c
+++ b/src/cpu/samsung/exynos5420/gpio.c
@@ -170,14 +170,14 @@ int gpio_direction_output(unsigned gpio, int value)
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
- gpio_cfg_pin(gpio, GPIO_OUTPUT);
-
val = readl(&bank->dat);
val &= ~DAT_MASK(GPIO_BIT(gpio));
if (value)
val |= DAT_SET(GPIO_BIT(gpio));
writel(val, &bank->dat);
+ gpio_cfg_pin(gpio, GPIO_OUTPUT);
+
return 0;
}