Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3690
-gerrit
commit e421389075afa5f202c74a49d2834f67288c8c5a
Author: Gabe Black <gabeblack(a)google.com>
Date: Wed Jun 19 20:15:57 2013 -0700
ARM: Don't leave alignment checking on after the exception test.
Currently, the exception handling code on ARM turns on alignment checks as an
easy way to generate an exception for testing purposes. It was leaving it on
which disabled unaligned accesses for other, unlreated code running later.
This change adjusts the code so the original value of the alignment bit is
restored after the test exception.
Change-Id: Id8d035a05175f9fb13de547ab4aa5496d681d30c
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/exception.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/arch/armv7/exception.c b/src/arch/armv7/exception.c
index 14f8216..1055cb5 100644
--- a/src/arch/armv7/exception.c
+++ b/src/arch/armv7/exception.c
@@ -143,9 +143,8 @@ void exception_init(void)
sctlr &= ~sctlr_te;
/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
sctlr &= ~sctlr_v;
- /* Enforce alignment. */
- sctlr |= sctlr_a;
- set_sctlr(sctlr);
+ /* Enforce alignment temporarily. */
+ set_sctlr(sctlr | sctlr_a);
extern uint32_t exception_table[];
set_vbar((uintptr_t)exception_table);
@@ -155,4 +154,7 @@ void exception_init(void)
exception_test();
test_abort = 0;
printk(BIOS_ERR, "Testing exceptions: DONE\n");
+
+ /* Restore original alignment settings. */
+ set_sctlr(sctlr);
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3702
-gerrit
commit f1e082d45780546728d1dca368e2d9913674d32b
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 23 03:16:46 2013 -0700
pit: Configure the pinmux for the i2c busses that are connected on pit.
Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/mainboard.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 1608788..64783ad 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -159,6 +159,17 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void gpio_init(void)
+{
+ /* Set up the I2C busses. */
+ exynos_pinmux_i2c2();
+ exynos_pinmux_i2c4();
+ exynos_pinmux_i2c7();
+ exynos_pinmux_i2c8();
+ exynos_pinmux_i2c9();
+ exynos_pinmux_i2c10();
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -169,6 +180,8 @@ static void mainboard_init(device_t dev)
};
void *fb_addr;
+ gpio_init();
+
tmu_init(&exynos5420_tmu_info);
/* Clock Gating all the unused IP's to save power */
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3703
-gerrit
commit 89498903525c3dc6bdb9ab930ee5b33ca84946ad
Author: Gabe Black <gabeblack(a)google.com>
Date: Mon Jun 24 03:14:41 2013 -0700
exynos5420: Clock the mmc blocks off of the mpll.
The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
been set to use a different pll. This changes them over and modifies the
divider so that the frequency stays the same.
Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/setup.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 7d63772..e89ed8e 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -222,7 +222,7 @@ struct exynos5_phy_control;
#define CLK_DIV_CPU0_VAL 0x01440020
/* CLK_SRC_TOP */
-#define CLK_SRC_TOP0_VAL 0x12221222
+#define CLK_SRC_TOP0_VAL 0x12222222
#define CLK_SRC_TOP1_VAL 0x00100200
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x11111111
@@ -231,7 +231,7 @@ struct exynos5_phy_control;
#define CLK_SRC_TOP7_VAL 0x00022200
/* CLK_DIV_TOP */
-#define CLK_DIV_TOP0_VAL 0x23712311
+#define CLK_DIV_TOP0_VAL 0x23713311
#define CLK_DIV_TOP1_VAL 0x13100B00
#define CLK_DIV_TOP2_VAL 0x11101100
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3699
-gerrit
commit a000656f779d8ff6a769eb821a1dd8263d4c4d81
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat Jun 22 19:43:40 2013 -0700
exynos5420: Fix the way the rate of the input clock for i2c buses is found.
The clock divider was being read from registers incorrectly which meant that
the periph rate was wrong.
Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/clock.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index e5ab001..8c4baf8 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -196,9 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
case PERIPH_ID_I2C9:
case PERIPH_ID_I2C10:
sclk = get_pll_clk(MPLL);
- sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1;
- div = (readl(&clk->clk_div_top0) & 0x7) + 1;
- return (sclk / sub_div) / div;
+ div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1;
+ return sclk / div;
default:
printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
return -1;