Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3749
-gerrit
commit 738e0b1d72c2d068c634a30bb934859238be0a02
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Fri Jun 21 20:11:47 2013 +0800
ec/google: Generalize communication protocol support in EC drivers.
Since EC protocol v3, the packet format will be the same for all buses (inclding
I2C, SPI, and LPC). That will simplify the implementation in each individual bus
driver source file.
To prepare for that, we will move the protocol part into crosec_proto.c:
crosec_command_proto, with bus driver in callback "crosec_io".
Change-Id: I9ccd19a57a182899dd1ef1cd90598679c1546295
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
src/ec/google/chromeec/Makefile.inc | 6 +++---
src/ec/google/chromeec/crosec_proto.c | 34 ++++++++++++++++++++++++++++++++++
src/ec/google/chromeec/ec.h | 9 +++++++++
3 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index 922c1fe..73b5b5e 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -1,9 +1,9 @@
-ramstage-y += ec.c
+ramstage-y += ec.c crosec_proto.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
-smm-y += ec.c
+smm-y += ec.c crosec_proto.c
smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
-romstage-y += ec.c
+romstage-y += ec.c crosec_proto.c
romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c
new file mode 100644
index 0000000..016de8d
--- /dev/null
+++ b/src/ec/google/chromeec/crosec_proto.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <stdint.h>
+#include <string.h>
+#include "ec.h"
+#include "ec_commands.h"
+#include "ec_message.h"
+
+int crosec_command_proto(struct chromeec_command *cec_command,
+ crosec_io_t crosec_io, void *context)
+{
+ // TODO(hungte) Add v3 protocol.
+ return -1;
+}
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 7679a8b..13e9f23 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -21,6 +21,8 @@
#ifndef _EC_GOOGLE_CHROMEEC_EC_H
#define _EC_GOOGLE_CHROMEEC_EC_H
+#include <stddef.h>
+#include <stdint.h>
#ifndef __PRE_RAM__
u32 google_chromeec_get_wake_mask(void);
@@ -60,6 +62,13 @@ struct chromeec_command {
* actual received size out */
};
+/* internal standard implementation for EC command protocols. */
+typedef int (*crosec_io_t)(uint8_t *write_bytes, size_t write_size,
+ uint8_t *read_bytes, size_t read_size,
+ void *context);
+int crosec_command_proto(struct chromeec_command *cec_command,
+ crosec_io_t crosec_io, void *context);
+
int google_chromeec_command(struct chromeec_command *cec_command);
#endif /* _EC_GOOGLE_CHROMEEC_EC_H */
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3748
-gerrit
commit 808f2f65e6eb2c68714356d2ef5bff963000afdc
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Jun 20 18:57:04 2013 +0800
ec/chromeec: Merge upstream V3 structure and constant definition.
Chrome EC protocol V3 has several new command structure and constants defined.
Simply cherry-picking changes from upstream.
Change-Id: I7cb61d3b632ff32743e4fa312e0cc691c1c4c663
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
src/ec/google/chromeec/ec_commands.h | 72 +++++++++++++++++++++++++++++++++++-
src/ec/google/chromeec/ec_message.h | 44 ++++++++++++++++++++++
2 files changed, 115 insertions(+), 1 deletion(-)
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index a2cc70c..d17bb44 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -28,6 +28,7 @@
*/
/* Current version of this protocol */
+/* TODO: This is effectively useless; protocol is determined in other ways */
#define EC_PROTO_VERSION 0x00000002
/* Command version mask */
@@ -44,7 +45,9 @@
/* I/O addresses for host command args and params */
#define EC_LPC_ADDR_HOST_ARGS 0x800 /* and 0x801, 0x802, 0x803 */
#define EC_LPC_ADDR_HOST_PARAM 0x804
-#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
+#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
+#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
+#define EC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
* and they tell the kernel that so we have to think of it as two parts. */
@@ -134,6 +137,8 @@
/* Host command interface flags */
/* Host command interface supports LPC args (LPC interface only) */
#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
+/* Host command interface supports version 3 protocol */
+#define EC_HOST_CMD_FLAG_VERSION_3 0x02
/* Wireless switch flags */
#define EC_WIRELESS_SWITCH_WLAN 0x01
@@ -194,6 +199,9 @@ enum ec_status {
EC_RES_UNAVAILABLE = 9, /* No response available */
EC_RES_TIMEOUT = 10, /* We got a timeout */
EC_RES_OVERFLOW = 11, /* Table / data overflow */
+ EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
+ EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
+ EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */
};
/*
@@ -275,6 +283,68 @@ struct ec_lpc_host_args {
*/
#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
+/*****************************************************************************/
+
+/*
+ * Value written to legacy command port / prefix byte to indicate protocol
+ * 3+ structs are being used. Usage is bus-dependent.
+ */
+#define EC_COMMAND_PROTOCOL_3 0xda
+
+#define EC_HOST_REQUEST_VERSION 3
+
+/* Version 3 request from host */
+struct ec_host_request {
+ /* Struct version (=3)
+ *
+ * EC will return EC_RES_INVALID_HEADER if it receives a header with a
+ * version it doesn't know how to parse.
+ */
+ uint8_t struct_version;
+
+ /*
+ * Checksum of request and data; sum of all bytes including checksum
+ * should total to 0.
+ */
+ uint8_t checksum;
+
+ /* Command code */
+ uint16_t command;
+
+ /* Command version */
+ uint8_t command_version;
+
+ /* Unused byte in current protocol version; set to 0 */
+ uint8_t reserved;
+
+ /* Length of data which follows this header */
+ uint16_t data_len;
+} __packed;
+
+#define EC_HOST_RESPONSE_VERSION 3
+
+/* Version 3 response from EC */
+struct ec_host_response {
+ /* Struct version (=3) */
+ uint8_t struct_version;
+
+ /*
+ * Checksum of response and data; sum of all bytes including checksum
+ * should total to 0.
+ */
+ uint8_t checksum;
+
+ /* Result code (EC_RES_*) */
+ uint16_t result;
+
+ /* Length of data which follows this header */
+ uint16_t data_len;
+
+ /* Unused bytes in current protocol version; set to 0 */
+ uint16_t reserved;
+} __packed;
+
+/*****************************************************************************/
/*
* Notes on commands:
*
diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h
new file mode 100644
index 0000000..a2421c7
--- /dev/null
+++ b/src/ec/google/chromeec/ec_message.h
@@ -0,0 +1,44 @@
+/*
+ * Chromium OS Matrix Keyboard Message Protocol definitions
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CROS_MESSAGE_H
+#define _CROS_MESSAGE_H
+
+/*
+ * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
+ *
+ * This is copied from the Chromium OS Open Source Embedded Controller code.
+ */
+enum {
+ /* The header byte, which follows the preamble */
+ MSG_HEADER = 0xec,
+
+ MSG_HEADER_BYTES = 3,
+ MSG_TRAILER_BYTES = 2,
+ MSG_PROTO_BYTES = MSG_HEADER_BYTES + MSG_TRAILER_BYTES,
+
+ /* Max length of messages */
+ MSG_BYTES = EC_HOST_PARAM_SIZE + MSG_PROTO_BYTES,
+};
+
+#endif
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3746
-gerrit
commit fbe1bd3017c2c57a3cd639b160c66eac2891dbc9
Author: Bill Richardson <wfrichar(a)chromium.org>
Date: Wed Jun 12 10:50:41 2013 -0700
ec: Reserve correct ioport regions for Chrome OS EC to use
The LPC-based ChromeOS EC uses several ioport regions to communicate with
the AP. In order for the new unified userspace access method to work, we
need them to be reserved by the BIOS.
Before /proc/ioports shows:
0800-0803
0804-08ff
We'd like just a single 256-byte region at 0x800, but ASL can't handle that.
So this will work:
0800-087f
0880-08ff
Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d
Signed-off-by: Bill Richardson <wfrichar(a)chromium.org>
---
src/ec/google/chromeec/acpi/superio.asl | 17 +++++------
src/ec/google/chromeec/ec_commands.h | 51 +++++++++++++++++++++++++++------
2 files changed, 52 insertions(+), 16 deletions(-)
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
index 4f71332..39ddd29 100644
--- a/src/ec/google/chromeec/acpi/superio.asl
+++ b/src/ec/google/chromeec/acpi/superio.asl
@@ -29,8 +29,9 @@
* SIO_EC_HOST_ENABLE : Enable EC host command interface resources
* EC_LPC_ADDR_HOST_DATA : EC host command interface data port
* EC_LPC_ADDR_HOST_CMD : EC host command interface command port
- * EC_LPC_ADDR_HOST_ARGS : EC host command arguments
- * EC_LPC_ADDR_HOST_PARAM : EC host command parameter buffer
+ * EC_HOST_CMD_REGION0 : EC host command buffer
+ * EC_HOST_CMD_REGION1 : EC host command buffer
+ * EC_HOST_CMD_REGION_SIZE : EC host command buffer size
*/
// Scope is \_SB.PCI0.LPCB
@@ -75,9 +76,8 @@ Device (SIO) {
{
FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
- FixedIO (EC_LPC_ADDR_HOST_ARGS, 4)
- FixedIO (EC_LPC_ADDR_HOST_PARAM,
- EC_HOST_PARAM_SIZE)
+ FixedIO (EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION_SIZE)
+ FixedIO (EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION_SIZE)
})
Name (_PRS, ResourceTemplate ()
@@ -85,9 +85,10 @@ Device (SIO) {
StartDependentFn (0, 0) {
FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
- FixedIO (EC_LPC_ADDR_HOST_ARGS, 4)
- FixedIO (EC_LPC_ADDR_HOST_PARAM,
- EC_HOST_PARAM_SIZE)
+ FixedIO (EC_HOST_CMD_REGION0,
+ EC_HOST_CMD_REGION_SIZE)
+ FixedIO (EC_HOST_CMD_REGION1,
+ EC_HOST_CMD_REGION_SIZE)
}
EndDependentFn ()
})
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 93258df..a2cc70c 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -42,10 +42,16 @@
#define EC_LPC_ADDR_HOST_CMD 0x204
/* I/O addresses for host command args and params */
-#define EC_LPC_ADDR_HOST_ARGS 0x800
+#define EC_LPC_ADDR_HOST_ARGS 0x800 /* and 0x801, 0x802, 0x803 */
#define EC_LPC_ADDR_HOST_PARAM 0x804
#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
+/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
+ * and they tell the kernel that so we have to think of it as two parts. */
+#define EC_HOST_CMD_REGION0 0x800
+#define EC_HOST_CMD_REGION1 0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
+
/* EC command register bit functions */
#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
@@ -726,15 +732,44 @@ enum lightbar_command {
/*****************************************************************************/
/* LED control commands */
-#define EC_CMD_LED_SET 0x29
+#define EC_CMD_LED_CONTROL 0x29
-#define EC_LED_FLAGS_AUTO (1 << 1)
+enum ec_led_id {
+ EC_LED_ID_BATTERY_LED = 0,
+ EC_LED_ID_POWER_BUTTON_LED,
+ EC_LED_ID_ADAPTER_LED,
+};
-struct ec_params_led_set {
- uint8_t r;
- uint8_t g;
- uint8_t b; /* Used as yellow if there is no blue LED */
- uint8_t flags;
+/* LED control flags */
+#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
+#define EC_LED_FLAGS_AUTO (1 << 1) /* Switch LED back to automatic control */
+
+enum ec_led_colors {
+ EC_LED_COLOR_RED = 0,
+ EC_LED_COLOR_GREEN,
+ EC_LED_COLOR_BLUE,
+ EC_LED_COLOR_YELLOW,
+ EC_LED_COLOR_WHITE,
+
+ EC_LED_COLOR_COUNT
+};
+
+struct ec_params_led_control {
+ uint8_t led_id; /* Which LED to control */
+ uint8_t flags; /* Control flags */
+
+ uint8_t brightness[EC_LED_COLOR_COUNT];
+} __packed;
+
+struct ec_response_led_control {
+ /*
+ * Available brightness value range.
+ *
+ * Range 0 means color channel not present.
+ * Range 1 means on/off control.
+ * Other values means the LED is control by PWM.
+ */
+ uint8_t brightness_range[EC_LED_COLOR_COUNT];
} __packed;
/*****************************************************************************/
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3745
-gerrit
commit 9522b5c49c91e816385a2f9c2b3dd5dac390af71
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jun 4 10:07:15 2013 -0700
slippy/falco/peppy: Enable SERIRQ continuous mode
The Chrome EC still does not tolerate SERIRQ in quiet mode
and so the keyboard does not work properly.
Change-Id: I9ab052187c9926ce0e2c86b86dfe987dd6564c1b
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 48b4ae9..1c4a7c0 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -1,5 +1,6 @@
config EC_GOOGLE_CHROMEEC
bool
+ select SERIRQ_CONTINUOUS_MODE
help
Google's Chrome EC
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3744
-gerrit
commit cb40e35fd688148bffe771e508e5509a4581eec7
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Jun 4 10:03:34 2013 -0700
ec: Add romstage function for checking and rebooting EC
Now that we are executing VbInit() in coreboot we can end up
in a situation where the recovery reason is consumed during
VbInit (end of romstage) and then the EC is rebooted to RO
during ramstage EC init, thereby losing the recovery reason.
Two possiblities are to remove the EC check+reboot from ramstage
and let it happen in depthcharge. This however means that the
system has to boot all the way into depthcharge and then reboot
the EC and the system again.
Instead if we do a check in romstage before VbInit() is called
then we can reboot the EC into RO early and avoid booting all
the way to depthcharge first.
This change adds a ramstage version the EC init function and
calls it from the shared romstage code immediately after the
PCH decode windows are setup.
Change-Id: I30d2a0c7131b8e4ec30c63eea36944ec111a8fba
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/cpu/intel/haswell/romstage.c | 8 ++++++++
src/ec/google/chromeec/ec.c | 39 +++++++++++++++++++++++++++++++++++++--
src/ec/google/chromeec/ec.h | 1 +
3 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 8196273..0cef888 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -38,6 +38,9 @@
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include <ec/google/chromeec/ec.h>
+#endif
#include "haswell.h"
#include "northbridge/intel/haswell/haswell.h"
#include "northbridge/intel/haswell/raminit.h"
@@ -216,6 +219,11 @@ void romstage_common(const struct romstage_params *params)
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
+#endif
+
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index d94338f..9b848c0 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -21,12 +21,12 @@
#include <console/console.h>
#include <arch/io.h>
#include <delay.h>
+#include <arch/hlt.h>
+#include <reset.h>
#ifndef __PRE_RAM__
#include <elog.h>
#include <stdlib.h>
#include <string.h>
-#include <reset.h>
-#include <arch/hlt.h>
#include "chip.h"
#endif
#include "ec.h"
@@ -99,6 +99,41 @@ u32 google_chromeec_get_events_b(void)
return google_chromeec_get_mask(EC_CMD_HOST_EVENT_GET_B);
}
+#ifndef __SMM__
+/* Check for recovery mode and ensure EC is in RO */
+void google_chromeec_early_init(void)
+{
+ struct chromeec_command cec_cmd;
+ struct ec_response_get_version cec_resp = {{0}};
+
+ cec_cmd.cmd_code = EC_CMD_GET_VERSION;
+ cec_cmd.cmd_version = 0;
+ cec_cmd.cmd_data_out = &cec_resp;
+ cec_cmd.cmd_size_in = 0;
+ cec_cmd.cmd_size_out = sizeof(cec_resp);
+ google_chromeec_command(&cec_cmd);
+
+ if (cec_cmd.cmd_code ||
+ (recovery_mode_enabled() &&
+ (cec_resp.current_image != EC_IMAGE_RO))) {
+ struct ec_params_reboot_ec reboot_ec;
+ /* Reboot the EC and make it come back in RO mode */
+ reboot_ec.cmd = EC_REBOOT_COLD;
+ reboot_ec.flags = 0;
+ cec_cmd.cmd_code = EC_CMD_REBOOT_EC;
+ cec_cmd.cmd_version = 0;
+ cec_cmd.cmd_data_in = &reboot_ec;
+ cec_cmd.cmd_size_in = sizeof(reboot_ec);
+ cec_cmd.cmd_size_out = 0; /* ignore response, if any */
+ printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
+ google_chromeec_command(&cec_cmd);
+ udelay(1000);
+ hard_reset();
+ hlt();
+ }
+}
+#endif /* ! __SMM__ */
+
#ifndef __PRE_RAM__
static int google_chromeec_set_mask(u8 type, u32 mask)
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 3eb555c..7679a8b 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -33,6 +33,7 @@ u16 google_chromeec_get_board_version(void);
void google_chromeec_init(void);
#endif
+void google_chromeec_early_init(void);
uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size);
u32 google_chromeec_get_events_b(void);
int google_chromeec_kbbacklight(int percent);
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3742
-gerrit
commit 622ee8ecb7112944be0b9b41adc909d3487836d4
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue May 21 07:49:11 2013 -0700
ec: Remove hardcoded GPI offset in EC SCI
With LynxPoint-LP the SCI GPE is no longer a GPIO
that is offset by 16. Remove the Add and fix up
the link definition so it is still accurate.
Change-Id: I091141183a09345b5ffe28365583e48019f9f5e5
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/ec/google/chromeec/acpi/ec.asl | 2 +-
src/mainboard/google/link/ec.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 2fb8e79..cb196a7 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -27,7 +27,7 @@ Device (EC0)
{
Name (_HID, EISAID ("PNP0C09"))
Name (_UID, 1)
- Name (_GPE, Add(EC_SCI_GPI, 16))
+ Name (_GPE, EC_SCI_GPI)
Name (TOFS, EC_TEMP_SENSOR_OFFSET)
Name (TNOP, 0xFD) // Thermal sensor has no power
Name (TBAD, 0xFE) // Thermal sensor bad reading
diff --git a/src/mainboard/google/link/ec.h b/src/mainboard/google/link/ec.h
index 6133f97..0044347 100644
--- a/src/mainboard/google/link/ec.h
+++ b/src/mainboard/google/link/ec.h
@@ -22,7 +22,7 @@
#include <ec/google/chromeec/ec_commands.h>
-#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */
+#define EC_SCI_GPI 23 /* GPIO7/GPE23 is EC_SCI# */
#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */
#define LINK_EC_SCI_EVENTS \
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3722
-gerrit
commit a8cc3f0c4773b852b51ec7b5d2e38e0ed85683b7
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 30 06:09:12 2013 -0700
pit: Enable the ps8625 driver.
Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig
index 20e0084..89ffb5b 100644
--- a/src/mainboard/google/pit/Kconfig
+++ b/src/mainboard/google/pit/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_INIT_TIMER
+ select DRIVER_PARADE_PS8625
config MAINBOARD_DIR
string