Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3757
-gerrit
commit 2b7927e57e588b0f26b662802729c4b928addf99
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Tue Jul 9 21:52:41 2013 -0600
ec: Fix spelling
Change-Id: I5e4d35572c43f07bec5ec0bcd75c717723228e2f
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/ec/compal/ene932/ec.c | 4 ++--
src/ec/google/chromeec/ec_commands.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c
index c3087e9..3f4d1b9 100644
--- a/src/ec/compal/ene932/ec.c
+++ b/src/ec/compal/ene932/ec.c
@@ -80,14 +80,14 @@ int kbc_cleanup_buffers(void)
}
-/* The ENE 60/64 EC registers are the same comand/status IB/OB KBC pair.
+/* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair.
* Check status from 64 port before each command.
*
* Ex. Get panel ID command C43/D77
* Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
* Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
* Check OBF set. Then Get Data(0x03:panel ID) from 0x60
- * Different commands return may or maynot respond and may have multiple
+ * Different commands return may or may not respond and may have multiple
* bytes. Keep it simple for nor
*/
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index c1b19bc..10a7402 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -255,7 +255,7 @@ struct ec_lpc_host_args {
* If EC gets a command and this flag is not set, this is an old-style command.
* Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with
* unknown length. EC must respond with an old-style response (that is,
- * withouth setting EC_HOST_ARGS_FLAG_TO_HOST).
+ * without setting EC_HOST_ARGS_FLAG_TO_HOST).
*/
#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
/*
@@ -748,7 +748,7 @@ struct ec_response_port80_last_boot {
/*****************************************************************************/
/* Thermal engine commands */
-/* Set thershold value */
+/* Set threshold value */
#define EC_CMD_THERMAL_SET_THRESHOLD 0x50
struct ec_params_thermal_set_threshold {
Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3756
-gerrit
commit c104578f27700c20d67b207ff226a73f4a91f0dd
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Tue Jul 9 21:51:14 2013 -0600
lib: Fix spelling
Change-Id: I999987af9cb44906e3c3135c0351a0cd6eb210ff
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/lib/cbmem.c | 4 ++--
src/lib/cbmem_console.c | 4 ++--
src/lib/compute_ip_checksum.c | 2 +-
src/lib/coreboot_table.c | 4 ++--
src/lib/fallback_boot.c | 2 +-
src/lib/gcov-io.h | 6 +++---
src/lib/libgcov.c | 2 +-
src/lib/lzma.c | 4 ++--
src/lib/memrange.c | 4 ++--
src/lib/ne2k.c | 2 +-
src/lib/rmodule.c | 2 +-
src/lib/selfboot.c | 2 +-
src/lib/usbdebug.c | 2 +-
13 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 3702da1..9e2ce0d 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -90,7 +90,7 @@ void cbmem_init(u64 baseaddr, u64 size)
for (;;) ;
}
- /* we don't need to call this in romstage, usefull only from ramstage */
+ /* we don't need to call this in romstage, useful only from ramstage */
#ifndef __PRE_RAM__
set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr);
#endif
@@ -205,7 +205,7 @@ void *cbmem_find(u32 id)
}
#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
-/* Returns True if it was not intialized before. */
+/* Returns True if it was not initialized before. */
int cbmem_initialize(void)
{
int rv = 0;
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index efb8e86..de452d7 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -24,7 +24,7 @@
/*
* Structure describing console buffer. It is overlaid on a flat memory area,
- * whith buffer_body covering the extent of the memory. Once the buffer is
+ * with buffer_body covering the extent of the memory. Once the buffer is
* full, the cursor keeps going but the data is dropped on the floor. This
* allows to tell how much data was lost in the process.
*/
@@ -138,7 +138,7 @@ void cbmemc_tx_byte(unsigned char data)
* the CBMEM console buffer contents.
*
* If there is overflow - add to the destination area a string, reporting the
- * overflow and the number of dropped charactes.
+ * overflow and the number of dropped characters.
*/
static void copy_console_buffer(struct cbmem_console *new_cons_p)
{
diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c
index 48f93d4..58a6bf1 100644
--- a/src/lib/compute_ip_checksum.c
+++ b/src/lib/compute_ip_checksum.c
@@ -40,7 +40,7 @@ unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned
new = ~new & 0xFFFF;
if (offset & 1) {
/* byte swap the sum if it came from an odd offset
- * since the computation is endian independant this
+ * since the computation is endian independent this
* works.
*/
new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index d25b59d..3fad4c7 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -399,7 +399,7 @@ static unsigned long lb_table_fini(struct lb_header *head)
/* Routines to extract part so the coreboot table or
* information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
- * implementaiton.
+ * implementation.
*/
static struct lb_memory *mem_ranges = NULL;
@@ -567,7 +567,7 @@ unsigned long write_coreboot_table(
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
- /* pass along the VDAT buffer adress */
+ /* pass along the VDAT buffer address */
lb_vdat(head);
/* pass along VBNV offsets in CMOS */
diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index ce1ba85..b956c94 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -8,7 +8,7 @@
static void set_boot_successful(void)
{
- /* Remember I succesfully booted by setting
+ /* Remember I successfully booted by setting
* the initial boot direction
* to the direction that I booted.
*/
diff --git a/src/lib/gcov-io.h b/src/lib/gcov-io.h
index 4502bd6..c5332ec 100644
--- a/src/lib/gcov-io.h
+++ b/src/lib/gcov-io.h
@@ -174,7 +174,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define BITS_PER_UNIT 8
#define LONG_LONG_TYPE_SIZE 64
-/* There are many gcc_assertions. Set the vaule to 1 if we want a warning
+/* There are many gcc_assertions. Set the value to 1 if we want a warning
message if the assertion fails. */
#ifndef ENABLE_ASSERT_CHECKING
#define ENABLE_ASSERT_CHECKING 1
@@ -335,7 +335,7 @@ typedef HOST_WIDEST_INT gcov_type;
/* Counters that are collected. */
#define GCOV_COUNTER_ARCS 0 /* Arc transitions. */
#define GCOV_COUNTERS_SUMMABLE 1 /* Counters which can be
- summaried. */
+ summed. */
#define GCOV_FIRST_VALUE_COUNTER 1 /* The first of counters used for value
profiling. They must form a consecutive
interval and their order must match
@@ -426,7 +426,7 @@ struct gcov_summary
struct gcov_ctr_summary ctrs[GCOV_COUNTERS_SUMMABLE];
};
-/* Structures embedded in coveraged program. The structures generated
+/* Structures embedded in coverage program. The structures generated
by write_profile must match these. */
#if IN_LIBGCOV
diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c
index 47a427f..f37d0d2 100644
--- a/src/lib/libgcov.c
+++ b/src/lib/libgcov.c
@@ -396,7 +396,7 @@ gcov_exit (void)
#endif
prefix_length = 0;
- /* If no prefix was specified and a prefix stip, then we assume
+ /* If no prefix was specified and a prefix strip, then we assume
relative. */
if (gcov_prefix_strip != 0 && prefix_length == 0)
{
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index cd60b3f..674a029 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -34,8 +34,8 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst)
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
/* The outSize in LZMA stream is a 64bit integer stored in little-endian
* (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by
- * unaligned memory address and to load in correct endianess, read each
- * byte and re-costruct. */
+ * unaligned memory address and to load in correct endianness, read each
+ * byte and re-construct. */
cp = src + LZMA_PROPERTIES_SIZE;
outSize = cp[3] << 24 | cp[2] << 16 | cp[1] << 8 | cp[0];
if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
diff --git a/src/lib/memrange.c b/src/lib/memrange.c
index 1a16ef7..af56e72 100644
--- a/src/lib/memrange.c
+++ b/src/lib/memrange.c
@@ -183,7 +183,7 @@ static void merge_add_memranges(struct memranges *ranges,
remove_memranges(ranges, begin, end, -1);
/* Find the entry to place the new entry after. Since
- * remove_memranges() was called above there is a guranteed
+ * remove_memranges() was called above there is a guaranteed
* spot for this new entry. */
for (cur = ranges->entries; cur != NULL; cur = cur->next) {
/* Found insertion spot before current entry. */
@@ -292,7 +292,7 @@ void memranges_fill_holes_up_to(struct memranges *ranges,
continue;
}
- /* If the previous entry does not directly preceed the current
+ /* If the previous entry does not directly precede the current
* entry then add a new entry just after the previous one. */
if (range_entry_end(prev) != cur->begin) {
resource_t end;
diff --git a/src/lib/ne2k.c b/src/lib/ne2k.c
index 31470fc..b678d79 100644
--- a/src/lib/ne2k.c
+++ b/src/lib/ne2k.c
@@ -132,7 +132,7 @@ static unsigned char eth_pio_read_byte(unsigned int src,
}
-/* varition of compute_ip_checksum which works on SRAM */
+/* Variation of compute_ip_checksum which works on SRAM */
unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned short length,
unsigned int eth_nic_base)
{
diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c
index b56ec32..462c7d7 100644
--- a/src/lib/rmodule.c
+++ b/src/lib/rmodule.c
@@ -232,7 +232,7 @@ int rmodule_load_alignment(const struct rmodule *module)
/* The load alignment is the start of the program's linked address.
* The base address where the program is loaded needs to be a multiple
* of the program's starting link address. That way all data alignment
- * in the program is presered. */
+ * in the program is preserved. */
return module->header->module_link_start_address;
}
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 4ebe109..2b69ac4 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -361,7 +361,7 @@ static int build_self_segment_list(
(void *)(intptr_t)ntohll(segment->load_addr));
*entry = ntohll(segment->load_addr);
/* Per definition, a payload always has the entry point
- * as last segment. Thus, we use the occurence of the
+ * as last segment. Thus, we use the occurrence of the
* entry point as break condition for the loop.
* Can we actually just look at the number of section?
*/
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index 200121f..e425fbf 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -333,7 +333,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
if (!(portsc & PORT_CONNECT))
return -1; //-ENOTCONN;
- /* bomb out completely if something weird happend */
+ /* bomb out completely if something weird happened */
if ((portsc & PORT_CSC))
return -2; //-EINVAL;
Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3755
-gerrit
commit f3c8b013376431880e983adb40b2613e34b62ba3
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Tue Jul 9 21:46:01 2013 -0600
include: Fix spelling
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/include/boot/coreboot_tables.h | 6 +++---
src/include/boot/elf_boot.h | 4 ++--
src/include/bootstate.h | 2 +-
src/include/cbfs_core.h | 2 +-
src/include/cbmem.h | 4 ++--
src/include/console/console.h | 2 +-
src/include/console/post_codes.h | 10 +++++-----
src/include/cpu/amd/amdfam10_sysconf.h | 2 +-
src/include/cpu/amd/amdk8_sysconf.h | 2 +-
src/include/cpu/amd/gx2def.h | 12 ++++++------
src/include/cpu/amd/lxdef.h | 12 ++++++------
src/include/cpu/x86/mtrr.h | 4 ++--
src/include/cpu/x86/smm.h | 4 ++--
src/include/device/dram/ddr3.h | 2 +-
src/include/device/pci_def.h | 6 +++---
src/include/ehci.h | 2 +-
src/include/gpio.h | 2 +-
src/include/pc80/mc146818rtc.h | 2 +-
src/include/rmodule.h | 6 +++---
src/include/romstage_handoff.h | 6 +++---
src/include/swab.h | 2 +-
src/include/thread.h | 4 ++--
src/include/timer.h | 6 +++---
src/include/uart8250.h | 2 +-
24 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index ee1c29f..87819ce 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -6,11 +6,11 @@
/* The coreboot table information is for conveying information
* from the firmware to the loaded OS image. Primarily this
* is expected to be information that cannot be discovered by
- * other means, such as quering the hardware directly.
+ * other means, such as querying the hardware directly.
*
* All of the information should be Position Independent Data.
* That is it should be safe to relocated any of the information
- * without it's meaning/correctnes changing. For table that
+ * without it's meaning/correctness changing. For table that
* can reasonably be used on multiple architectures the data
* size should be fixed. This should ease the transition between
* 32 bit and 64 bit architectures etc.
@@ -27,7 +27,7 @@
* table entry is required or not. This should remove much of the
* long term compatibility burden as table entries which are
* irrelevant or have been replaced by better alternatives may be
- * dropped. Of course it is polite and expidite to include extra
+ * dropped. Of course it is polite and expedite to include extra
* table entries and be backwards compatible, but it is not required.
*/
diff --git a/src/include/boot/elf_boot.h b/src/include/boot/elf_boot.h
index b119bab..89772a8 100644
--- a/src/include/boot/elf_boot.h
+++ b/src/include/boot/elf_boot.h
@@ -10,7 +10,7 @@
*
* All of the information must be Position Independent Data.
* That is it must be safe to relocate the whole ELF boot parameter
- * block without changing the meaning or correctnes of the data.
+ * block without changing the meaning or correctness of the data.
* Additionally it must be safe to permute the order of the ELF notes
* to any possible permutation without changing the meaning or correctness
* of the data.
@@ -51,7 +51,7 @@ typedef struct
#define EBN_BOOTLOADER_NAME 0x00000002
/* This specifies just the name of the bootloader for easy comparison */
#define EBN_BOOTLOADER_VERSION 0x00000003
-/* This specifies the version of the bootlader */
+/* This specifies the version of the bootloader */
#define EBN_COMMAND_LINE 0x00000004
/* This specifies a command line that can be set by user interaction,
* and is provided as a free form string to the loaded image.
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 40822a7..23398a2 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -148,7 +148,7 @@ struct boot_state_callback {
bscb_->arg = arg_
/* The following 2 functions schedule a callback to be called on entry/exit
- * to a given state. Note that thare are no ordering guarantees between the
+ * to a given state. Note that there are no ordering guarantees between the
* individual callbacks on a given state. 0 is returned on success < 0 on
* error. */
int boot_state_sched_on_entry(struct boot_state_callback *bscb,
diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index 20636e2..54e2f60 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -56,7 +56,7 @@
#include <stdint.h>
/** These are standard values for the known compression
- alogrithms that coreboot knows about for stages and
+ algorithms that coreboot knows about for stages and
payloads. Of course, other CBFS users can use whatever
values they want, as long as they understand them. */
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index efb0f90..982a6d8 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -86,7 +86,7 @@ struct cbmem_entry;
* implemented by the board or chipset to define the upper address where
* cbmem lives. This address is required to be a 32-bit address. Additionally,
* the address needs to be consistent in both romstage and ramstage. The
- * dynamic cbmem infrasturue allocates new regions below the last allocated
+ * dynamic cbmem infrastructure allocates new regions below the last allocated
* region. Regions are defined by a cbmem_entry struct that is opaque. Regions
* may be removed, but the last one added is the only that can be removed.
*
@@ -100,7 +100,7 @@ struct cbmem_entry;
#define DYN_CBMEM_ALIGN_SIZE (4096)
-/* Initialze cbmem to be empty. */
+/* Initialize cbmem to be empty. */
void cbmem_initialize_empty(void);
/* Return the top address for dynamic cbmem. The address returned needs to
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 9112f35..7faa873 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -60,7 +60,7 @@ extern struct console_driver econsole_drivers[];
extern int console_loglevel;
#else
/* __PRE_RAM__ */
-/* Using a global varible can cause problems when we reset the stack
+/* Using a global variable can cause problems when we reset the stack
* from cache as ram to ram. If we make this a define USE_SHARED_STACK
* we could use the same code on all architectures.
*/
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index f66d276..a0dd694 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -24,7 +24,7 @@
* This aims to be a central point for POST codes used throughout coreboot.
* All POST codes should be declared here as macros, and post_code() should
* be used with the macros instead of hardcoded values. This allows us to
- * quicly reference POST codes when nothing is working
+ * quickly reference POST codes when nothing is working
*
* The format for a POST code macro is
* #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED
@@ -93,7 +93,7 @@
* \brief Entry into coreboot in hardwaremain (RAM)
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has succesfully loaded and started executing.
+ * ramstage has successfully loaded and started executing.
*/
#define POST_ENTRY_RAMSTAGE 0x80
@@ -107,7 +107,7 @@
/**
* \brief Console boot message succeeded
*
- * First console message has been succesfully sent through the console backend
+ * First console message has been successfully sent through the console backend
* driver.
*/
#define POST_CONSOLE_BOOT_MSG 0x40
@@ -129,7 +129,7 @@
/**
* \brief Devices have been configured
*
- * Device confgration has completed.
+ * Device configuration has completed.
*/
#define POST_DEVICE_CONFIGURATION_COMPLETE 0x88
@@ -207,7 +207,7 @@
/*
* The following POST codes are taken from src/include/cpu/amd/geode_post_code.h
* They overlap with previous codes, and most are not even used
- * Some maiboards still require them, but they are deprecated. We want to consolidate
+ * Some mainboards still require them, but they are deprecated. We want to consolidate
* our own POST code structure with the codes above.
*
* standard AMD post definitions for the AMD Geode
diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h
index 2f08fd8..baba6ce 100644
--- a/src/include/cpu/amd/amdfam10_sysconf.h
+++ b/src/include/cpu/amd/amdfam10_sysconf.h
@@ -64,7 +64,7 @@ struct amdfam10_sysconf_t {
unsigned lift_bsp_apicid;
int apicid_offset;
- void *mb; // pointer for mb releated struct
+ void *mb; // pointer for mb related struct
};
diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h
index 3ae35fd..87bd4d5 100644
--- a/src/include/cpu/amd/amdk8_sysconf.h
+++ b/src/include/cpu/amd/amdk8_sysconf.h
@@ -19,7 +19,7 @@ struct amdk8_sysconf_t {
unsigned lift_bsp_apicid;
int apicid_offset;
- void *mb; // pointer for mb releated struct
+ void *mb; // pointer for mb related struct
};
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index ee55c2f..beb4c65 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -399,12 +399,12 @@
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
#define BMIO 6 /* Base Mask IO */
#define SCIO 7 /* Swiss 0xCeese IO */
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
-#define BMO_SMM 10 /* Specail marker for SMM */
-#define BM_SMM 11 /* Specail marker for SMM */
-#define BMO_DMM 12 /* Specail marker for DMM */
-#define BM_DMM 13 /* Specail marker for DMM */
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */
+#define BMO_SMM 10 /* Special marker for SMM */
+#define BM_SMM 11 /* Special marker for SMM */
+#define BMO_DMM 12 /* Special marker for DMM */
+#define BM_DMM 13 /* Special marker for DMM */
#define RO_FB 14 /* special for Frame buffer. */
#define R_FB 15 /* special for FB. */
#define OTHER 0x0FE /* Special marker for other */
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 4eee156..da26895 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -533,12 +533,12 @@
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
#define BMIO 6 /* Base Mask IO*/
#define SCIO 7 /* Swiss 0xCeese IO*/
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/
-#define BMO_SMM 10 /* Specail marker for SMM*/
-#define BM_SMM 11 /* Specail marker for SMM*/
-#define BMO_DMM 12 /* Specail marker for DMM*/
-#define BM_DMM 13 /* Specail marker for DMM*/
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/
+#define BMO_SMM 10 /* Special marker for SMM*/
+#define BM_SMM 11 /* Special marker for SMM*/
+#define BMO_DMM 12 /* Special marker for DMM*/
+#define BM_DMM 13 /* Special marker for DMM*/
#define RO_FB 14 /* special for Frame buffer.*/
#define R_FB 15 /* special for FB.*/
#define OTHER 0x0FE /* Special marker for other*/
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 38c3f7c..017a77e 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -47,14 +47,14 @@
* x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
* of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
* want to call the components of x86_setup_mtrrs() because of other
- * rquirements the ordering should still preserved.
+ * requirements the ordering should still preserved.
* 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
* of the nature of the global MTRR enable flag. Therefore, all direct
* or indirect callers of enable_fixed_mtrr() should ensure that the
* variable MTRR MSRs do not contain bad ranges.
* 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
* the caching of the ROM. However, it is set to uncacheable (UC). It
- * is the responsiblity of the caller to enable it by calling
+ * is the responsibility of the caller to enable it by calling
* x86_mtrr_enable_rom_caching().
*/
void x86_setup_mtrrs(void);
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index df7e3de..cacbff0 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -423,7 +423,7 @@ struct smm_runtime {
u32 save_state_size;
/* The apic_id_to_cpu provides a mapping from APIC id to cpu number.
* The cpu number is indicated by the index into the array by matching
- * the deafult APIC id and value at the index. The stub loader
+ * the default APIC id and value at the index. The stub loader
* initializes this array with a 1:1 mapping. If the APIC ids are not
* contiguous like the 1:1 mapping it is up to the caller of the stub
* loader to adjust this mapping. */
@@ -446,7 +446,7 @@ void *smm_get_save_state(int cpu);
#else
/* SMM Module Loading API */
-/* Ths smm_loader_params structure provides direction to the SMM loader:
+/* The smm_loader_params structure provides direction to the SMM loader:
* - stack_top - optional external stack provided to loader. It must be at
* least per_cpu_stack_size * num_concurrent_stacks in size.
* - per_cpu_stack_size - stack size per cpu for smm modules.
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 69c072b..53a42ee 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -63,7 +63,7 @@
/*
* Module type (byte 3, bits 3:0) of SPD
- * This definition is specific to DDR3. DDR2 SPDs have a diferent structure.
+ * This definition is specific to DDR3. DDR2 SPDs have a different structure.
*/
enum spd_dimm_type {
SPD_DIMM_TYPE_UNDEFINED = 0x00,
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 58a7321..ac20659 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -177,7 +177,7 @@
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
-#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
+#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCIX */
#define PCI_CAP_ID_HT 0x08 /* Hypertransport */
@@ -208,7 +208,7 @@
#define PCI_PM_PMC 2 /* PM Capabilities Register */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
-#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
+#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
@@ -255,7 +255,7 @@
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
-/* Message Signalled Interrupts registers */
+/* Message Signaled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
diff --git a/src/include/ehci.h b/src/include/ehci.h
index b096f42..f920352 100644
--- a/src/include/ehci.h
+++ b/src/include/ehci.h
@@ -161,7 +161,7 @@ struct ehci_regs {
#define USBMODE_CM_IDLE (0<<0) /* idle state */
/* Moorestown has some non-standard registers, partially due to the fact that
- * its EHCI controller has both TT and LPM support. HOSTPCx are extentions to
+ * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
* PORTSCx
*/
#define HOSTPC0 0x84 /* HOSTPC extension */
diff --git a/src/include/gpio.h b/src/include/gpio.h
index f602b1e..3311fd6 100644
--- a/src/include/gpio.h
+++ b/src/include/gpio.h
@@ -57,7 +57,7 @@ enum gpio_types {
enum mvl3 {
LOGIC_0,
LOGIC_1,
- LOGIC_Z, /* high impedence / tri-stated / floating */
+ LOGIC_Z, /* high impedance / tri-stated / floating */
};
#endif /* GPIO_H */
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 29e0348..170a433 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -22,7 +22,7 @@
/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
- * totalling to a max high interval of 2.228 ms.
+ * totaling to a max high interval of 2.228 ms.
*/
# define RTC_UIP 0x80
# define RTC_DIV_CTL 0x70
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index 35a82c1..247711a 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -95,18 +95,18 @@ struct rmodule_header {
u32 relocations_begin_offset;
u32 relocations_end_offset;
/* The starting address of the linked program. This address is vital
- * for determining relocation offsets as the reloction info and other
+ * for determining relocation offsets as the relocation info and other
* symbols (bss, entry point) need this value as a basis to calculate
* the offsets.
*/
u32 module_link_start_address;
/* The module_program_size is the size of memory used while running
- * the program. The program is assumed to consume a contiguos amount
+ * the program. The program is assumed to consume a contiguous amount
* of memory. */
u32 module_program_size;
/* This is program's execution entry point. */
u32 module_entry_point;
- /* Optional paramter structure that can be used to pass data into
+ /* Optional parameter structure that can be used to pass data into
* the module. */
u32 parameters_begin;
u32 parameters_end;
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index 3152fb2..699838a 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -23,12 +23,12 @@
#include <string.h>
#include <cbmem.h>
-/* It is the chipset's responsbility for maintaining the integrity of this
+/* It is the chipset's responsibility for maintaining the integrity of this
* structure in CBMEM. For instance, if chipset code adds this structure
* using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber
* fields it doesn't own. */
struct romstage_handoff {
- /* Inidicate if the current boot is an S3 resume. If
+ /* Indicate if the current boot is an S3 resume. If
* CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
* responsible for initializing this variable. Otherwise, ramstage
* will be re-loaded from cbfs (which can be slower since it lives
@@ -42,7 +42,7 @@ struct romstage_handoff {
#if defined(__PRE_RAM__)
/* The romstage_handoff_find_or_add() function provides the necessary logic
- * for initializng the romstage_handoff structure in cbmem. Different components
+ * for initializing the romstage_handoff structure in cbmem. Different components
* of the romstage may be responsible for setting up different fields. Therefore
* that same logic flow should be used for allocating and initializing the
* structure. A newly allocated structure will be memset to 0. */
diff --git a/src/include/swab.h b/src/include/swab.h
index c5e4370..8a7daba 100644
--- a/src/include/swab.h
+++ b/src/include/swab.h
@@ -10,7 +10,7 @@
* separated swab functions from cpu_to_XX,
* to clean up support for bizarre-endian architectures.
*
- * See asm-i386/byteorder.h and suches for examples of how to provide
+ * See asm-i386/byteorder.h and such for examples of how to provide
* architecture-dependent optimized versions
*
*/
diff --git a/src/include/thread.h b/src/include/thread.h
index 148c448..0522337 100644
--- a/src/include/thread.h
+++ b/src/include/thread.h
@@ -43,7 +43,7 @@ void threads_initialize(void);
* current state in the boot state machine until it is complete. */
int thread_run(void (*func)(void *), void *arg);
/* thread_run_until is the same as thread_run() except that it blocks state
- * transitions from occuring in the (state, seq) pair of the boot state
+ * transitions from occurring in the (state, seq) pair of the boot state
* machine. */
int thread_run_until(void (*func)(void *), void *arg,
boot_state_t state, boot_state_sequence_t seq);
@@ -52,7 +52,7 @@ int thread_run_until(void (*func)(void *), void *arg,
int thread_yield_microseconds(unsigned microsecs);
/* Allow and prevent thread cooperation on current running thread. By default
- * all threads are marked to be cooperative. That means a thread can yeild
+ * all threads are marked to be cooperative. That means a thread can yield
* to another thread at a pre-determined switch point. Current there is
* only a single place where switching may occur: a call to udelay(). */
void thread_cooperate(void);
diff --git a/src/include/timer.h b/src/include/timer.h
index 40ac367..06128ce 100644
--- a/src/include/timer.h
+++ b/src/include/timer.h
@@ -67,13 +67,13 @@ int timers_run(void);
* 0 returned on success, < 0 on error. */
int timer_sched_callback(struct timeout_callback *tocb, unsigned long us);
-/* Add microseconds to an absoute time. */
+/* Add microseconds to an absolute time. */
static inline void mono_time_add_usecs(struct mono_time *mt, long us)
{
mt->microseconds += us;
}
-/* Add milliseconds to an absoute time. */
+/* Add milliseconds to an absolute time. */
static inline void mono_time_add_msecs(struct mono_time *mt, long ms)
{
mono_time_add_usecs(mt, ms * USECS_PER_MSEC);
@@ -85,7 +85,7 @@ static inline void mono_time_add_rela_time(struct mono_time *mt,
mono_time_add_usecs(mt, t->microseconds);
}
-/* Compare two absoluted times: Return -1, 0, or 1 if t1 is <, =, or > t2,
+/* Compare two absolute times: Return -1, 0, or 1 if t1 is <, =, or > t2,
* respectively. */
static inline int mono_time_cmp(const struct mono_time *t1,
const struct mono_time *t2)
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index d42e822..e6a318a 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -63,7 +63,7 @@
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define UART_LCR_PEN 0x08 /* Parity eneble */
+#define UART_LCR_PEN 0x08 /* Parity enable */
#define UART_LCR_EPS 0x10 /* Even Parity Select */
#define UART_LCR_STKP 0x20 /* Stick Parity */
#define UART_LCR_SBRK 0x40 /* Set Break */
Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3754
-gerrit
commit 9206cc594f41bec2ce04f7e4bb05a0d874358085
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Tue Jul 9 21:39:46 2013 -0600
drivers: Fix spelling
Change-Id: Ib0d98e3ab5b2943c36f88765587e8963a4f49604
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/drivers/ati/ragexl/mach64.h | 4 ++--
src/drivers/elog/elog.c | 2 +-
src/drivers/elog/gsmi.c | 2 +-
src/drivers/i2c/w83795/w83795.c | 4 ++--
src/drivers/i2c/w83795/w83795.h | 4 ++--
src/drivers/oxford/oxpcie/oxpcie_early.c | 2 +-
src/drivers/pc80/i8259.c | 2 +-
src/drivers/pc80/mc146818rtc.c | 2 +-
src/drivers/pc80/tpm.c | 2 +-
9 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h
index e0dae0d..3acbef4 100644
--- a/src/drivers/ati/ragexl/mach64.h
+++ b/src/drivers/ati/ragexl/mach64.h
@@ -1045,7 +1045,7 @@
#define SCISSOR_TOP_FLAG 0x40
#define SCISSOR_BOTTOM_FLAG 0x80
-/* ATI VGA Extended Regsiters */
+/* ATI VGA Extended Registers */
#define sioATIEXT 0x1ce
#define bioATIEXT 0x3ce
@@ -1057,7 +1057,7 @@
#define VGAGRA 0x3ce
#define GRA06 0x06
-/* VGA Seququencer Registers */
+/* VGA Sequencer Registers */
#define VGASEQ 0x3c4
#define SEQ02 0x02
#define SEQ04 0x04
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
index 71e908b..6e89b5f 100644
--- a/src/drivers/elog/elog.c
+++ b/src/drivers/elog/elog.c
@@ -629,7 +629,7 @@ static int elog_flash_area_bootstrap(void)
/*
* Shrink the log, deleting old entries and moving the
- * remining ones to the front of the log.
+ * remaining ones to the front of the log.
*/
static int elog_shrink(void)
{
diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c
index dac1af4..b8bc253 100644
--- a/src/drivers/elog/gsmi.c
+++ b/src/drivers/elog/gsmi.c
@@ -96,7 +96,7 @@ u32 gsmi_exec(u8 command, u32 *param)
break;
case GSMI_CMD_CLEAR_EVENT_LOG:
- /* Get paramter buffer even though we don't use it */
+ /* Get parameter buffer even though we don't use it */
cel = (struct gsmi_clear_eventlog_param *)(*param);
if (!cel)
break;
diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c
index d2bd348..9c51fff 100644
--- a/src/drivers/i2c/w83795/w83795.c
+++ b/src/drivers/i2c/w83795/w83795.c
@@ -77,7 +77,7 @@ static void w83795_dts_enable(u8 dts_src)
/* store bank3 regs first before enable DTS */
/*
- * TD/TR1-4 termal diode by default
+ * TD/TR1-4 thermal diode by default
* 0x00 Disable
* 0x01 thermistors on motherboard
* 0x10 different mode voltage
@@ -169,7 +169,7 @@ static void w83795_set_fan(w83795_fan_mode_t mode)
//SFIV TODO
}
- /* Set Hystersis of Temperature (HT) */
+ /* Set Hysteresis of Temperature (HT) */
//TODO
}
diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h
index f8d5164..e18cd28 100644
--- a/src/drivers/i2c/w83795/w83795.h
+++ b/src/drivers/i2c/w83795/w83795.h
@@ -38,9 +38,9 @@
#define DTS_SRC_AMD_SBTSI (1 << 0)
#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */
-#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */
+#define W83795_REG_TTTI(n) (0x260 + (n)) /* Target temperature W83795G/ADG will try to tune the fan output to keep */
#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */
-#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */
+#define W83795_REG_HT(n) (0x270 + (n)) /* Hysteresis of Temperature */
#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */
#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 9899619..2bca5c7 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -64,7 +64,7 @@ void oxford_init(void)
CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
/* Memory window for the OXPCIe952 card */
- // XXX is the calculation of base and limit corect?
+ // XXX is the calculation of base and limit correct?
pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
diff --git a/src/drivers/pc80/i8259.c b/src/drivers/pc80/i8259.c
index 78880c9..6f97c56 100644
--- a/src/drivers/pc80/i8259.c
+++ b/src/drivers/pc80/i8259.c
@@ -94,7 +94,7 @@ void setup_i8259(void)
/* Now clear the interrupts through OCW1.
* First we mask off all interrupts on the slave interrupt controller
* then we mask off all interrupts but interrupt 2 on the master
- * controller. This way the cascading stays alife.
+ * controller. This way the cascading stays alive.
*/
outb(ALL_IRQS, SLAVE_PIC_OCW1);
outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index d91f207..be52454 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -132,7 +132,7 @@ void rtc_init(int invalid)
/*
* Avoid clearing pending interrupts in the resume path because
* the Linux kernel relies on this to know if it should restart
- * the RTC timerqueue if the wake was due to the RTC alarm.
+ * the RTC timer queue if the wake was due to the RTC alarm.
*/
if (acpi_slp_type == 3)
return;
diff --git a/src/drivers/pc80/tpm.c b/src/drivers/pc80/tpm.c
index 9a4fc09..aeae3a0 100644
--- a/src/drivers/pc80/tpm.c
+++ b/src/drivers/pc80/tpm.c
@@ -565,7 +565,7 @@ int tis_open(void)
/*
* tis_close()
*
- * terminate the currect session with the TPM by releasing the locked
+ * terminate the correct session with the TPM by releasing the locked
* locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
* removal did not succeed).
*/
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3753
-gerrit
commit 2f593fcf00e5ed59f6034c46dfd670256c0d7631
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 30 05:56:26 2013 -0700
parade: Add a driver for the parade ps8625.
This driver is basically the same as the one in U-Boot but without the device
tree stuff. That driver is, in turn, a straightforward implementation of the
sequence of register writes described in the data sheet. Comments were added
in U-Boot which helpfully describe what the register writes are actually
doing and are kept.
Change-Id: I64ba6b373478853bb2120f0553a43de901170d02
Signed-off-by: Gabe Black <gabeblack(a)google.com>
---
src/drivers/Kconfig | 1 +
src/drivers/Makefile.inc | 1 +
src/drivers/parade/Kconfig | 20 ++++
src/drivers/parade/Makefile.inc | 20 ++++
src/drivers/parade/ps8625/Kconfig | 24 +++++
src/drivers/parade/ps8625/Makefile.inc | 20 ++++
src/drivers/parade/ps8625/ps8625.c | 161 +++++++++++++++++++++++++++++++++
src/drivers/parade/ps8625/ps8625.h | 25 +++++
8 files changed, 272 insertions(+)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 386508a..c4378b1 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -27,6 +27,7 @@ source src/drivers/ics/Kconfig
source src/drivers/ipmi/Kconfig
source src/drivers/maxim/Kconfig
source src/drivers/oxford/Kconfig
+source src/drivers/parade/Kconfig
if PC80_SYSTEM
source src/drivers/pc80/Kconfig
endif
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index f4fe146..9a1be72 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -24,6 +24,7 @@ subdirs-y += generic
subdirs-y += i2c
subdirs-y += maxim
subdirs-y += oxford
+subdirs-y += parade
subdirs-y += realtek
subdirs-y += sil
subdirs-y += trident
diff --git a/src/drivers/parade/Kconfig b/src/drivers/parade/Kconfig
new file mode 100644
index 0000000..b4b2ac2
--- /dev/null
+++ b/src/drivers/parade/Kconfig
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+source src/drivers/parade/ps8625/Kconfig
diff --git a/src/drivers/parade/Makefile.inc b/src/drivers/parade/Makefile.inc
new file mode 100644
index 0000000..efbd11d
--- /dev/null
+++ b/src/drivers/parade/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-$(CONFIG_DRIVER_PARADE_PS8625) += ps8625/
diff --git a/src/drivers/parade/ps8625/Kconfig b/src/drivers/parade/ps8625/Kconfig
new file mode 100644
index 0000000..41aa92b
--- /dev/null
+++ b/src/drivers/parade/ps8625/Kconfig
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config DRIVER_PARADE_PS8625
+ bool
+ default n
+ help
+ Parade ps8625 display port to lvds bridge
diff --git a/src/drivers/parade/ps8625/Makefile.inc b/src/drivers/parade/ps8625/Makefile.inc
new file mode 100644
index 0000000..ef546ba
--- /dev/null
+++ b/src/drivers/parade/ps8625/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-$(CONFIG_DRIVER_PARADE_PS8625) += ps8625.c
diff --git a/src/drivers/parade/ps8625/ps8625.c b/src/drivers/parade/ps8625/ps8625.c
new file mode 100644
index 0000000..6cbe3b7
--- /dev/null
+++ b/src/drivers/parade/ps8625/ps8625.c
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "ps8625.h"
+
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+struct parade_write {
+ uint8_t offset;
+ uint8_t reg;
+ uint8_t val;
+};
+
+static const struct parade_write parade_writes[] = {
+ { 0x02, 0xa1, 0x01 }, /* HPD low */
+ /*
+ * SW setting
+ * [1:0] SW output 1.2V voltage is lower to 96%
+ */
+ { 0x04, 0x14, 0x01 },
+ /*
+ * RCO SS setting
+ * [5:4] = b01 0.5%, b10 1%, b11 1.5%
+ */
+ { 0x04, 0xe3, 0x20 },
+ { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
+ /*
+ * RPHY Setting
+ * [3:2] CDR tune wait cycle before
+ * measure for fine tune b00: 1us,
+ * 01: 0.5us, 10:2us, 11:4us.
+ */
+ { 0x04, 0x8a, 0x0c },
+ { 0x04, 0x89, 0x08 }, /* [3] RFD always on */
+ /*
+ * CTN lock in/out:
+ * 20000ppm/80000ppm. Lock out 2
+ * times.
+ */
+ { 0x04, 0x71, 0x2d },
+ /*
+ * 2.7G CDR settings
+ * NOF=40LSB for HBR CDR setting
+ */
+ { 0x04, 0x7d, 0x07 },
+ { 0x04, 0x7b, 0x00 }, /* [1:0] Fmin=+4bands */
+ { 0x04, 0x7a, 0xfd }, /* [7:5] DCO_FTRNG=+-40% */
+ /*
+ * 1.62G CDR settings
+ * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+ */
+ { 0x04, 0xc0, 0x12 },
+ { 0x04, 0xc1, 0x92 }, /* Gitune=-37% */
+ { 0x04, 0xc2, 0x1c }, /* Fbstep=100% */
+ { 0x04, 0x32, 0x80 }, /* [7] LOS signal disable */
+ /*
+ * RPIO Setting
+ * [7:4] LVDS driver bias current :
+ * 75% (250mV swing)
+ */
+ { 0x04, 0x00, 0xb0 },
+ /*
+ * [7:6] Right-bar GPIO output strength is 8mA
+ */
+ { 0x04, 0x15, 0x40 },
+ /* EQ Training State Machine Setting */
+ { 0x04, 0x54, 0x10 }, /* RCO calibration start */
+ /* [4:0] MAX_LANE_COUNT set to one lane */
+ { 0x01, 0x02, 0x81 },
+ /* [4:0] LANE_COUNT_SET set to one lane */
+ { 0x01, 0x21, 0x81 },
+ { 0x00, 0x52, 0x20 },
+ { 0x00, 0xf1, 0x03 }, /* HPD CP toggle enable */
+ { 0x00, 0x62, 0x41 },
+ /* Counter number, add 1ms counter delay */
+ { 0x00, 0xf6, 0x01 },
+ /*
+ * [6]PWM function control by
+ * DPCD0040f[7], default is PWM
+ * block always works.
+ */
+ { 0x00, 0x77, 0x06 },
+ /*
+ * 04h Adjust VTotal tolerance to
+ * fix the 30Hz no display issue
+ */
+ { 0x00, 0x4c, 0x04 },
+ /* DPCD00400='h00, Parade OUI = 'h001cf8 */
+ { 0x01, 0xc0, 0x00 },
+ { 0x01, 0xc1, 0x1c }, /* DPCD00401='h1c */
+ { 0x01, 0xc2, 0xf8 }, /* DPCD00402='hf8 */
+ /*
+ * DPCD403~408 = ASCII code
+ * D2SLV5='h4432534c5635
+ */
+ { 0x01, 0xc3, 0x44 },
+ { 0x01, 0xc4, 0x32 }, /* DPCD404 */
+ { 0x01, 0xc5, 0x53 }, /* DPCD405 */
+ { 0x01, 0xc6, 0x4c }, /* DPCD406 */
+ { 0x01, 0xc7, 0x56 }, /* DPCD407 */
+ { 0x01, 0xc8, 0x35 }, /* DPCD408 */
+ /*
+ * DPCD40A, Initial Code major revision
+ * '01'
+ */
+ { 0x01, 0xca, 0x01 },
+ /* DPCD40B, Initial Code minor revision '05' */
+ { 0x01, 0xcb, 0x05 },
+ /* DPCD720, Select internal PWM */
+ { 0x01, 0xa5, 0xa0 },
+ /*
+ * FFh for 100% PWM of brightness, 0h for 0%
+ * brightness
+ */
+ { 0x01, 0xa7, 0xff },
+ /*
+ * Set LVDS output as 6bit-VESA mapping,
+ * single LVDS channel
+ */
+ { 0x01, 0xcc, 0x13 },
+ /* Enable SSC set by register */
+ { 0x02, 0xb1, 0x20 },
+ /*
+ * Set SSC enabled and +/-1% central
+ * spreading
+ */
+ { 0x04, 0x10, 0x16 },
+ /* MPU Clock source: LC => RCO */
+ { 0x04, 0x59, 0x60 },
+ { 0x04, 0x54, 0x14 }, /* LC -> RCO */
+ { 0x02, 0xa1, 0x91 } /* HPD high */
+};
+
+void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(parade_writes); i++) {
+ const struct parade_write *w = ¶de_writes[i];
+ i2c_write(bus, chip_base + w->offset, w->reg, sizeof(w->reg),
+ &w->val, sizeof(w->val));
+ }
+}
diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h
new file mode 100644
index 0000000..2ef7577
--- /dev/null
+++ b/src/drivers/parade/ps8625/ps8625.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __PS8625_H__
+#define __PS8625_H__
+
+void parade_ps8625_bridge_setup(unsigned bus, unsigned chip_base);
+
+#endif
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3751
-gerrit
commit cd968d941559c82bfbb8964166f207cac19bf2f6
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Wed Jun 26 19:42:12 2013 +0800
ec/google: Support ChromeOS EC on SPI bus.
For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface
(see spi-generic.h) to exchange data.
Note: Only EC protocol v3 is supported for SPI bus.
Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
---
src/ec/google/chromeec/Kconfig | 18 ++++++++--
src/ec/google/chromeec/Makefile.inc | 3 ++
src/ec/google/chromeec/ec_spi.c | 65 +++++++++++++++++++++++++++++++++++++
3 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 1c4a7c0..342db3e 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -22,7 +22,21 @@ config EC_GOOGLE_CHROMEEC_I2C_CHIP
config EC_GOOGLE_CHROMEEC_LPC
depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
- bool
- default y
+ def_bool y
help
Google Chrome EC via LPC bus.
+
+config EC_GOOGLE_CHROMEEC_SPI
+ depends on EC_GOOGLE_CHROMEEC
+ def_bool n
+ help
+ Google's Chrome EC via SPI bus.
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+ depends on EC_GOOGLE_CHROMEEC_SPI
+ hex "SPI bus for Google's Chrome EC"
+
+config EC_GOOGLE_CHROMEEC_SPI_CHIP
+ depends on EC_GOOGLE_CHROMEEC_SPI
+ hex
+ default 0
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index 73b5b5e..541bb13 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -1,9 +1,12 @@
ramstage-y += ec.c crosec_proto.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
smm-y += ec.c crosec_proto.c
smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
+smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
romstage-y += ec.c crosec_proto.c
romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
+romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c
new file mode 100644
index 0000000..5525e31
--- /dev/null
+++ b/src/ec/google/chromeec/ec_spi.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <spi-generic.h>
+#include "ec.h"
+#include "ec_commands.h"
+
+#define CROSEC_SPI_SPEED (500000)
+
+static int crosec_spi_io(uint8_t *write_bytes, size_t write_size,
+ uint8_t *read_bytes, size_t read_size,
+ void *context)
+{
+ struct spi_slave *slave = (struct spi_slave *)context;
+ int rv;
+
+ spi_claim_bus(slave);
+ rv = spi_xfer(slave, write_bytes, write_size * 8, read_bytes,
+ read_size * 8);
+ spi_release_bus(slave);
+
+ if (rv != 0) {
+ printk(BIOS_ERR, "%s: Cannot complete SPI I/O\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int google_chromeec_command(struct chromeec_command *cec_command)
+{
+ static struct spi_slave *slave = NULL;
+ if (!slave) {
+ slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS,
+ CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP,
+ CROSEC_SPI_SPEED,
+ SPI_READ_FLAG | SPI_WRITE_FLAG);
+ }
+ return crosec_command_proto(cec_command, crosec_spi_io, slave);
+}
+
+#ifndef __PRE_RAM__
+u8 google_chromeec_get_event(void)
+{
+ printk(BIOS_ERR, "%s: Not supported.\n", __func__);
+ return 0;
+}
+#endif